FR2986925A1 - METHOD AND ELECTRONIC DEVICE FOR GENERATING A VARIABLE CLOCK SIGNAL - Google Patents

Abstract

According to this method, a control input (G) of a retaining propagation logic circuit (1) is repeatedly applied to a resistor generation control (M) and is clocked by means of a reference clock signal ( CLKR) the application of said command (M) to said input (G), using said reference clock signal (CLKR), the application to said input (G) of an erase command from the last hold applied to said input, said logic circuit (1) is commanded to propagate said generated restraint and subsequent erasure of said generated restraint to a restraint output (C) of said logic circuit (1). from one cycle to another of said reference clock signal (CLKR) the command (M) for varying the duration of propagation of said restraint in said logic circuit (1), and generating said variable clock signal (CLKV) from the logic state present on said holdback output (C).

Description

The present invention relates to a method and an electronic device for generating a variable clock signal. In a logic electronic circuit, it may be desirable to vary the frequency of a clock that clockes one or more functional blocks.

Several reasons, which may be cumulative, may dictate such a recourse to a variable clock frequency in a controlled manner: - to provide a counter-measure to hidden channel piracy of DPA (Differential Power Analysis) type, this type driver performing statistical analysis on a collection of samples captured in a synchronized manner with respect to the internal operation of the circuit. Decreasing the possibility of synchronization decreases the efficiency of statistical analysis for a given number of samples; - reduction of the intensity of electromagnetic radiation emitted at a given frequency, by dispersion of the main frequency and its harmonics; - To facilitate the electrical decoupling of the circuit by dispersion of the current consumption peaks. The three reasons given lead to the use of variable frequency clocks, but countermeasure to hacking also requires a random variation of the frequency. In addition, in the latter case, no electrical connection that would be able to convey directly or indirectly such a variable frequency clock signal must be accessible in a simple manner outside the electronic circuit that uses it, in order not to not provide help in synchronizing the captures of an attack.

An electronic device generating a clock signal of variable frequency / period will therefore preferably be in the form of an integrated circuit functional block, because in an integrated circuit it is possible to completely bury a logical architecture.

Furthermore, there is a need to be able to generate variable frequency clock signals of 100 MHz or more in programmable logic integrated circuits of the FPGA (field-programmable gate array) type. For this type of component and at these frequencies, there is no known reliable and easily achievable solution allowing the period and the duty cycle of a high frequency clock signal to be varied within the cycle. to say at the high limit of the speed capabilities of the component, without passing through pins of the component connected to an electronic phase shift circuit.

A specialist in the design of architectures based on FPGA components has at his disposal, for the generation of clock signals, certain functional blocks dedicated to the PLL type (in English "Phase-locked loop") or DLL (in English " Delay-locked loop "). However, these blocks are intended to provide generally fixed frequencies, at most reprogrammable during the operation of the component, and the pitch of possible frequencies is not very thin. PLL blocks can sometimes slightly vary the frequency generated around its base value (spread spectrum technique), but the variation of the frequencies produced is not random or likely to be controlled. to the cycle to make it random. One solution is to create an oscillator based on logical elements. In such a case the propagation times of the signals in the logic elements and the conductive tracks define the period of the oscillator. This solution does not offer a great stability in voltage and temperature, it requires regular calibration a priori complex to achieve and makes regularly unavailable oscillator.

Another solution is to select as one clock signal one of several stably generated in the integrated circuit, but this poses at least one problem that is related to the selected signal change. Since the signals are continuously out of phase but not of a precisely known value since they pass through different paths, switching from one signal to another entails a performance penalty and / or a design complexity to ensure that the duration at high or low state of the clock signal generated, as well as its period, do not fall below the limit value allowed by the logic set clocked by this clock.

In practice, this other solution is not exploitable because it is too complicated to implement to try to guarantee the durations of travel of the signals relative to each other. If the travel times are not properly controlled, this results in a performance penalty due to the time required to pass cleanly from one signal to another without violation of the minimum required time of the generated clock signal. The aim of the invention is to provide a method and an electronic device which make it possible to generate a clock signal whose frequency can be varied, but without too much distance from this frequency of its maximum value in order to penalize as little as possible the logic circuits which depend on the clock signal generated. Indeed, the lower the clock frequency, the lower the performance of the circuits clocked by this clock signal. Too frequent downtime is bad for performance. The invention also aims at providing a method and an electronic device which make it possible to generate a clock signal whose period and the duty cycle can be controlled to the cycle in such a way that the period of the clock signal is not less than to a desired minimum value. The invention also aims at providing a method and an electronic device that make it possible to generate a clock signal whose period and the duty cycle are also variable in a random or pseudo-random or deterministic manner, depending on the quality of the clock. command.

For this purpose, the subject of the invention is a method of generating a variable clock signal comprising the following steps: repetitive application, clocked by means of a reference clock of fixed period, a restraint generation control at a control input of a restrained propagation logic circuit, - repetitive application, clocked by means of said reference clock signal, at said input of an erase control of the last restraint applied to said logic circuit; - controlling said logic circuit to propagate said generated restraint and subsequent erasure of said generated restraint to a retaining output of said logic circuit; - changing from one cycle to another of said reference, the command applied to said logic circuit to vary the propagation time of said restraint in said logic circuit, and - generating said variable clock signal from of the logic state present on said holding output. This method makes it possible in a very simple manner to generate a clock signal whose frequency can be varied without taking this frequency too far from its maximum value. It should be understood that the change from one cycle to another of the command applied to the logic circuit does not mean that this command is necessarily modified at each cycle. The command can remain the same for several consecutive cycles and the variable clock signal can not be modified on these consecutive cycles, until a modification of the control, therefore of the restraint, and consequently of the temporal characteristics the clock signal intervenes. According to a possible characteristic of the invention, said retaining and erasure generation commands of the last retaining are applied to said logic circuit respectively on a first edge and on the next edge of the same cycle of said reference clock signal. . The timing of the generation and erasure of a restraint are therefore particularly simple to implement. According to another possible characteristic of the invention, said retaining propagation logic circuit comprises cells of different weights each belonging to the group comprising adders and subtracters, each cell comprising at least two control inputs one of which receives said a retaining generation control, a retaining inlet and a retaining outlet connected to the retaining input of the adjacent higher weight cell, the retaining output of the heaviest weight cell constituting said retaining output of said retaining output logic circuit. The process can be implemented by the use of inexpensive and widely available components. According to another possible characteristic of the invention, said control is adapted to cause the generation of a restraint by a single one of said cells. The generation of a restraint is thus particularly simple. Generating only a single restraint leads to a simple system and the effort of focusing is minimal during the realization. According to another possible characteristic of the invention, a holdback different from that generated in the previous cycle is generated by a cell of lower weight than that of the cell that has generated the previous hold. This makes it possible to ensure that the duration of the high state and the duration of the low state of each of the periods of the variable clock signal never fall below a predetermined value. According to another possible feature of the invention, said method comprises at least one quiescent cycle, devoid of application of a hold generation command to said logic circuit, between a hold generation command applied to a cell and a restraint generation control applied to a cell of higher weight. These idle cycles make it possible to avoid that an inversion of the order of output of the detentions occurs with respect to their order of creation, or that the period of the variable clock signal falls below the minimum value allowed. . According to another possible characteristic of the invention, said adders and subtracters are of the two base operating type. This mode of operation in base two facilitates the implementation of the method in and / or with the most common logic integrated circuits. According to another possible characteristic of the invention, said variable clock signal is generated by inverting its logic level on each of the active edges of the signal at the holding output of said logic circuit, an active edge being constituted by one of the two edges of a cycle of said signal at the holding output. This generates a variable clock signal whose period is at least twice that of the reference clock signal CLKR, and whose duty ratio is 50% at the maximum frequency but may be different from 50% at other frequencies. The invention also relates to an electronic device for implementing the method defined above, this device comprising: - a clock for the generation of a reference clock signal of fixed period, - a logic circuit to carry propagation comprising cells of different weights each belonging to the group comprising adders and subtracters, each cell comprising at least two control inputs, a holding input and a holding output connected to the holding input of the adjacent cell higher weight, - a control circuit clocked by said reference clock signal for: - applying to said retention propagation logic circuit a restraint generation command and an erase control of said restraint subsequent to its generation, controlling the propagation by said cells, up to the retaining outlet of the cell of the heaviest weight, of a reservoir enumerated and erasing said restraint, - changing from one cycle to another of said reference clock signal said command for varying the propagation time of said restraint by said logic circuit, and - an output circuit for generating said variable clock signal from the logic state present at said retaining output of the highest weight cell. The device according to the invention requires only a minimum of unsophisticated and inexpensive components to make a variable frequency clock generator. As indicated above, the control circuit does not necessarily modify, at each cycle of the reference clock signal, the command it applies to the carry propagation logic circuit. The command can remain the same for several consecutive cycles and the variable clock signal can not be modified on these consecutive cycles, until a modification of the control, therefore of the restraint, and consequently of the temporal characteristics the clock signal intervenes. According to one possible characteristic of the invention, said control circuit is adapted to prohibit, during at least one cycle of said reference clock signal, the application of a carry generation command to said carry propagation logic circuit between a hold generation command applied to a cell and a hold generation command applied to a higher weight cell. This arrangement ensures that the periods of the variable clock signal never fall below a predetermined value. According to another possible characteristic of the invention, said control circuit is adapted to apply to said logic circuit a command for the generation of said restraint by a single one of said cells. The structure of the device for implementing such a feature is particularly simple to implement. According to another possible characteristic of the invention, each of said cells comprises two operand inputs and said control circuit comprises a first register whose parallel outputs are connected to one of the two operand inputs of said cells respectively. The structure of the device for implementing such a feature is particularly simple to implement.

According to another possible characteristic of the invention, said control circuit comprises a second register controlling the contents of the first register to ensure, from one cycle to another of said reference clock signal, an offset of said command such as said Retention is generated by a cell of weight at most equal to that of the cell that generated the previous hold. The structure of the device for implementing such a feature is particularly simple to implement. According to another possible characteristic of the invention, said control circuit controls the erasure of the contents of said first register in the same cycle of said reference clock signal as that in which a command has been loaded in said first register. The control of the device is thus particularly simple. According to another possible characteristic of the invention, said control circuit applies to the other operand input of each of said cells the same logic level as that of said restraint. Such a very simple control makes it possible to ensure the propagation of a restraint applied to any cell when the latter does not generate itself any restraint. According to another possible characteristic of the invention, said control circuit applies a constant logic level to the retaining input of the least significant cell of said logic circuit. Such a very simple control makes it possible to ensure the propagation of a restraint applied to any cell. According to another possible characteristic of the invention, said output circuit comprises a T-type flip-flop connected to said retaining output of said logic circuit for inverting at its output the logic level of said variable clock signal on each of the active edges of the signal. at the holding output of said logic circuit, an active edge being constituted by one of the two edges of a cycle of said signal at the holding output. Such a T-type flip-flop makes it very easy to generate the variable clock signal from the output C of the adder 1. Moreover, when the clock input of the T-flip-flop is the only input of the circuit which is wired to the output C of the adder 1, this has the great advantage of avoiding any problem of clock competition since the connection is without branching. Other features and advantages of the invention will emerge from the following description of an embodiment given solely by way of example and illustrated by the appended drawings in which: FIG. 1 is a block diagram illustrating an adder propagation propagation device used in an electronic device according to the invention for generating a clock signal with a period and a duty cycle which are variable in a controlled manner; FIG. 2 is a simplified diagram showing basic components of a clock signal generating electronic device according to the invention using the carry propagation adder of FIG. 1; FIG. 3 is a more detailed view of an electronic device generating a clock signal according to the invention based on a binary adder with propagation propagation; FIG. 4 is a truth table illustrating the operation of a cell of the retention propagation bit-adder of FIG. 3; FIG. 5 is a timing diagram illustrating the operation of the electronic clock signal generating device according to the invention; FIG. 6 is a timing diagram illustrating, in different cases, the idle cycles generated by the electronic device according to the invention; FIG. 7 is a circuit diagram according to an exemplary embodiment of the shift register 4 looped back on itself of FIG. 3; FIG. 8 is a circuit diagram according to an exemplary embodiment of the control logic circuit 9 of FIG. 3; and FIG. 9 is a truth table illustrating the operation of a 3-bit to 2-bit code converter present in the circuit of FIG. 8. Referring to FIGS. 1 and 2, an electronic device for generating a Controlled variable clock period and duty cycle signal comprises a delay line consisting of a carry propagation adder 1 having K U cells whose U1, U2 UK_i, UK cells have been shown in FIG. adder 1 is connected by some of its inputs (directly as shown or, alternatively, indirectly via combinational logic) to the outputs of a register 2 clocked by a reference clock signal CLKR period TCLKR and a suitable duty cycle. The acceptable values of the duty cycle depend on the technological constraints of implementation of the device. The output C of the adder 1, which is its retaining output, is connected (directly as shown in the drawing or, alternatively, via combinational logic) to the input of a flip-flop 3 of the T-type (or circuit functionally equivalent) which, as will be described hereinafter, generates at its output a variable period clock and duty cycle clock signal CLKV hereafter referred to as a variable clock signal.

The adder 1 with propagation of restraint (also called sequential adder, and "carry propagate adder" or "ripple carry adder" in English) makes it possible to add two numbers whose numbers are expressed in a certain base according to the type of the cells of the adder. In the example of the adder 1 of FIG. 3, the numbers are expressed in base 2. Each addition cell U of the adder 1 comprises inputs P and G to which the numbers to be added are applied, an input of Cl restraint and a CO restraining outlet. The K addition cells U of the adder 1 are connected together in pairs by the retaining path: the outgoing retention on the holding output CO of a cell U is at the same time the incoming restraint on the input Cl restraint of the neighboring cell of higher weight. In the example shown, the cell U1 is of greater weight than the cell U2, which is itself of greater weight than the cell U3, etc. Each cell U adds the values of its two inputs P and G with the value of its holding input C1, and provides the resultant sum on its output S (not shown because it is not used in the context of the present invention) and the outgoing containment on its CO output.

In the context of the present invention, the adder 1 designates as well an adder itself as a combined subtractor or adder-subtractor, with propagation propagation, considering that a subtractor is a special form of adder, namely an adder whose one of the operands sees its opposite value with respect to zero. The adder 1 has a retaining inlet CN which is the retaining input C1 of the UK cell of the lowest weight. This NC input is wired to a fixed logic value 0 or 1 which allows the carry propagation in the adder 1 without this input itself generating hold.

Moreover, each cell U has its input P wired so that the cell propagates in its output CO the value of its input C1. As a variant, the adder 1 can also be constituted and wired in such a way that a cell U propagates in its output CO the complementary value of its input Cl, in order to make the propagation time of a retaining flowing over the same distance in 1 constant, whether it is originally 0 or 1. In fact, according to the technology employed, the duration of propagation of a logic level 1 in a cell may be different from that of a logic level 0. The outgoing retaining in C of the adder 1 is used for the generation of the clock signal CLKV to variable period and duty cycle.

The adder 1 is used in a delay line in that a hold is generated in one of the cells U, by establishing an appropriate value on the input G of said cell U, and propagates on the along the adder 1 until output in C. Thus, the total propagation time of the created retainer depends on the number of cells crossed, therefore the position of the generation cell. In the case where several inputs G are simultaneously controlled so that the respective cells U each generate a restraint, then it is the restraint generated by the strongest cell that is propagated to C, because a restraint created is absorbed by a cell of higher weight that generates its own restraint. The inputs G of the adder 1 are fed by the register 2 clocked by the reference clock signal CLKR. This register 2 stores at the same time K values whose set is called command M. These K values (K bits in the case of an adder in base 2) are each the value supplied to the input G of a cell U and the device is physically arranged such that the delay between the occurrence of a command M in the register 2 and its arrival in the corresponding U cell is the same for the K command-cell pairs. When the register 2 does not contain any command making it possible to generate a hold in the adder 1, then no hold is generated in the adder 1 which may nevertheless still be propagating a previously created retainer, and / or by train to propagate the erasure of the restraint. The deletion of a restraint is in fact the propagation in the adder 1 of a retaining logic level complementary to that of the restraint that was previously circulating. For example, if a logical level 1 hold has been controlled by the register 2 and then generated and propagated by the adder 1, then the erasure of the hold consists of the erasure of the contents of the register 2 and the propagation which followed by a logic level 0 hold. The operating polarities of the adder 1 can quite well be adapted such that the generated resistor is of logic level 0 and that of logic level deletion 1. As previously described the detentions can also be of alternating logic levels along the adder 1, by causing the inversion of the logic level by certain U cells of the propagation path. The restraint C coming out of the adder 1 is used as a clock signal of the flip-flop 3 which inverts the state of its output Q on each active edge of this clock signal. The active edge may be the rising edge or the falling edge, depending on the implementation chosen for the device and in particular the logic level of the generated output at C output. The output of the flip-flop 3 is the CLKV clock signal. variable TCLKV period and variable duty cycle. One of the edges of the reference clock CLKR, rising or falling, is used to register in the register 2 the holding generation command presented on its input D, while the next rising or falling edge triggers the erasure of the contents of the register 2, thus the erasure of the restraint. The erasure of the contents of the register 2 is controlled by the reset input R, which is asynchronous because of the immediate effect independent of the clock input. Therefore, by cycle of the reference clock signal CLKR, it can be generated in the adder 1 a retainer and its erasure. On the timing diagram of FIG. 5, it is assumed that the level reservoirs "1" and "0" propagate at the same speed because at the output C of the adder 1 the state "1" lasts the same time as the state "1" of the reference clock signal CLKR. On this timeline, propagation delays are such that 42> A1, 43> A2 and 44> A3. The general case which must be respected is AnAl, 4342 and 44> .43, etc. If the hold in adder 1 is always generated in the same cell U, i.e. if the delay A is constant from one cycle to the next of the reference clock signal CLKR, then the TCLKV period value is simply twice that of TCLKR, and the duty cycle of CLKV variable clock signal is 50%. At the time tc1 a front of a cycle of the reference clock signal CLKR creates at time t1, with a delay A1, an active edge of the clock signal present at the output C of the adder 1 and the time t02 a homologous front of a second cycle of the reference clock signal CLKR is necessary to create at the output C of the adder 1 at time t2, with a delay 42, a second active edge of the clock signal acting on the flip-flop 3. The CLKV output of the flip-flop 3 goes high on the first of the two aforementioned active fronts and returns to the low state on the second of the aforementioned active fronts. Two periods of the reference clock signal CLKR thus create at the output Q of the flip-flop 3 a complete period of the variable clock signal CLKV. Similarly, at the time tc3 a homologous front of a third cycle of the reference clock signal CLKR created at the output C of the adder 1 at time t3, with a delay 43, a third active edge of the clock signal acting on the rocker 3.

At time tc5, a rest period corresponding to five cycles of the reference clock signal CLKR without control applied to adder 1 is generated because it is assumed here that with 44 the end of the delay line constituted by the adder 1 is reached. This rest period is ended at the time tclo with the submission to the adder 1 of a new hold generation command. The time tfpr marks the end of propagation of the deductions during the rest period. At the time tc10 the retaining generation resumed results in the appearance of an active edge of the clock signal at the output C at time t5, with a delay 410, and so on. Whenever a logic level resistor 1 is applied by the output C of the adder 1 to the clock input of the flip-flop 3 at times t2 = tc2 + 3,2, t3 = -t3 + 43, t4 = tc4, A4, t574,10,410, t6 = tc11 + 3,11, t7 = t, 12, Al2 this triggers the tilting of the flip-flop 3, therefore the inversion of the logic state at its output Q which constitutes the signal variable clock CLKV. The length of the adder 1, in number of U cells, is chosen according to the technology of the circuits used, ensuring that a retaining generated by the register 2 can not be caught, and thus erased, by the following restraint (commanded or erased) generated by the register 2 before reaching the output C. In an adder of sufficiently large length, such a retrofit can occur if a restraint propagates faster to a logical level than to another. Preferably, for the greatest simplicity of design, the length of the adder 1 is chosen such that the maximum duration of propagation of the restraint in the adder 1, whatever the level of the restraint, is less than half -value of the period of the TCLKR reference clock signal. For clarity of the drawing, this is not the solution that has been retained in the example illustrated by the timing diagram of FIG. 5. With a duty ratio of the reference clock signal CLKR of 50%, then no catching up is possible. can occur because the erasure hold is generated when the previous hold, the commanded hold, is already output at C. Similarly, in this case, the commanded hold is generated when the previous hold, the erasure hold, is already output C. Alternatively, as for example in the case of Figure 5, the length of the adder 1 can be chosen such that several restraints circulate at the same time provided that a restraint can never catch the previous.

The device described is adapted so that the clock signal CLKV can be produced with variable duty cycle and period, with each of the two logic levels of the clock signal CLKV of duration at least equal to the value of the period TCLKR. Thus the TCLKV period will never be less than twice the TCLKR period.

For this purpose, the register 2 receives a content which is such that in a reference clock cycle CLKR, with respect to the preceding cycle, the retaining generation cell U is the same or a cell of lower weight. Thus, the delay of propagation of the restraint in the delay line formed by the adder 1 is identical or increasing from one cycle to another.

From one cycle to the other of the reference clock signal CLKR, the control of the register 2 makes it possible to choose the number of cells U of the adder 1 to be added in the path of the generated resistor. This number of U cells to be added in the path is called offset. When the desired offset causes the new retaining generation position to pass the end of the adder 1, i.e., is beyond the least significant U cell, the register 2 does not. is not allowed to load the new command. At least one idle cycle of the adder 1 is then imposed during which no new restraint is created or propagated. Such a rest cycle is illustrated in the timing diagram of FIG. 5, where the register 2 contains no control and thus does not generate by the adder 1 any restraint between the times t .5 and -cl O. In the cycle of the CLKR reference clock signal that follows the rest, the register 2 is again authorized to load a command M. This new command M indicates a position of generation of the restraint in any of U1 cells U2 UK since, of At rest cycle (s), the desired minimum duration for the current logic level of the CLKV variable clock signal is guaranteed.

The minimum number of idle cycles clocked by the reference clock signal CLKR when the end of the adder 1 is exceeded depends on the maximum propagation time of the detentions in the entire length of the adder 1 and the value of TCLKR. Indeed, before being able to re-order the generation of a new hold in cell U1 or one of its close neighbors, it is imperative that no more restraint is circulating in the adder. It must also be ensured that the delay between the edges of the signal at the output C of the adder 1 is acceptable for the flip-flop 3 or any other output logic circuit fed by the output C. As many rest cycles as there are times the value of TCLKR in the maximum propagation time in adder 1 must be imposed. The larger integer value of the result is taken into account. For example, if adder 1 has a maximum propagation time of 70ns while TCLKR = 5Ons, then at least two rest cycles of CLKR should be imposed because 70/50 = 1.4. The timing diagram of FIG. 6 illustrates various examples of idle times as a function of the relative value of the maximum propagation delay of a hold in adder 1 and the period TCLKR of reference clock signal CLKR. From the value of the cycle-controlled shift of the reference clock signal CLKR arise both the duty cycle of the variable clock signal CLKV and its period TCLKV. The described device has the advantage that the offset is programmed, synchronously and by means of a single clock signal CLKR, in each cycle of the reference clock signal CLKR, outside the idle cycle. The successive numbers loaded in the register 2 represent the position of generation of a restraint in this register. If this position varies to a lower weight cell (s) than the previous cycle, then there is offset. The numbers representative of the offset value, which induce variations in the TCLKV period and the duty cycle of the variable clock signal CLKV, may be deterministic, random, or pseudo-random values. The unavailability during the rest cycles of the delay line constituted by the adder 1 causes the variable clock generator device described to be of most interest when the variable clock signal CLKV produced must vary the most. possible in the vicinity and within the limit of a maximum frequency 1 / (2xTCLKR), without the need for other specific temporal characteristics. The device is in this case all the more interesting that the dispersion of propagation times of the retention in and between the U cells is important. Another important feature of the device is the lack of need for calibration. Indeed, the length of the adder 1 can be determined without any experimentation, simply by referring to the data sheet of the selected electronic component or components. The indicated performance of an adder makes it possible to deduce its maximum propagation time per cell. The length of the adder 1 is then chosen as a function of the period of the reference clock signal CLKR, this period being itself chosen according to the frequency performance of the logic block to be clocked. Due to the operating principle of the device, any logic block 20 which can be clocked by a TCLKR x 2 period clock can be clocked by the variable clock signal CLKV produced, insofar as this block has no constraint of a clock signal other than the maximum frequency of the latter and that it does not require a duty cycle different from 50% at this maximum frequency. The device shown in FIG. 3 is built around a binary adder 1. In the latter, each cell U is a full adder of three bits ("Full Adder" in English) which performs the addition of three values each on 1 bit. This adder is the one commonly found in FPGA integrated circuits. The NC input of the adder 1 is fed by the constant value '0' so as not to generate a hold by this input.

The input P of the adder 1 has its K bits set to 1, thus allowing each of the cells U to propagate on its holding output CO the incoming hold received on its input C1 or to generate a hold on this holding output CO, according to the value of the input G, as is apparent from the table of FIG. 4. The input G of the adder 1 is supplied directly by the register 2 of width K bits. The register 2 presents to the adder 1 either all of its bits at '0', a bit at '1' and all the others at '0'. The bit at '1' is the one that controls a retaining generation in the U cell of 1 that it feeds.

The register 2 is fed by a register 4 of width K bits. The register 4 is a shift register looped back on itself and which contains a single bit of value '1', all the others being at '0'. The register 4 makes it possible to shift its contents by a certain number of bits per cycle of the reference clock signal CLKR, this number of bits being the desired offset of the position of generation of the restraint in the following cycle of the signal of reference clock CLKR (ie once register 2 has captured the contents of register 4). The reset input of the register 2 is connected to the output of a NOR gate 5. One of the inputs of the NOR gate 5 receives the reference clock signal CLKR, while its other input is connected to the output of a flip-flop 6 of the D type. The clock input of the flip-flop 6 is connected to the output of an inverting gate (NO) 7 to which the reference clock signal CLKR is applied as input, while its data entry is at a logical level '1'. The asynchronous reset input R of flip-flop 6 is connected to the output of an AND gate 8, one of whose inputs receives the reference clock signal CLKR while its other input is connected to the output of FIG. the flip-flop 6. The register 2 loads the content applied to it by the register 4 on the rising edge of the reference clock signal CLKR which is applied to its clock input, then is reset on its input R by the NOR gate 5 whose output goes to '1' consecutively to the falling edge of the reference clock signal CLKR.

The erasure signal of the register 2 generated by the NOR gate 5 is then deactivated by the output of the flip-flop 6 which has changed to the following one at the falling edge of the reference clock signal CLKR (transformed into a rising edge by the door 7).

For the next rising edge of the reference clock signal CLKR, the register 2 is then again ready to capture the contents of the register 4. In effect, the flip-flop 6 is erased (its output is reset to zero) by the output of FIG. the AND gate 8, following the rising edge of the reference clock signal CLKR. The flip-flop D 6 therefore applies a level '0' to one of the inputs of the NOR flip-flop 5, while the other input thereof, which receives the reference clock CLKR, is at level 1 . The role of the flip-flop 6 is simply to deactivate the erase signal of the register 2 produced by the NOR gate 5 so that the register 2 can record new content at the next rising edge of the reference clock signal CLKR.

A synchronous logic control circuit 9 with respect to the reference clock signal CLKR checks at each cycle of the reference clock signal CLKR the position of the bit at '1' in the register 4, and controls the amplitude of the offset. This same control circuit also imposes the sleep cycle (s) at the registers 4 and 2 when the desired offset causes the '1' bit to pass through the loopback of the register 4 on itself. The rest of the registers 4 and 2 is passively controlled by the non-activation of their input CE represented in the diagram, that is to say by the absence of logic level 1. The input CE is the conventional authorization input loading by the clock ("Clock Enable" in English). The amount of offset applied to each cycle depends on the type of variation of the desired clock signal. The control circuit 9 receives or creates values according to the desired result for the variable clock signal CLKV. The synchronous control logic circuit 9 makes it possible, for example, to interfere with a microprocessor or with a random number generator in order to vary the period TCLKV and the duty cycle of the variable clock signal CLKV randomly. FIG. 7 represents a circuit constituting an exemplary embodiment of the shift register 4 of FIG. 3. The circuit 4 comprises K multiplexers MUX, with 1 K, of which only three MUX1, MUX1 and MUXK have been represented in the drawing. Each multiplexer MUX1 has, in the specific example of FIG. 7, four inputs connected to certain bits of the Q output of K bits of a register 10.

The SEL selection input of the MUX multiplexers is coded on two bits. The selection value SEL is applied to the multiplexers MUX1 by the control circuit 9 of FIG. 8. The register 10 is powered by the outputs Di of the K multiplexers MUXi. The selection value 0 of SEL selects the Q bit, the Q output, the selection value 1 selects the Qi_i bit, the selection value 2 selects the Q.2 bit, the selection value 3 allows to select the Q1-3 bit In this example, the value of SEL corresponds directly to the desired offset for the next hold generation position in the adder 1. The SEL input is common to all the MUX1 multiplexers. This is enabled by the fact that a single bit of the output Q of the register 10 has the value "1". This bit will therefore be shifted from zero to three positions in the register 10, and all the other bits of the register 10 will also be shifted by the same number of positions, but they are bits having the value '0'. After each cycle of the clock CLKR, and therefore each global offset of the register 10, there is always only one bit to '1' in the register 10. The register 10 self-initializes at start-up of the device with at its output Q one of the bits and only one at the value "1", and all the other bits at the logical value "0". With this arrangement, the circuit 4 does not need data inputs. FIG. 8 represents a circuit constituting an exemplary embodiment of the synchronous control logic circuit 9 of FIG. 3. The circuit 9 comprises a register 11 whose input ST is connected to the output Q of a generator 12 of numbers of two bits. The input ST indicates the desired offset in number of cells U of the adder 1. The output Q of the register 11 is connected to the input SEL of the shift register 4, that is to say at the input SEL of each of the multiplexers MUX1 to MUXK.

The output Q of the register 11 is also connected to one of the inputs OH of a binary adder 13 whose output C is applied to the input of an AND gate 14. The other input of the AND gate 14 is connected at the output of a flip-flop D 15. The flip-flop D 15 receives as input, on the one hand the clock signal CLKR, and on the other hand the output of the adder 13 inverted by an inverter 16. The output of the AND gate 14 is connected to the EC inputs of the register 11 and the register 4, while the EC input of the register 2 is connected to the output of the D flip-flop 15. The circuit 9 is completed by a converter 17 which converts a code three bits in a two-bit code according to a combinational logic whose truth table is represented in FIG. 9. The converter 15 receives on its input IN a value MPFA representing the least significant bits MK-2, MK-1, MK of the command M applied by the register 2 to the adder 1. The output of the converter 17 is connected to the second input OP2 of the adder 13. The adder 13 has the effect that, when its holding output C is "1", a rest cycle is imposed on the device. In the present embodiment, the adder 13 is sized to require only a rest cycle in case of exceeding the end of the adder 1. In the example of Figure 8, the number generator 12 two bits and a binary counter. It comprises a two-bit binary adder 18 whose output is connected to the input D of a register 19 whose output Q coded on two bits constitutes the input of the register 11. The output Q of the register 19 is also connected to the one of the inputs OP1 of the adder 18 whose other input has its value set to "01". The output Q of the generator 12 is synchronized with the clock CKR whose signal is applied to the clock input of the register 19. In each clock cycle, the contents of the register 19 are incremented by the value "1" which is the fixed value present on the input OP2 of the adder 18. The two-bit number generator circuit 12 can also be a random number generator, a pseudorandom number generator, a correspondence table connected to a counter to generate a determined sequence of numbers of offsets, a microprocessor controlled register, etc.

Numerous variations are possible with respect to the embodiment of the invention described above by way of example. Thus: the use of the fronts of the reference clock signal CLKR can be reversed throughout the device, that is to say that the falling edges are used in place of the rising edges, and vice versa. versa; the delay line may be constituted by a subtractor or a combined adder-subtractor assembly, as long as the principle of propagation of restraint is preserved; the delay line may be of another type, operating by propagating '0' as a restraint and then '1' for erasing this restraint; in this case the flip-flop 3 uses the falling edge of the restraint C; the delay line may be of another type in which the propagated restraint takes the form of a succession of '1' and '0'; the delay line can operate in a base different from 2; the delay line may be of a type propagating a hold composed of several bits; the cells U composing the delay line may not all be logically identical; the flip-flop 3 can be replaced by a set of several flip-flops and / or the combinational logic, all performing the same function of switching the output state to produce the clock signal CLKV; the path between the output C of the delay line and the flip-flop 3 may include combinational logic; the path from register 2 to the delay line may include combinational logic.

Claims (17)

REVENDICATIONS1. A method of generating a variable clock signal characterized in that it comprises the following steps: repetitive application, clocked by means of a reference clock clock (CLKR) of fixed period (TCLKR), a command (M) for retaining generation at a control input (G) of a retaining propagation logic circuit (1), repetitive application, clocked by means of said reference clock signal (CLKR), at said input ( G) an erase command of the last hold applied to said logic circuit (1), controlling said logic circuit (1) to propagate said generated hold and subsequent erasure of said generated hold to a hold output ( C) of said logic circuit (1), changing, from one cycle to another of said reference clock signal (CLKR), the command (M) applied to said logic circuit (1) to vary the propagation time of said retention in said logic circuit (1), and generative ion of said variable clock signal (CLKV) from the logic state present on said holdback output (C). 2. Method according to claim 1, characterized in that said commands for generating retaining and erasing the last retaining are applied to said logic circuit (1) respectively on a first front and on the next edge of the same cycle of said reference clock signal (CLKR). 3. Method according to any one of claims 1 and 2, characterized in that said logic circuit (1) retaining propagation comprises several cells (U) of different weights each belonging to the group comprising adders and subtracters, each cell (U) comprising at least two control inputs (P, G) one of which receives said restraint generation control (M), a restraint input (C1) and a restraint output (CO) connected to the input retaining (Cl) of the adjacent cell of higher weight, the retaining output of the cell (U1) of the highest weight constituting said retaining output of said logic circuit (1). 4. Method according to claim 3, characterized in that said control (M) is adapted to cause the generation of a restraint by a single one of said cells (U). 5. Method according to claim 4, characterized in that a retention different from that generated in the previous cycle is generated by a cell (U) of lower weight than that of the cell that generated the previous hold 6. Method according to claim 5, characterized in that it comprises at least one idle cycle, devoid of application of a carry generation command to said logic circuit (1), between a carry generation command applied to a cell (U) and a retaining generation control applied to a cell (U) of higher weight. 7. Method according to any one of claims 3 to 6, characterized in that said adders and subtracters are of the type based on two base. 8. Method according to any one of claims 1 to 7, characterized in that said variable clock signal (CLKV) is generated by inverting its logic level on each of the active edges of the signal at the holding output (C) of said logic circuit, an active edge being constituted by one of the two edges of a cycle of said signal at the holding output (C). 9. Electronic device for implementing the method according to any one of claims 1 to 8, characterized in that it comprises: - a clock for generating a reference clock signal (CLKR) period fixed (TCLKR), - a retaining propagation logic circuit (1) comprising cells (U) of different weights each belonging to the group comprising the adders and the subtractors, each cell (U) comprising at least two control inputs (P); , G), a holding inlet (C1) and a holding outlet (CO) connected to the holding inlet (C1) of the adjacent higher-weight cell, - a control circuit (2, 4, 9) clocked by said reference clock signal (CLKR) for: - applying to said retention propagation logic circuit (1) a restraint generation command and an erase control of said restraint subsequent to its generation, - controlling the propagation by said cells (U), up to u'à the retaining outlet (C) of the cell (U1) of the highest weight, a retaining generated and the erasure of said retaining, - change from one cycle to another of said clock signal reference (CLKR) said command (M) for varying the duration of propagation of said hold by said logic circuit (1), and - an output circuit (3) for generating said variable clock signal (CLKV) from from the logic state present at said retaining output (C) of the cell (U1) of highest weight. 10. Device according to claim 9, characterized in that said control circuit (2, 4, 9) is adapted to prohibit, during at least one cycle of said reference clock signal (CLKR), the application of a resistor generation control for said carry propagation logic circuit (1) between a hold generation command applied to a cell (U) and a carry generation command applied to a higher weight cell (U). 11. Device according to any one of claims 9 and 10, characterized in that said control circuit (2, 4, 9) is adapted to apply to said logic circuit (1) a command (M) for the generation of said restraint by only one of said cells (U). 12. Device according to any one of claims 9 to 11, characterized in that said control circuit comprises a first register (2) whose outputs are respectively connected to one of the operand inputs (G) of each of said cells (U). 13. Device according to claims 11 and 12, characterized in that said control circuit comprises a second register (4) controlling the contents of the first register (2) to ensure, from one cycle to another of said clock signal of reference (CLKR), an offset of said control (M) such that said restraint is generated by a cell (U) of weight at most equal to that of the cell having generated the previous restraint 14. Device according to any one of claims 12 and 13, characterized in that said control circuit (2, 4, 9) controls the erasure of the contents of said first register (2) in the same cycle of said clock signal reference (CLKR) than that in which a command (M) has been loaded in said first register (2). 15. Device according to any one of claims 9 to 14, characterized in that said control circuit (2, 4, 9) applies to the other operand input (P) of each of said cells (U) the same logical level than that of said restraint. 16. Device according to any one of claims 9 to 15, characterized in that said control circuit (2, 4, 9) applies a constant logic level to the holding input (Cl) of the cell (UK) of lowest weight of said logic circuit (1). Device according to any one of claims 9 to 16, characterized in that said output circuit comprises a T-type flip-flop (3) connected to said holding output (C) of said logic circuit (1) for inverting at its output (Q) the logic level of said variable clock signal (CLKV) on each of the active edges of the signal at the holding output (C) of said logic circuit, an active edge being constituted by one of the two edges of a cycling said signal to the holding output (C).