FR2972202A1 - Forming semiconductor structure e.g. electronic device structures e.g. transistors, comprises forming III-V semiconductor layer on substrate, and forming an indium-III-V semiconductor layer on growth surface of III-V semiconductor layer - Google Patents

Abstract

The method comprises forming a III-V semiconductor layer (130) on a substrate (110), and forming an indium (In)-III-V semiconductor layer (140) on a growth surface of the III-V semiconductor layer with an In solid phase concentration above an In saturation regime by combining an In precursor, a group III element precursor different from the In precursor and a group V element precursor in a processing chamber configured with an In super-saturation regime that includes a chamber temperature that is lower than a chamber temperature corresponding to the In saturation regime. The method comprises forming a III-V semiconductor layer (130) on a substrate (110), forming an indium (In)-III-V semiconductor layer (140) on a growth surface of the III-V semiconductor layer with an In solid phase concentration above an In saturation regime by combining an In precursor, a group III element precursor different from the In precursor and a group V element precursor in a processing chamber configured with an In super-saturation regime that includes a chamber temperature that is lower than a chamber temperature corresponding to the In saturation regime, selecting the group V element precursor to include ammonia and trimethylindium, and selecting the group III element precursor to include triethylgallium. The In-III-V semiconductor layer has a thickness that is greater than a critical thickness. The step of forming the In-III-V semiconductor layer comprises decreasing a desorption flux of In from V-pit sidewalls of the In-III-V semiconductor layer relative to a desorption flux of indium from the growth surface of the In-III-V semiconductor layer, increasing an incorporation of In in V-pit sidewalls relative to an incorporation of In in the growth surface of the Indium-III-V semiconductor layer, increasing an In partial pressure in the processing chamber relative to an overall group III partial pressure, and forming an indium gallium nitride layer. The step of increasing the incorporation of In in the V-pit sidewalls comprises decreasing the chamber temperature, increasing a chamber pressure, and/or increasing an In partial pressure. An independent claim is included for a semiconductor structure.

Description

FIELD Embodiments of the present invention generally relate to III-V semiconductor structures and methods of forming III-V semiconductor structures.

Background III-V semiconductor materials, such as, for example, group III arsenides (eg, gallium indium arsenide (InGaAs)), group III phosphides (e.g., phosphide gallium indium (InGaP)) and group III nitrides (for example, gallium indium nitride (InGaN)) can be used in a number of electronic device structures. Some exemplary electronic devices are switching structures (e.g., transistors, etc.), light-emitting structures (e.g., laser diodes, light-emitting diodes, etc.), light-receiving structures. (For example, waveguides, separators, mixers, photodiodes, solar cells, solar sub-cells, etc.), and / or microelectromechanical system structures (e.g., accelerometers, pressure sensors, etc.). These electronic device structures containing III-V group semiconductor materials can be used in a large number of applications. For example, these device structures are often used to produce radiation (eg, visible light) at one or more of various wavelengths. The light emitted by these structures can be used not only for lighting applications, but can also be used in multimedia storage and retrieval applications, communication applications, printing applications, spectroscopy applications, multimedia applications, and other applications. biological agent detection applications and image projection applications. In more detail, the InGaN layer can initially develop "pseudomorphically" on the underlying substrate, so that a network parameter of the InGaN layer is brought (eg, forced by atomic forces) to correspond substantially to a network parameter of the underlying substrate on which it is developed. An absence of correspondence between the networks of the InGaN layer and the underlying substrate (for example, GaN) can induce a stress in the crystal lattice of the InGaN layer, and this induced stress can induce a constraint energy. which can increase with increasing thickness of the InGaN layer. As the thickness of the InGaN layer increases during its growth, the stress energy in the InGaN layer can increase until, at a thickness generally called "critical thickness", the InGaN layer increases. InGaN can no longer develop in a pseudomorphic way and may suffer a relaxation of constraints. A relaxation of the stresses in the InGaN layer can result in a deterioration of the quality of the InGaN layer. For example, this deterioration in crystal quality in the InGaN layer may include formation of crystalline defects (eg, dislocations), roughening of an InGaN layer surface, and / or formation of regions of a non-homogeneous material composition.

In some cases, these defects may render the device ineffective. For example, the defects may be large enough to cause a short circuit through a p-n junction of light emitting diodes (LEDs) or laser diodes, so that the light emitting device can not generate the desired electromagnetic energy. There is a need for III-V semiconductor structures and methods for forming these III-V semiconductor structures that have reduced defect densities to enhance the quality of the devices formed therewith. In particular, there is a need for III-V semiconductor structures and a method for forming them which include indium alloyed with other materials to form an indium-containing layer with defect densities. reduced which is relatively thick, which has relatively high indium concentrations, or a combination of these characteristics.

Brief Summary The various embodiments of the present invention generally relate to III-V semiconductor structures and methods for forming these III-V semiconductor structures. For example, in some embodiments, the present invention includes gallium indium nitride (InGaN) structures for forming InGaN structures.

This summary is provided to introduce a selection of concepts in a simplified form which are further described in the following detailed description of some exemplary embodiments of the invention. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. In some embodiments, the present invention includes methods of forming a semiconductor structure comprising forming a III-V semiconductor layer on a substrate and forming a III-V semiconductor layer indium with a reduced V-shaped void density on a growth surface of the III-V semiconductor layer. The III-V-indium semiconductor layer is formed with an indium solid phase concentration above an indium saturation regime by combining at least one indium precursor, a group element precursor. III different from the indium precursor, and a group V element precursor in a processing chamber configured with a super-saturation indium regime which comprises a chamber temperature lower than a corresponding chamber temperature for the saturation of indium. In further embodiments, the present invention includes methods of developing a layer of indium gallium nitride (InGaN). A group III element precursor at a Group III partial pressure is introduced into a treatment chamber comprising a substrate with a III-V semiconductor layer formed thereon. A Group V element precursor at a Group V partial pressure is introduced into the process chamber and an indium precursor at an indium partial pressure is introduced into the process chamber. A III-V-indium semiconductor layer is formed with a decreased V-shaped void density and a thickness greater than a critical thickness by developing a super-saturation indium regime in the process chamber which includes a chamber temperature. less than a corresponding chamber temperature for an indium saturation regime. In further embodiments, the present invention includes methods for determining processing parameters for an InGaN layer. An indium saturation regime is determined for the InGaN layer in a range of indium partial pressure with respect to a combination of a group III element pressure and a temperature and a substantially constant pressure for a treatment chamber. A super-saturation indium regime is determined, which comprises a surface growth temperature below the growth surface temperature for the indium saturation regime, wherein the super-saturation indium regime is sufficient to develop a V-shaped hollow density decreased to a higher indium solid phase concentration.

In further embodiments, the present invention includes a semiconductor structure comprising a substrate and a III-V semiconductor layer formed on the substrate. The semiconductor structure also comprises a layer of InGaN with a decreased V-shaped void density and an indium solid phase concentration higher than an indium solid phase concentration of an indium saturation regime, in wherein the InGaN layer is formed in a super-saturation indium regime with a chamber temperature lower than that for the indium saturation regime. Aspects, details, and other additional combinations of the elements of the embodiments of the invention will be apparent from the following detailed description.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention may be more fully understood with reference to the following detailed description of exemplary embodiments of the present invention, which are illustrated in the accompanying drawings, in which: Figure 1 is a cross-sectional diagram of a semiconductor structure with a substrate, a III-V semiconductor layer and a III-V-In semiconductor layer formed thereon and illustrating dislocations and V-shaped recesses formed therein ; Figure 2 is a simplified isometric diagram illustrating a V-shaped depression in a III-V-In semiconductor layer; Fig. 3 is a schematic cross-sectional diagram of a substrate with a III-V semiconductor layer and a III-V-In semiconductor layer formed thereon and illustrating a decreased density of shaped V-shaped recesses. in these according to one or more embodiments of the invention; FIG. 4 is a solid phase concentration graph of indium versus indium gas phase concentration to illustrate an indium saturation regime in certain indium gas phase concentrations; FIG. 5 is a solid phase concentration graph of indium as a function of the indium partial pressure, showing the saturation regime of FIG. 4 and super-saturation regimes according to one or more embodiments of the invention. ; and FIGS. 6A-6C are graphs illustrating an indium solid phase concentration, a V-shaped cavity density and a V-shaped cavity width, respectively, all with respect to an indium partial pressure in one or more modes. embodiment of the invention.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION The illustrations presented herein are not considered actual views of a particular material, device, or process, but are merely idealized representations that are used to describe embodiments of the present invention. It should be understood that any reference in this document to an element using a designation such as "first", "second", etc. does not limit the quantity or order of these elements, unless this limitation is explicitly stated. Instead, these designations may be used in this document as a convenient method of distinguishing two elements or instances of one or more elements. Thus, a reference to first and second elements does not mean that only two elements can be used here or that the first element must precede the second element in a certain way. In addition, unless otherwise specified, a set of elements may include one or more elements. The elements described in this document may include multiple instances of the same element. These elements may be indicated generically by a digital designator (eg, 110) and specifically indicated by the numerical indicator followed by an alphabetic designator (eg, 110A) or a numeric indicator preceded by a "dash" (e.g. , 110-1). To facilitate understanding of the description, for the most part, the element number indicators begin with the number of the schema on which the elements are introduced or examined most completely. Thus, for example, the identifiers of elements in Figure 1 will be mainly in the lxx digital format and the elements in Figure 4 will be mainly in the 4xx digital format. The following description provides specific details, such as types of materials and processing conditions, to provide a detailed description of embodiments of the present invention and the practice thereof. However, one skilled in the art will appreciate that the embodiments of the present invention can be practiced without using these specific details and in conjunction with conventional manufacturing techniques. In addition, the description provided herein does not form a complete process flow for the manufacture of a semiconductor device or system. Only the process actions and structures necessary to understand the embodiments of the present invention are described in detail herein. The materials described herein may be formed (e.g., deposited or developed) by any suitable technique including, but not limited to, chemical vapor deposition ("CVD"), chemical deposition, and plasma enhanced vapor phase ("PECVD"), atomic layer deposition ("ALD"), plasma enhanced ALD, or physical vapor deposition ("PVD"). Although the materials described and illustrated herein may be formed as layers, the materials are not limited to layers and may be formed in other three-dimensional configurations. The terms "horizontal" and "vertical", as used herein, define the relative positions of elements or structures with respect to a plane or major surface of a semiconductor structure (for example, a semiconductor wafer, matrix, substrate, etc.), regardless of the orientation of the semiconductor structure, and are orthogonal dimensions interpreted with respect to the orientation of the described structure. As used herein, the term "vertical" refers to and includes a dimension substantially perpendicular to the major surface of a semiconductor structure, and the term "horizontal" refers to a dimension substantially parallel to the major surface of the semiconductor structure. semiconductor structure. As used herein, the term "semiconductor structure" refers to and includes any structure that is used for the formation of a semiconductor device. Semiconductor structures include, for example, matrices and semiconductor wafers (for example, support substrates and device substrates), as well as sets or composite structures that include two matrices and / or semi-wafers. -conductors or more integrated three-dimensionally with each other. Semiconductor structures also include fully-manufactured semiconductor devices, as well as intermediate structures formed during the fabrication of semiconductor devices. The semiconductor structures may include conductive materials, semiconductor materials, non-conductive materials (e.g., electrical insulators), and combinations thereof. As used herein, the term "treated semiconductor structure" means and includes any semiconductor structure that includes one or more at least partially formed device structures. The processed semiconductor structures are a subset of semiconductor structures, and all semiconductor structures treated are semiconductor structures. As used herein, the term "III-V semiconductor" refers to and includes any semiconductor material that is at least predominantly composed of one or more Group IIIA elements of the table. periodic (eg, B, Al, Ga, In and Ti) and one or more elements of the group VA of the periodic table (eg, N, P, As, Sb and Bi).

As used herein, the terms "indium gallium nitride" and "InGaN" refer to indium nitride (InN) and gallium nitride (GaN) alloys having the composition InxGalxN, where 0 <x < - 1.

As used herein, the term "critical thickness" refers to the average total thickness of a layer of semiconductor material to which, and beyond which, the pseudomorphic growth is interrupted and the layer undergoes relaxation of the stresses. As used herein, the term "growth surface" refers to any surface of a semiconductor substrate or semiconductor layer upon which further growth of the semiconductor substrate or the semiconductor layer can be performed. As used herein, the term "dislocation" refers to a region of a semiconductor material in which an imperfection of a crystalline structure for the semiconductor material exists, which may be characterized by properties such that for example, missing elements in the crystal structure and broken bonds in the crystal structure. As used herein, the term "substantially" is used herein to refer to a result that is complete except for the deficiencies normally expected in the art.

Embodiments of the invention may have applications for a wide range of III-V semiconductor materials. For example, the methods and structures of the embodiments of the invention can be applied to Group III nitrides, Group III arsenides, Group III phosphides and Group III antimonides, in a binary, ternary form. quaternary and quinary. Particular applications relate to the growth of group III nitride semiconductors containing indium, such as gallium indium nitride (InGaN). Therefore, for the sake of brevity and convenience only, not limitation, the following description and figures reflect common characteristics of group III nitrides, and may focus particularly on InGaN. Experimentation in group III nitride material systems shows that InGaN layers, which are heteroepitaxially grown to a thickness greater than a critical thickness, can undergo stress relaxation to mitigate a constraint in the resulting crystal lattice. a lack of network correspondence. At the beginning of stress relaxation in the InGaN layers, a larger amount of indium may be incorporated, which may result in a non-uniform concentration profile of indium in the thickness of the InGaN layers. For example, an InGaN layer may comprise a larger percentage of indium near a growing surface of the layer. Such a non-uniform indium composition in the InGaN layer may be undesirable for at least some applications. An experiment also shows that the relaxation of the stresses of the InGaN layer can also result in a roughening of the growth surface of the InGaN layer. This roughening of the surface can hinder the production of semiconductor devices by using the InGaN layer. In addition, an experiment has shown that the stress relief of the InGaN layer can result in an increase of a defect density in the crystalline material. These defects may include, for example, dislocations and regions of nonhomogeneous composition (i.e., separate phase regions). As a non-limiting example, in the case of InGaN (Group III nitride material), InGaN layers may be heteroepitaxially deposited on an underlying substrate, which may have a crystal lattice which does not match that of the InGaN layer above. For example, InGaN layers may be deposited on a semiconductor substrate comprising gallium nitride (GaN). The GaN may have a lattice parameter in the relaxed (i.e., substantially stress-free) plane of about 3.189Å, and the InGaN layers may have a lattice parameter in the relaxed, dependent plane of the corresponding indium percentage content of about 3.21 A (for 7% indium, i.e., InO, O7GaO, 93N), about 3.24 Å (for 15 % indium, i.e., InO, 15GaO, 85N), and about 3.26 A (for 25% indium, i.e., InO, 25Ga 0.75N) . Fig. 1 is a schematic cross sectional diagram of a semiconductor structure 100 with a layer of semiconductor material 130 and a III-V-indium semiconductor layer 140 formed thereon and illustrating dislocations (132). and 142) and V-shaped depressions 150 formed therein. The semiconductor structure 100 may be manufactured or otherwise provided to include a substrate 110. The substrate 110 may comprise a semiconductor material that may be used as a seed layer for use in forming a several additional layers of semiconductor material thereon as part of the fabrication of the semiconductor material layer 130 and the III-V-indium semiconductor layer 140, as described in more detail below . The layer of semiconductor material 130 may be attached to and supported by the substrate 110. In some embodiments, however, the layer of semiconductor material 130 may comprise a self-supporting solid layer of semiconductor material that is not disposed on or supported by a substrate or any other material. In some embodiments, the layer of semiconductor material 130 may comprise an epitaxial layer of semiconductor material. By way of example and not limitation, the layer of semiconductor material 130 may comprise an epitaxial layer of III-V semiconductor material. As a non-limiting example, the semiconductor layer 130 may be an epitaxial layer of GaN. The substrate 110 may be a material such as, for example, an aluminum oxide (Al 2 O 3) (for example, a sapphire), a zinc oxide (ZnO), a silicon (Si) or a silicon carbide (SiC) , a gallium arsenide (GaAs), a lithium gallate (LiGaO 2), a lithium aluminate (LiAlO 2), an aluminum oxide yttrium (Y3A15012), or a magnesium oxide (MgO). Optionally, one or more intermediate layers of material (not shown), such as another layer of semiconductor material or one or more layers of dielectric material, may be disposed between the layer of semiconductor material 130 and the substrate These intermediate layers of material may be used, for example, as a seed layer to form the layer of semiconductor material 130 thereon, or as a tie layer for bonding the semi-conductive layer of material. conductor 130 to the substrate 110, as could be done when it is difficult or impossible to form the layer of semiconductor material 130 directly on the substrate 110. In addition, the connection of the layer of semiconductor material 130 to the substrate 110 may be desired if the semiconductor material 130 comprises polar crystalline orientations. In these embodiments, the bonding process can be used to change the polarity of the polar semiconductor material. The figures in this document are not drawn to scale, and in reality the III-V semiconductor layer 130 may be relatively thin compared to the substrate 110.

Dislocations (132B and 132D) can be formed during the formation of the III-V 130 semiconductor layer. As shown in FIG. 1, these dislocations can be through-going dislocations while the layer is formed with increasing thickness. In other words, once a dislocation occurs, it may tend to propagate as the layer is formed and thus appear on a final surface of the III-V semiconductor layer 130 at the end of its formation.

Any of various methods known in the art can be used to reduce the density of dislocations in the III-V 130 semiconductor layer. These methods include, for example, lateral epitaxial overgrowth (ELO), a pendulum epitaxy, in-situ masking techniques, etc. The layer of semiconductor material 130 may be deposited, for example, using a process such as a metallo-organic chemical vapor deposition (MOCVD), a molecular beam epitaxy (MBE), or a vapor phase epitaxy. hydride (HVPE).

FIG. 1 also illustrates an additional III-V semiconductor material 140 on the III-V semiconductor layer 130. As a non-limiting example, the additional III-V semiconductor material 140 may comprise a layer of InGaN 140 or indium in combination with another type of III-V semiconductor material such as gallium phosphide (GaP) and gallium arsenide (GaAs). An indium semiconductor layer in combination with a III-V semiconductor material may be referred to herein as a III-VIndium semiconductor material or a III-V-Indium 140 semiconductor layer. InGaN alloys develop without network mapping on GaN models (for example, GaN 130 on sapphire 110). The more indium in the InGaN layer 140, the greater the lack of network matching between the InGaN 140 layer and the GaN model. Generally, growth without network matching (i.e., a lack of correspondence between the InGaN 140 layer and the GaN model) is accompanied by a relaxation of the stresses when the constraint energy stored in the InGaN layer 140 is greater than the stress energy to nucleate the dislocations. This unmatched network growth occurs for a network arranged in cubic systems, but is more complex for materials with a hexagonal network structure such as GaN or InGaN or AlGaN.

In the hexagonal layers, there may not be an easy slip plane for dislocations and, therefore, a much greater stress energy can be stored in the InGaN layer 140 prior to nucleation of the dislocations. When relaxation is achieved, plastic relaxation occurs by modifying the growth surface. When the growth surface is (0001) hexagonal, depression defects 150 may appear. These trough defects appear as inverted pyramids with a vertex near a dislocation (often a through dislocation) of the GaN sub-surface and are often referred to as V 150 troughs. While the InGaN 140 layer is develops, the inverted pyramid also develops. With thick layers of InGaN, V 150 cavities can become very large. Generally, finer layers of InGaN 140 can be developed with little hollow in V 150 otherwise none. A thin layer may not reach a thickness (i.e., critical thickness) at which stress relaxation would occur because the stress energy in the InGaN layer 140 increases with the thickness of the layer. layer. However, for some applications, thick InGaN layers may be desirable. As a result, with conventional treatment, V-shaped depressions 150 are present in the thicker InGaN 140 layers and the V-shaped depressions 150 become deeper and wider as the InGaN 140 layer becomes thicker. In addition to the thinner InGaN layers, it may generally be possible to form a relatively V-trough-free InGaN layer if the indium concentration is kept at a relatively low level relative to the gallium concentration. However, many applications require thick InGaN layers, high indium concentrations in the InGaN layers, or a combination thereof, all of which can result in large, deep V-shaped depressions.

As mentioned, the V-shaped depressions often start from a dislocation, such as through dislocations designated 132B and 132D in the III-V 130 semiconductor layer and 142A and 142E in the III-V semiconductor layer. -indium 140. From these dislocations 132, V-shaped depressions (150A, 150B, 150D and 150E) can form and develop more widely as the III-V-indium semiconductor layer 140 develops. V-shaped depressions can also begin as original dislocation as shown by the V 150C trough. These deep V 150 voids may result in orifices after further processing for layer transfer, i.e., by smart-cut and bonding processes. V-shaped depressions 150 may also locally modify the depth of ion implantation and may result in division defects. In addition, further growth after layer transfer on InGaN hollow layers leads to very deep depressions that are detrimental to an LED device. For example, if a V-shaped depression 150 appears through the entire InGaN layer 140, it may short-circuit the LED portion of the LED device, rendering the device unable to perform its intended function. FIG. 2 is a simplified isometric diagram illustrating a non-limiting example of a V-shaped hollow 150 in a nonlimiting example of the III-V-In semiconductor layer 140. The hexagonal shape of the opening on a growth surface 148 is due to the growth of crystalline structure of InGaN. Further, the side walls 152 of the V-shaped recess lead from an apex 155 where the V-shaped recess 150 has begun to form due to crystalline structure growth so that the V-shaped recess 150 generally has a fixed proportion between a width 156 and a depth 154. Therefore, the depth 154 of the V-shaped recess 150 can be accurately estimated based on the width 156 of the V-shaped recess.

Embodiments of the present invention can reduce the number, size, or combination thereof of V shaped depressions 150 formed when a III-V-indium semiconductor layer 130 is formed on a semiconductor layer. III-V 130. This reduction of the V 150 recesses is also referred to herein as "reduced V-shaped hollow density" and "V-reduced hollow density". Thus, a decreased V-shaped void density may refer to a smaller number of V-shaped depressions in a given surface area, to smaller V-shaped depressions in a given surface area, or to a combination of a larger one. small number of V-shaped depressions and smaller V-shaped depressions in a given surface area. Although not bound to any particular theory for the formation of V-shaped depressions, Shiojiri (M. Shiojiri, CC Chuo, JT Hsu, JR Yang, H. Saijo, J. Appl Phys., 99, 073505 (2006) ) suggests that the growth rate is different in the planes {10-11} which are the lateral walls of V-shaped recesses 152 compared to the basal plane {0001} of the growth surface 148. Moreover, the planes {10-11 V-shaped sidewalls 152 may have a bonding coefficient for indium greater than that of the basal plane {0001} of the growth surface 148. Accordingly, the embodiments of the present invention can reduce the density. of V-shaped recesses by increasing a percentage of indium in the gas phase during the treatment, which can saturate the indium concentration in the basal plane {0001} of the growth surface 148 of the solid material formed while allowing concentration higher indium in the planes {10-11} of the side walls V-shaped hollow 152 to promote the growth of InGaN on the V-shaped sidewalls.

Fig. 3 is a simplified cross-sectional diagram of a semiconductor substrate 110 with a semiconductor material layer 130 and a III-V-indium semiconductor layer 140 formed thereon and illustrating a decreased density of V-shaped recesses formed therein according to one or more embodiments of the invention. As in FIG. 1, the semiconductor structure 100 may be manufactured or otherwise provided to include a substrate 110. The substrate 110, the semiconductor material layer 130, and the III-V-indium semiconductor layer 140 are similar. Figure 3 illustrates conventional V-shaped recesses 152A, 152B and 152C (i.e., V-shaped recesses that can be formed when conventional processing is used). Figure 3 also illustrates smaller V-shaped recesses (158A, 158B and 158C), which create a decreased V-shaped dimming density according to one or more embodiments of the invention. The decreased V-shaped recesses 158A and 158C illustrate that the V-shaped troughs from the through dislocations 132B and 132C, respectively, have grown at a slower rate (i.e., have not become so large) relative to V-shaped depressions 152A and 152C formed using conventional treatment. The decreased V-recess 158B illustrates a smaller V-shaped recess than the V-shaped recess 152B which can be formed directly from a dislocation using conventional treatment. Figure 4 is an indium solid phase concentration graph as a function of a gaseous indium phase concentration to illustrate an indium saturation regime in certain indium gas phase concentrations. Figure 4 can be developed from an experiment in a process chamber with a relatively constant temperature, a relatively constant pressure, a relatively constant total gas flow and a relatively constant rotational speed for the semiconductor wafer. With a specific gallium flow rate, an indium flow can be modified to change a percentage of indium in the gas phase, as shown by the x-axis. The percentage of indium in the solid phase that develops in the InGaN layer is illustrated on the y-axis as a function of the percentage of indium in the gas phase. In some embodiments, an indium precursor for the formation of the InGaN layer may comprise, for example, trimethylindium (TMI), triethylindium (TEI), or a combination thereof.

In some embodiments, a gallium precursor for formation of the InGaN layer may include, for example, triethylgallium (TEG) or other suitable material. In some embodiments, a nitrogen precursor for formation of the InGaN layer may include, for example, ammonia (NH3) or other suitable material. Thus, for one embodiment:% indium in the gas phase = 100 (TMI flow / (TMI flow + TEG flow)) (1) Initially, while the percentage of indium in the gas phase increases the percentage of indium in the solid phase increases proportionally, as shown by segment 410A. However, an inflection point 410B is reached, at which a further increase in the percentage of indium in the gas phase does not lead to an increase in the percentage of indium in the solid phase, as shown by the 410C segment. This indium concentration range in the gas phase in which there is not a proportional increase in indium concentration in the solid phase is referred to herein as the indium saturation regime. FIG. 5 is a solid phase concentration graph of indium as a function of the indium partial pressure, showing the saturation regime of FIG. 4 and the super-saturation regimes according to one or more embodiments of the invention. As those skilled in the art will recognize, the gas flow rate in a treatment chamber is related to the partial pressure due to each of the different gases in the treatment chamber. Therefore, it is possible to also represent the concentration of indium in the gas phase by:% indium in the gas phase = 100 (PTMI / (PTMI + PTEG)) (2) In other words, it is possible to determine easily a relation between an indium partial pressure (PTMI) and a global group III partial pressure (PTMI + PTEG), which is a combination of the indium partial pressure and a gallium partial pressure. For the sake of clarity, most of the description given in this paper relates to partial pressures; however, those skilled in the art will understand that the descriptions are equally applicable to associated flows. Of course, there may be other inert gases (eg, nitrogen) and other reagents, such as, for example, dopants in the reaction chamber.

As non-limiting examples, an N-type dopant. k may include silicon-containing vapor such as, for example, silane (SiH4) and a P-type dopant may comprise magnesium-containing vapor such as, for example, bis (cyclopentadienyl) magnesium (Cp2Mg). In FIG. 5, the y-axis illustrates a percentage of indium in the solid phase (also referred to herein as indium concentration in the solid phase) as a function of the x-axis illustrating a partial pressure of indium (also called here concentration of indium in the gas phase). Segments 510A and 510C illustrate the proportional increase (510A) of the indium concentration in the solid phase relative to the concentration of indium in the gas phase, followed by the saturation regime in which the indium concentration remains relatively high. constant (510B) with increasing indium concentration in the gas phase.

Line 520 illustrates a super-saturation indium regime in which a higher concentration of indium in the solid phase can be obtained relative to the saturation regime. Thus, as used herein, the term "super-saturation regime of indium" refers to a condition in a process chamber configured to develop a higher concentration of Indium in the semiconductor phase layer. solid formed relative to that which would be formed in the solid phase semiconductor layer using the saturation regime discussed above. As a non-limiting example, a saturation regime can be defined by a chamber pressure, a growth surface temperature, a precursor partial pressure of element III, a precursor partial pressure of element V and a partial pressure. indium precursor data. A higher concentration or partial pressure of the indium precursor than that of the saturation regime can develop a super-saturation regime which forms a higher concentration of indium in the semiconductor layer formed. As another nonlimiting example, in a saturation regime defined by a given growth surface temperature, a given chamber pressure, a given semiconductor wafer rotation speed and a given partial pressure combination of a precursor indium, group III precursor and Group V element precursor, a reduction in the growth surface temperature can create a super-saturation regime producing a solid phase growth condition which develops a higher percentage of indium in the semiconductor layer formed than that which would be obtained for the saturation regime. Similarly, an increase in chamber pressure, or a change in the rotational speed of the semiconductor wafer, while maintaining the temperature at the saturation regime temperature, may develop a super-saturation regime of indium. On line 520, the chamber parameters, such as, for example, chamber pressure and semiconductor wafer rotation, are kept relatively constant and reduced to develop the super-indium regime. The temperature can be as a growth chamber or surface temperature. As the temperature can be saturation temperature determined that non-limiting example, the chamber temperature for segments 510A and 510B is about 839 ° C and the chamber temperature for line 520 is about 811 ° C. In addition, the relative concentration between group III precursors (for example, an indium precursor combined with a gallium precursor) and a group III precursor is kept relatively constant at a ratio of V / III = 3560. In other words, in one embodiment, as the line 520 moves from left to right, the partial pressure for the TEG can remain relatively constant and, while the partial pressure for the TMI increases, the partial pressure for the ammonia increases proportionally to maintain the V / III ratio at around 3560.

The line 530, as a non-limiting example, can be developed with a chamber temperature of about 811 ° C. and a group V partial pressure (for example, a partial pressure of ammonia) maintained substantially constant with respect to the group III partial pressure and the varying indium partial pressure. In other words, in one embodiment, as line 530 moves from left to right, the partial pressure for TEG and ammonia can remain relatively constant while the partial pressure for TMI increases. In more detail, and with reference to FIGS. 3 and 5, the flow of indium precursor to the InGaN layer 140 can affect the incoming flux of indium species available for interaction on the growth surface 148 and the V-shaped sidewalls 152. Indium can be very volatile. At a surface, the TMI will break and release the metal (for example, indium) that can be incorporated into the solid layer or dissipate as vapor. With a higher temperature, the probability will be greater that the metal will dissipate rather than incorporate. Accordingly, there is a trade-off between indium incorporation in the InGaN layer 140 and desorption (also referred to as desorption flow) of indium from the InGaN layer 140. By lowering the temperature, or by increasing the pressure, the incorporation may be favored to increase the solid phase concentration of indium in the InGaN layer 140. In addition, although a saturation regime can be attained for the growth surface 148, the V-shaped sidewalls 152, with a different growth facet, may be more favorable at higher growth rates than the growth surface 148, which may result in decreased V-shaped void density. FIGS. 6A to 6C are graphs illustrating an indium solid phase concentration, a V-shaped cavity density and a V-shaped cavity width, respectively, all with respect to an indium partial pressure according to one or more modes of production. As can be seen with the line 610 in FIG. 6A, as the concentration of indium in the gas phase increases, the indium concentration in the solid phase also increases to an indium concentration of about 94. %. At this point, increases in gas phase concentration lead to lower solid phase concentrations. As can be seen with the line 620 in Figure 6B, as the concentration of indium in the gas phase increases, the V-shaped void density also increases to an indium concentration of about 94%. At this point, increases in gas phase concentration lead to lower solid phase concentrations. However, as illustrated by the line 630 in Figure 6C, as the concentration of indium in the gas phase increases, the width of the V-shaped depressions decreases. The dots in Fig. 6C illustrate an average V-shaped trough width, while the upper bars 632 and lower bars 634 illustrate the three-sigma distribution points for a V-shaped trough width. As a result, while the partial pressure indium increases, a decreased V-shaped void density can be observed by a smaller number of V-shaped depressions per given area, smaller V-shaped recesses, or a combination of V-shaped recesses per area The hollow width is a preferred way of measuring V-shaped troughs by atomic force microscopy (AFM) since the AFM tip may not be sharp enough to penetrate. to the total depth of the V-shaped trough to measure the depth correctly. From crystallographic considerations (for example, the angle between the planes (10-11) and (0001)), a trough depth can be calculated from the trough width (JE Northrup, LT Romano, J. Neugebauer , Appl., Lett., 74 (6), 2319 (1999) It should also be noted that with very thin InGaN layers, V-shaped depressions may exist but are not detectable because their widths may As stated previously, many applications require thick InGaN layers, high indium concentrations in the InGaN layers, or a combination thereof, all of which can resulting in large deep V-shaped depressions Certain embodiments of the present invention can generate decreased V-valley densities for solid-phase indium concentrations of about 6% to 9%. of achievement, densities V-shaped dimples can be obtained for relatively thick InGaN layers of about 150 nanometers and possibly up to about 200 nanometers.

Claims (18)

REVENDICATIONS1. A method of forming a semiconductor structure, comprising: forming a III-V semiconductor layer on a substrate; forming a III-V-indium semiconductor layer with a decreased V-shaped trough density on a growth surface of the III-V semiconductor layer and with an indium solid phase concentration above a trough of indium saturation by combining at least one indium precursor, a Group III element precursor different from the indium precursor and a Group V element precursor in a processing chamber configured with a superconducting regime. indium saturation which has a chamber temperature lower than a chamber temperature corresponding to the indium saturation regime. The method of claim 1, further comprising forming the III-V-indium semiconductor layer with a thickness greater than a critical thickness. The method of claim 1, wherein forming the III-V-indium semiconductor layer with the decreased V-shaped void density further comprises decreasing an indium desorption flux from the recess sidewalls. in V with respect to an indium desorption flux from the growth surface of the III-V-indium semiconductor layer. 4. The process according to claim 1, wherein the formation of the III-V-indium semiconductor layer with the decreased V-shaped void density further comprises increasing indium incorporation into the V-shaped sidewalls by relative to indium incorporation into the growth surface of the III-V-indium semiconductor layer. The method of claim 4, wherein increasing the indium incorporation in the V-shaped sidewalls comprises at least one of the decrease of the chamber temperature, the increase of the pressure. of chamber and the increase of indium partial pressure. The method of claim 1, wherein forming the III-V-indium semiconductor layer with the decreased V-shaped void density further comprises increasing an indium partial pressure in the process chamber with respect to an overall group III partial pressure. The method of claim 1, wherein forming the III-V-indium semiconductor layer comprises forming a layer of indium gallium nitride (InGaN). The method of claim 1, further comprising selecting the group V element precursor to include ammonia. 30 The method of claim 1, further comprising selecting the indium precursor to include trimethylindium. The method of claim 1, further comprising selecting the group III element precursor to include triethylgallium. The method of claim 1, wherein forming the III-V-indium semiconductor layer further comprises increasing the indium partial pressure in the process chamber relative to an overall group III partial pressure. A semiconductor structure, comprising: a substrate; a III-V semiconductor layer formed on the substrate; an InGaN layer with a decreased V-shaped void density and an indium solid phase concentration higher than an indium solid phase concentration of an indium saturation regime, wherein the InGaN layer is formed in a super-saturation indium regime with a chamber temperature lower than that for the indium saturation regime. The semiconductor structure of claim 12, wherein the InGaN layer with the decreased V-shaped void density further comprises a layer formed by decreasing an indium desorption flux from the V-shaped sidewalls. relative to an indium desorption flux from a growth surface of the InGaN layer. The semiconductor structure according to claim 12, wherein the InGaN layer with the decreased V-shaped void density further comprises a layer formed by increasing indium incorporation into the V-shaped sidewalls with respect to a incorporation of indium into a growth surface of the InGaN layer. The semiconductor structure of claim 12, wherein the InGaN layer with the decreased V-shaped void density further comprises a layer formed by increasing an indium partial pressure in a process chamber relative to a pressure. partial group III overall. The semiconductor structure of claim 12, wherein the InGaN layer comprises an indium concentration of from about 6% to about 9%. The semiconductor structure of claim 12, wherein the InGaN layer has a total thickness of at least about 150 nm. The semiconductor structure of claim 12, wherein the InGaN layer further has a thickness greater than a critical thickness.