FR2970611B1 - Étage de sortie forme dans et sur un substrat de type soi - Google Patents
Étage de sortie forme dans et sur un substrat de type soiInfo
- Publication number
- FR2970611B1 FR2970611B1 FR1150313A FR1150313A FR2970611B1 FR 2970611 B1 FR2970611 B1 FR 2970611B1 FR 1150313 A FR1150313 A FR 1150313A FR 1150313 A FR1150313 A FR 1150313A FR 2970611 B1 FR2970611 B1 FR 2970611B1
- Authority
- FR
- France
- Prior art keywords
- transistor
- soi
- conducting state
- output stage
- type substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/217—Class D power amplifiers; Switching amplifiers
- H03F3/2171—Class D power amplifiers; Switching amplifiers with field-effect devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01707—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits
- H03K19/01721—Modifications for accelerating switching in field-effect transistor circuits in asynchronous circuits by means of a pull-up or down element
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/387—A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/041—Modifications for accelerating switching without feedback from the output circuit to the control circuit
- H03K17/0412—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit
- H03K17/04123—Modifications for accelerating switching without feedback from the output circuit to the control circuit by measures taken in the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/30—Modifications for providing a predetermined threshold before switching
- H03K17/302—Modifications for providing a predetermined threshold before switching in field-effect transistor switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K2217/00—Indexing scheme related to electronic switching or gating, i.e. not by contact-making or -breaking covered by H03K17/00
- H03K2217/0018—Special modifications or use of the back gate voltage of a FET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Amplifiers (AREA)
- Logic Circuits (AREA)
Abstract
L'invention concerne un procédé de commande d'un étage d'amplification de sortie comprenant des premier (5) et second (7) transistors MOS de puissance complémentaires de type SOI, en série entre des premier (VDD ) et second (GND ) rails d'alimentation, ce procédé comprenant les étapes suivantes : relier le corps (B ) du premier transistor (5) au premier rail (VDD ) lorsque le premier transistor est maintenu dans un état non-passant ; relier le corps (B ) du second transistor (7) au second rail (GND ) lorsque le second transistor est maintenu dans un état non-passant ; et relier le corps (B , B ) de chacun des transistors (5, 7) au noeud (OUT) commun auxdits transistors, pendant les périodes de commutation de ce transistor d'un état non-passant vers un état passant.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1150313A FR2970611B1 (fr) | 2011-01-14 | 2011-01-14 | Étage de sortie forme dans et sur un substrat de type soi |
US13/333,862 US8629721B2 (en) | 2011-01-14 | 2011-12-21 | Output stage formed inside and on top of an SOI-type substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1150313A FR2970611B1 (fr) | 2011-01-14 | 2011-01-14 | Étage de sortie forme dans et sur un substrat de type soi |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2970611A1 FR2970611A1 (fr) | 2012-07-20 |
FR2970611B1 true FR2970611B1 (fr) | 2013-08-30 |
Family
ID=44000706
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR1150313A Expired - Fee Related FR2970611B1 (fr) | 2011-01-14 | 2011-01-14 | Étage de sortie forme dans et sur un substrat de type soi |
Country Status (2)
Country | Link |
---|---|
US (1) | US8629721B2 (fr) |
FR (1) | FR2970611B1 (fr) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8803551B2 (en) * | 2012-07-30 | 2014-08-12 | Infineon Technologies Austria Ag | Low supply voltage logic circuit |
FR3009149A1 (fr) | 2013-07-24 | 2015-01-30 | St Microelectronics Sa | Element a retard variable |
DE102015205714A1 (de) * | 2015-03-30 | 2016-10-06 | Siemens Aktiengesellschaft | Sendeverstärker zum Verstärken eines Signals in einem drahtlosen Übertragungssystem |
EP3343763B1 (fr) | 2016-12-29 | 2019-11-06 | GN Hearing A/S | Circuit d'attaque de sortie comprenant des commutateurs mos avec sollicitation de l'électrode de grille arriere réglable |
US11616506B2 (en) | 2018-09-26 | 2023-03-28 | Nxp Usa, Inc. | High speed buffer circuit |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH057149A (ja) * | 1991-06-27 | 1993-01-14 | Fujitsu Ltd | 出力回路 |
JPH0786917A (ja) * | 1993-09-14 | 1995-03-31 | Sanyo Electric Co Ltd | インバータ回路 |
US5644266A (en) * | 1995-11-13 | 1997-07-01 | Chen; Ming-Jer | Dynamic threshold voltage scheme for low voltage CMOS inverter |
JP4439031B2 (ja) * | 1999-04-15 | 2010-03-24 | 株式会社ルネサステクノロジ | 半導体装置 |
-
2011
- 2011-01-14 FR FR1150313A patent/FR2970611B1/fr not_active Expired - Fee Related
- 2011-12-21 US US13/333,862 patent/US8629721B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2970611A1 (fr) | 2012-07-20 |
US8629721B2 (en) | 2014-01-14 |
US20120182070A1 (en) | 2012-07-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20150930 |