FR2965397A1 - Method for manufacturing semi-conductor structure during manufacturing of e.g. semiconductor devices, involves replacing sacrificial material by conductor material, and forming portion of via across wafer in contact with another portion - Google Patents

Abstract

The method involves providing sacrificial material (102) inside a via indentation (112) parallely extending across a semi-conductor structure (120). A portion of a via is formed across a wafer in the structure and aligned across the wafer with the via indentation. The material inside the via indentation is replaced by a conductor material, and another portion of the via is formed across the wafer in electric contact with the former portion of the via across the wafer. An independent claim is also included for a semiconducting structure, comprising a sacrificial material.

Description

DESCRIPTION METHODS OF FORMING INTERCONNECTION HOLES THROUGH THE WAFER IN SEMICONDUCTOR STRUCTURES USING SACRIFICIAL MATERIAL, AND SEMICONDUCTOR STRUCTURES FORMED BY SUCH METHODS

TECHNICAL FIELD OF THE INVENTION The present invention relates generally to methods of forming semiconductor structures comprising vias through the wafer, and to semiconductor structures formed by such methods.

BACKGROUND OF THE INVENTION Semiconductor structures include, and are formed during the fabrication of, devices that utilize semiconductor materials (in other words, semiconductor devices) such as, for example, electronic signal processing devices, memory devices, photoelectric devices (eg, light-emitting diodes (LEDs), laser diodes, solar cells, etc.), micro- and nanoelectromechanical devices, etc. . In such semiconductor structures, it is often necessary or desirable to electrically and / or structurally couple a semiconductor structure to another device or structure (eg, another semiconductor structure). Such methods in which semiconductor structures are coupled to another device or structure are often referred to as "three-dimensional (3D) integration processes". 3D integration of two or more semiconductor structures may have a number of advantages in microelectronic applications. For example, 3D integration of microelectronic components can lead to improved electrical performance and decreased power consumption while reducing the surface area of the device footprint. See, for example, P. Garrou et al., "The Handbook of 3D Integration" Wiley-VCH (2008). The 3D integration of semi-conductive structures can be done by attaching a semiconductor wafer to another or more semiconductor wafer (in other words "wafer on wafer" (D2D)), the fixation of a semiconductor wafer on one or more semiconductor wafers (so-called "wafer-on-wafer" assembly (D2W)) as well as by attaching a semiconductor wafer to another or more semiconductor wafer (mounting in other words "wafer on wafer" (W2W)), or by a combination of these modes of attachment. Often, individual wafers or slices can be relatively thin and difficult to handle with equipment intended for processing wafers or wafers. This is the reason why wafers or so-called carrier wafers may be attached to current wafers or wafers which include the active and passive components of operational semiconductor devices. In general, wafers or carrier wafers do not include any of the active or passive components of a semiconductor device to be formed. In the present document, such platelets or carrier slices are referred to as "carrier substrates". Carrier substrates increase the overall thickness of wafers or wafers and facilitate the handling of wafers or wafers by processing equipment used to treat active and / or passive components in wafers or wafers attached thereto. which comprise the active and passive components of a semiconductor device to be manufactured thereon. It is common to use what is referred to herein as "through-wafers" or "TWIs" to establish electrical connections between active components in a semiconductor structure and conduction characteristics of another device or structure to which the semiconductor structure is attached. Holes through the wafer are conductive vias that extend through at least a portion of a semiconductor structure.

BRIEF SUMMARY OF THE INVENTION In some embodiments, the present invention relates to methods of manufacturing a semiconductor structure. A sacrificial material may be provided within at least one via hole recess extending partially through a semiconductor structure.

A first portion of at least one vias through the wafer may be formed in the semiconductor structure. The first portion of the at least one vias through the wafer may be aligned with the at least one vias recess. The sacrificial material within the at least one vias recess may be replaced by a conductive material to form a second portion of the at least one vias through the wafer that is in electrical contact with the first portion. at least one vias through the wafer. The present invention also includes additional embodiments of methods for manufacturing semiconductor structures. According to such methods, a sacrificial material is provided within at least one via hole recess extending in a surface of a semiconductor structure. A layer of semiconductor material may be provided over the surface of the semiconductor structure, and at least one device structure may be fabricated by means of the layer of semiconductor material. A first portion of at least one vias through the wafer is formed which extends through the layer of semiconductor material. The semiconductor structure may be thinned from a side thereof opposite the layer of semiconductor material. The sacrificial material may be removed from within the at least one via hole in the semiconductor structure and the first portion of the at least one via hole may be exposed through the wafer at the same time. inside the recess hole; a conductive material may be provided within the vias recess to form a second portion of the at least one vias through the wafer. In still other embodiments, the present invention relates to semiconductor structures formed by methods described herein. For example, in some embodiments, a semiconductor structure comprises a sacrificial material within at least one via hole recess extending partially through a semiconductor structure from a surface of the structure. semiconductor material disposed above the surface of the semiconductor structure, and at least one device structure comprising at least a portion of the semiconductor material which is disposed above the surface of the semiconductor material; semiconductor structure. A first portion of at least one vias through the wafer extends through the semiconductor material disposed above the surface of the semiconductor structure, and the first portion of the at least one interconnection across the wafer is aligned with the at least one via hole recess. In further embodiments, the present invention relates to semiconductor structures comprising an active surface, a back surface, at least one transistor disposed within the semiconductor structure between the active surface and the back surface. and at least one vias through the wafer extending at least partially through the semiconductor structure from at least one of the active surface and the back surface. The at least one through hole in the wafer comprises a first portion, a second portion, and an identifiable boundary between a microstructure of the first portion and a microstructure of the second portion.

BRIEF DESCRIPTION OF THE DIFFERENT VIEWS OF THE DRAWINGS Although the description ends with claims which detail in detail and which distinctly claim what are considered embodiments of the invention, the advantages of embodiments of The invention can be more readily understood from reading the description of certain exemplary embodiments of the invention when read in conjunction with the accompanying drawings, in which: FIG. 1 is a cross-sectional side view simplified part of a semiconductor structure; Fig. 2 is a simplified cross-sectional side view of a portion of another semiconductor structure that can be formed by providing vias recesses partially through the semiconductor structure of Fig. 1; Fig. 3 is a simplified cross-sectional side view of a portion of another semiconductor structure which may be formed by providing a dielectric material on or above the exposed surfaces of the semiconductor structure of the Figure 2 inside the vias recesses in it; Fig. 4 is a simplified cross-sectional side view of a portion of another semiconductor structure that can be formed by providing a material such as polysilicon for example inside the recesses of the recess. vias of interconnection of the semiconductor structure of Figure 3; Fig. 5 is a simplified cross-sectional side view of a portion of a bonded semiconductor structure that may be formed by bonding another semiconductor structure to the semiconductor structure of Fig. 4; Fig. 6 is a simplified cross-sectional side view of a portion of another semiconductor structure which may be formed by thinning the other semiconductor structure in the bonded semiconductor structure of Fig. 5; FIG. 7 is an enlarged view of a portion of another semiconductor structure that may be formed by fabricating transistors and shallow trench isolation structures in and / or on the bonded semiconductor structure of Figure 6; Fig. 8 is an enlarged view of a portion of another semiconductor structure that can be formed by providing a layer of dielectric material over the semiconductor structure of Fig. 7, and providing portions of vias through the wafer through the semiconductor structure; Fig. 9 is an enlarged view of a portion of another semiconductor structure that may be formed by fabricating a layer or more comprising electroconductive structures above a surface of the semiconductor structure of Fig. 8; ; Fig. 10 is an enlarged view of a portion of another semiconductor structure that can be formed by bonding the semiconductor structure of Fig. 9 to a carrier substrate; Fig. 11 is an enlarged view of a portion of another semiconductor structure which may be formed by removing a polysilicon material from the inside of vias recesses of the semiconductor structure of Figs. 10; Fig. 12 is an enlarged view of a portion of another semiconductor structure that may be formed by providing a conductive material within the vias recesses of the semiconductor structure of Fig. 11. to form additional portions of vias through the wafer therein; Fig. 13 is an enlarged view of a portion of another semiconductor structure which may be formed by removing the carrier substrate from the semiconductor structure of Fig. 12 and providing conductive bumps above exposed ends of the vias through the slice in them; Figures 14 to 16 illustrate additional methods that may be used to process a semiconductor wafer similar to that shown in Figure 10 to a semiconductor structure similar to that shown in Figure 11; and Figs. 17 to 20 further illustrate other methods that can be used to process a semiconductor wafer similar to that shown in Fig. 10 to a semiconductor structure similar to that shown in Fig. 11.

DETAILED DESCRIPTION OF THE INVENTION The following description provides specific details, such as the types of materials employed and the processing conditions, for example, so as to provide a full description of embodiments of the present invention and their implementation. . However, it will be apparent to those skilled in the art that the embodiments of the invention may be implemented without using these specific details but by applying conventional manufacturing techniques. In addition, the description provided herein does not constitute a complete flow of operations involved in the realization of a device or a semiconductor system. Only the methods and structures necessary for understanding the embodiments of the present invention are described in detail here. The materials described herein may be formed (deposited or grown, for example) using any suitable technique such as, but not limited to, spin coating, apron coating, Bridgeman and Czochralski, Chemical Vapor Deposition ("CVD"), Plasma Assisted Chemical Vapor Deposition ("PECVD"), Atomic Layer Deposition ("ALD"), Plasma Assisted Atomic Layer Deposition ("PEALD") or Physical Vapor Deposition ("PVD"). Although the materials described and illustrated herein may be formed as layers, the materials are not limited to layers and may be formed in other three-dimensional configurations. k As used in this document, the terms "horizontal" and "vertical" define relative positions of elements or structures with respect to a principal plane or surface of a semiconductor structure ( wafer, wafer, substrate for example, etc.), regardless of the orientation of the semiconductor structure, and are orthogonal dimensions interpreted with respect to the orientation of the structure that is described. As used herein, the term "vertical" refers to and includes a dimension substantially perpendicular to the major surface of a semiconductor structure, and the term "horizontal" refers to a dimension substantially parallel to the main surface. of the semiconductor structure. As used herein, the term "semiconductor structure" refers to and includes any structure that is used in the formation of a semiconductor device. Semiconductor structures include, for example, wafers and wafers (for example, support substrates and device substrates), and composite assemblies or structures that include two or more wafers and / or wafers that are integrally integrated with each other. three-dimensional with each other. Semiconductor structures also include fully fabricated semiconductor devices as well as intermediate structures that are formed during the fabrication of semiconductor devices. The semiconductor structures may include conductive materials, semiconductor materials and / or non-conductive materials. As used herein, the term "treated semiconductor structure" refers to and includes any semiconductor structure that comprises at least a partially formed or more than one device structure. Treated semiconductor structures are a subset of semiconductor structures, and all treated semiconductor structures are semiconductor structures. As used herein, the term "bonded semiconductor structure" refers to and includes any structure that includes two or more semiconductor structures that are attached to each other. Glued semiconductor structures are a subset of semiconductor structures, and all bonded semiconductor structures are semiconductor structures. In addition, glued semiconductor structures which comprise a treated semiconductor structure or more are also considered treated semiconductor structures. As used herein, the term "device structure" refers to and includes any portion of a treated semiconductor structure that is, comprises, or defines at least a portion of an active component. or passive of a semiconductor device to be formed on or in the semiconductor structure. For example, device structures comprise active and passive integrated circuit components such as, for example, transistors, transducers, capacitors, resistors, conductive lines, conductive vias and connection pads. conductive. As used herein, the term "through-wafer" or "TWI" means and includes any conductive vias extending through at least a portion of a first semiconductor structure which is used to provide a structural interconnection and / or electrical interconnection between the first semiconductor structure and a second semiconductor structure via an interface between the first semiconductor structure and the second semiconductor structure -conductrice. In the art, vias across the wafer are also referred to by other terms such as "through vias through silicon" or "via vias" (TSV) and vias through the wafer "or" TWV ". The TWIs generally extend through a semiconductor structure in a direction generally perpendicular to the generally planar major surfaces of the semiconductor structure (in other words, in a direction parallel to the "Z" axis). As used herein, the term " active surface ", when used in connection with a treated semiconductor structure, refers to and includes a principal exposed surface of the treated semiconductor structure which has or will be processed to form one or more device structures in and / or on the exposed main surface of the treated semiconductor structure. As used herein, the term "back surface", when used in connection with a treated semiconductor structure, means and includes a main exposed surface of the semiconductor structure being treated on a surface. opposite side of the semiconductor structure treated with respect to an active surface of the semiconductor structure. As used herein, the term " III-V semiconductor material " means and includes any material comprising primarily one or more elements belonging to Group IIIA of the Periodic Table of Elements (B). , Al, Ga, In and Ti), and one or more members belonging to group VA 10 of the periodic table of elements (N, P, As, Sb and Bi). As used herein, the term "coefficient of thermal expansion", when used in connection with a material or structure, refers to the average linear thermal expansion coefficient of the temperature material or structure. room. As will be discussed in more detail hereinafter, in certain embodiments, the present invention relates to methods of forming semiconductor structures that include a via hole across the wafer or more in them. . The vias through the wafer may comprise two or more portions that are formed during separate treatments. Fig. 1 is a simplified cross-sectional side view of a portion of a first semiconductor structure 100. The first semiconductor structure 100 may comprise a layer or substrate of material 102. For example, the material 102 may comprise a ceramic such as, for example, an oxide (silicon dioxide (SiO2) or aluminum oxide (Al2O3), for example) or a nitride (silicon nitride (Si3N4) or boron nitride (BN), eg.). In another example, the first semiconductor material 100 may comprise a semiconductor material such as, for example, silicon (Si), germanium (Ge), III-V semiconductor material, and the like. On the other hand, the material 102 may comprise a single crystal of semiconductor material or an epitaxial layer of semiconductor material. By way of nonlimiting example, the material 102 of the first semiconductor structure 100 may comprise a single crystal of bulk silicon material.

FIG. 2 illustrates another semiconductor structure 110 that can be formed by providing vias recesses 112 in the semiconductor structure 100 of FIG. 1. The vias 112 recesses can be used to form portions of vias through the wafer, as will be discussed in more detail in the following. As shown in Fig. 2, the vias recesses 112 may extend in and at least partially through the material 102 of the semiconductor structure 110 from a first major surface 104 thereof. In some embodiments, the vias 112 may include blind vias recesses that extend only partially through the material 102 of the semiconductor structure 110. The vias recesses 112 may have a generally cylindrical cross sectional shape or any other shape in cross section. The vias 112 may have an average cross-sectional dimension (eg, average diameter) of about one micrometer (1 μm) or less, or about ten micrometers (10 μm) or less, even fifty micrometers (50 pm) or less. On the other hand, vias recesses 112 may have an average aspect ratio (i.e., the ratio of the average height to the average dimension in cross section) in a range s'. ranging from about 0.5 to about 10.0. FIG. 3 illustrates another semiconductor structure 120 that can be formed by providing a dielectric material 122 at the surfaces of the material 102 within the vias of the vias 112. By way of example and not limitation the dielectric material 122 may comprise a ceramic such as, for example, an oxide (silicon dioxide (SiO2) or aluminum oxide (Al2O3), for example), a nitride (silicon nitride (Si3N4) or nitride). boron (BN), for example) or oxynitride (eg silicon oxynitride). The dielectric material 122 may be formed in situ on or in the exposed surfaces of the material 102 within the vias recesses 112. In additional embodiments, the dielectric material 122 may be deposited over the exposed surfaces of the material 102 within the vias recesses 112. By way of non-limiting special example, the material 102 may comprise a solid silicon material, the dielectric material 122 may comprise oxide of silicon, and the dielectric material 122 may be formed by oxidizing the exposed surfaces of the material 102 within the vias 112. In some embodiments, the dielectric material 122 may also be deposited above of the first major surface 104 of the semiconductor structure 110 (FIG. 2), as shown in FIG.

Referring to FIG. 4, the vias 112 (FIG. 3) can be filled with a sacrificial material 132. The sacrificial material 132 comprises a material which will eventually be removed and replaced with another material, such as will see in more detail in the following. The sacrificial material 132 may comprise, for example, a polycrystalline silicon material. In other words, the sacrificial material 132 may comprise a silicon having a microstructure which comprises a plurality of silicon grains stuck together randomly oriented within the microstructure. Such silicon material is commonly referred to as "polysilicon" material in the art. In further embodiments, the sacrificial material 132 may comprise any other material that can be selectively etched relative to the material 102 (and optional dielectric material 122) such as a ceramic, a semiconductor material (a polycrystalline SiGe material, eg), a polymer material, a metal, etc. In some embodiments, the sacrificial material 132 may comprise one or more additional dielectric material, such as an oxide, nitride, or oxynitride (eg silicon dioxide). The sacrificial material 132 may have a composition that is selected such that the atoms of the sacrificial material 132 do not diffuse in a significant amount in surrounding areas of a semiconductor structure during the processing of the semiconductor structure. temperatures greater than about 400 ° C at which the semiconductor structure may be subjected during the fabrication of transistors or other device structures, as will be discussed in more detail below, or which would not affect negatively the semiconductor structure if the atoms were to diffuse in a significant amount in the surrounding structure during such treatments at high temperatures. In some embodiments, the sacrificial material 132 may have a coefficient of thermal expansion corresponding to about forty percent (40%) of a thermal expansion coefficient exhibited by the material 102, corresponding to about twenty percent (20%). %) of a coefficient of thermal expansion exhibited by the material 102, or even corresponding to about five percent (5%) of a coefficient of thermal expansion exhibited by the material 102. In addition, in some embodiments the sacrificial material 132 may comprise a material having a coefficient of thermal expansion of about 5.0 x 10-6 ° C-1 or less, about 3.0 x 10-6 ° C-1 or less or even about 1.0 x 10-6 ° C-1 or less.

After supplying the sacrificial material 132 within the vias 112 (Figure 3), the surface 134 of the semiconductor structure 130 may be planarized to cause the exposed surfaces of the sacrificial material 132 to be exposed. at least substantially coplanar and coextensive with the exposed surface of the material 102 at the surface 134 of the semiconductor structure 130. In more detail, the sacrificial material 132 may be formed by marrying the top of the first major surface 104 ( and optional dielectric material 122), for example, using CUD techniques. The sacrificial material 132 may be formed to a thickness such that the vias 112 are at least substantially completely filled with the sacrificial material 132. Any excess sacrificial material 132 (and optional dielectric material 122) can then be removed. for planarizing the surface 134 of the semiconductor structure 130. For example, the surface 134 of the semiconducting semiconductor 130 may be planarized using a chemical method (eg wet or dry chemical etching process). , a mechanical process (eg a grinding or honing process), or a chemical mechanical polishing (CMP) process. After supply of the sacrificial material 132 within the vias 112 recesses (FIG. 3), as seen in the foregoing, a thin layer of semiconductor material may be provided over the the surface 134 of the semiconductor structure 130. By way of nonlimiting example, a thin layer of semiconductor material may be provided above the surface 134 of the semiconductor structure 130, as will be seen from FIG. in greater detail in the following with reference to FIGS. 20 and 6. FIG. 5 illustrates a glued semiconductor structure which can be formed by gluing another semiconductor structure comprising a substrate 142 to the surface 134 of the semi structure. The substrate 142 may comprise a semiconductor material such as, for example, silicon (Si), germanium (Ge), a III-V semiconductor material, and the like. On the other hand, the substrate material 142 may comprise a monocrystal 30 of semiconductor material or an epitaxial layer of semiconductor material. By way of non-limiting example, the substrate material 142 may comprise a monocrystal of bulk silicon material. Substrate 142 may be adhered to surface 134 using a direct bonding method in which sacrificial 132 (and optional dielectric material 122) may then be removed to planarize surface 134 of semiconductor structure 130. For example, the surface 134 of the semiconductor structure 130 may be planarized using a chemical process (eg wet or dry chemical etching process), a mechanical process (eg a grinding or honing process) or by a chemical mechanical polishing process (CMP).

After supplying the sacrificial material 132 inside the vias 112 recesses (FIG. 3), as seen in the foregoing, a thin layer of semiconductor material may be provided over the surface 134 of the semiconductor structure 130. By way of nonlimiting example, a thin layer of semiconductor material may be provided above the surface 134 of the semiconductor structure 130, as will be seen more FIG. 5 illustrates a glued semiconductor structure that can be formed by gluing another semiconductor structure comprising a substrate 142 to the surface 134 of the semiconductor structure 130. FIG. 4. The substrate 142 may comprise a semiconductor material such as, for example, silicon (Si), germanium (Ge), a semiconductor material of III-V type, etc. On the other hand, the substrate material 142 may comprise a single crystal of semiconductor material or an epitaxial layer of semiconductor material. By way of nonlimiting example, the material of the substrate 142 may comprise a single crystal of bulk silicon material. Substrate 142 may be adhered to surface 134 using a direct bonding method in which (Figure 4) at a bonding interface therebetween. The bonding material 148 may have an average thickness of, for example, about 1000 angstroms.

In additional embodiments, the bonding surface of the substrate 142 may comprise a semiconductor material (eg, silicon), and the bonding surface of the semiconductor structure 130 may comprise at least substantially the same semi material. -conductor (silicon, for example). In such embodiments, a silicon silicon surface bonding method can be used to bond the bonding surface of the substrate 142 to a bonding surface of the semiconductor structure 130.

In some embodiments, direct bonding between the bonding surface of the substrate 142 and the bonding surface of the semiconductor structure 130 can be established by forming each of the bonding surface of the substrate 142 and the bonding surface of the substrate. the semiconductor structure 130 so as to have relatively smooth surfaces, and then abutting the bonding surfaces together and maintaining contact between the bonding surfaces during annealing treatment.

For example, each of the bonding surface of the substrate 142 and the bonding surface of the semiconductor structure 130 may be formed to have a root mean square surface roughness (RRms) of about two nanometers (2.0 nm) or less, of about one nanometer (1.0 nm) or less, or even about one quarter of a nanometer (0.25 nm) or less. In some embodiments, each of the bonding surface of the substrate 142 and the bonding surface of the semiconductor structure 130 may be formed to have a root mean square surface roughness (RRms) of about one-quarter to one nanometer (0.25 nm) and about two nanometers (2.0 nm), or even between about one-half nanometer (0.5 nm) and about one nanometer (1.0 nm).

The annealing treatment may include heating the substrate 142 and the semiconductor structure 130 in an oven at a temperature of from about one hundred degrees Celsius (100 ° C) to about four hundred degrees Celsius (400 ° C) for a period of time. from about two minutes (2 minutes) to about fifteen hours (15 hours). Each of the bonding surface of the substrate 142 and the bonding surface of the semiconductor structure 130 may be formed so as to be relatively smooth, as seen in the foregoing, using at least one of a mechanical polishing process and a chemical etching process. For example, a chemical mechanical polishing (CMP) process may be used to planarize and / or reduce the surface roughness of each of the bonding surface of the substrate 142 and the bonding surface of the semiconductor structure 130. A first portion 144 of the substrate 142 may be removed from the semiconductor structure 140 of Figure 5, leaving a second portion 146 of the remaining substrate 142 above the surface 134 and forming the bonded semiconductor structure 150 of Figure 6 In other words, the first portion 144 of the substrate 142 can be separated from the second. Part 146 of the substrate 142. The semiconductor structure 150 of Figure 6 comprises a thin layer of semiconductor material 152 over the surface 134. The thin layer of semiconductor material 152 is provided by the second portion 144 of the substrate 142 (Figure 5).

Referring again to Figure 5, by way of example and not limitation, the method known in the industry as SMART-CUT® process can be used to separate the first portion 144 of the substrate 142 from the second portion 146 of the substrate 142. Such methods are described in detail in, for example, US Patent No. RE 39,484 to Bruel (published February 6, 2007), U.S. Patent No. 6,303,468 to Aspar et al. October 2001), U.S. Patent No. 6,335,258 to Aspar et al. (published January 1, 2002), U.S. Patent No. 6,756,286 to Moriceau et al. (published June 29, 2004), U.S. Patent No. 6 809,044 to Aspar et al. (Published October 26, 2004), and US Patent No. 6,946,365 to Aspar et al. (Published September 20, 2005). A plurality of ions (hydrogen, helium, or inert gas ions, for example) may be implanted into the substrate 142. The ions may be implanted into the substrate 142 before or after the substrate is attached. to semiconductor 130 of FIG. 4, as seen in the foregoing. For example, ions may be implanted into the substrate 142 from an ion source (not shown) placed on one side of the substrate 142. Ions may be implanted into the substrate 142 along a substantially perpendicular direction to the main surfaces of the substrate 142. As is known in the art, the depth at which the ions are implanted in the substrate is at least partially a function of the energy with which the ions are implanted in the substrate. In general, implanted ions with less energy will be implanted at a relatively shallow depth while ions implanted with more energy will be implanted at a relatively deeper depth. Ions can be implanted into the substrate 142 with a predetermined energy selected to implant the ions at a desirable depth within the substrate 142. As a non-limiting special example, the ions can be implanted inside. substrate 142 at a selected depth such that the average thickness T of the second portion 146 of the substrate 142 is about three hundred nanometers (300 nm) or less, or even about one hundred nanometers (100 nm) or less. As is known in the art, inevitably, at least some of the ions may be implanted at depths other than the desired implantation depth, and a graph of the concentration of ions as a function of the depth in the substrate 142 since a substrate surface 142 may exhibit a generally bell-shaped (symmetrical or asymmetric) curve having a maximum at a desirable implantation depth.

When implanted into the substrate 142, the ions may define a fracture plane 143 (shown in dashed lines in FIG. 5) within the substrate 142. The fracture plane 143 may comprise a layer or a region having the interior of the substrate 142 which is aligned with (centered around, for example) the plane of maximum concentration of ions with the substrate 142. The fracture plane 143 may define a zone of weakness within the substrate 142 along of which the substrate 142 may be cleaved or fractured during further processing. Substrate 142 may be cleaved or fractured along fracture plane 143 by heating substrate 142, applying mechanical force to substrate 142, or otherwise applying energy to substrate 142. 3M In further embodiments, the second portion 146 of the substrate 142 may be provided above the surface 134 of the semiconductor structure 130 of Figure 4 by gluing a layer of relatively thick material (a layer having an average thickness of more than about 300 microns, e.g., such as substrate 142, and then thinning the relatively thick substrate 142 from the side 149 thereof opposite the surface 134.

For example, the substrate 142 may be thinned using a chemical process (eg wet or dry chemical etching process), a mechanical process (eg a grinding or honing process), or a chemical mechanical polishing process (CMP). In still other embodiments, a relatively thin semiconductor material layer (which may be at least substantially similar in composition and configuration to the second portion 146 of the substrate 142) may be formed in situ above ( For example, a layer of relatively thin silicon material may be formed by depositing a material, such as silicon, over the surface. 134 of the semiconductor structure 130 of Figure 4 to a desirable thickness. After providing a thin layer of semiconductor material 152 over the surface 134 of the semiconductor structure 130 of Figure 3, one or more device structures may be formed on and / or in the thin layer of Semiconductor material 152. In other words, one or more device structures may be formed by means of the thin layer of semiconductor material 152. By way of example and not limitation, a plurality of transistors may be manufactured using the thin layer of semiconductor material 152. FIG. 7 illustrates a portion of the glued semiconductor device 150 of FIG. 6 encircled by a dashed line 158, subsequent to the treatment of the semiconductor structure. 150 to form the treated and bonded semiconductor structure 160 of FIG. 7. The semiconductor structure 160 includes a transistor 162 or more. For the sake of clarity, a single transistor 162 is shown in Figure 7. As shown in Figure 7, each transistor 162 may include a source that includes a source region 163A and a source contact 163B, a drain that includes a drain region 164A and a drain contact 164B, and a gate structure 165. Each of the region source 163A and the drain region 164A may comprise regions of the thin layer of semiconductor material 152 which have been doped with one or more dopants to render these regions electroconductive. The source region 163A and the drain region 164A may be separated from each other by a channel region 166 which may comprise an undoped region of the thin layer of semiconductor material 152. The gate structure 165 may be disposed above the channel region 166 laterally between the source and the drain of the transistor 162. Each of the source contact 163B, the drain contact 164B and the gate structure 165 may comprise a conductive material such as a metal or more, or a doped polysilicon material. The conductive material of the gate structure 165 may be electrically isolated from the thin layer of semiconductor material 152 by a dielectric material or c. Further, such as an oxide, nitride, oxynitride, etc. As shown in FIG. 7, a shallow trench isolation structure 168 or more may be formed in and through the layer. The shallow trench isolation structures 168 may comprise a dielectric material and may be used to electrically isolate each transistor 162 from other transistors or other device structures. of the semiconductor structure 160. By way of example and not limitation, the shallow trench isolation structures 168 may comprise a dielectric material such as an oxide, a nitride, an oxynitride, and the like. The shallow trench isolation structures 168 may be vertically aligned (i.e., aligned in a direction perpendicular to the major surfaces of the semiconductor structure 160, such as the surface 134, for example) with the recesses of vias 112 and sacrificial material 132 contained therein. In other words, the vias 112 and the sacrificial material 132 may be arranged relative to each other so that a straight line can be drawn at least substantially perpendicular to the main surfaces of the structure. semiconductor 160, such as surface 134, for example, which passes through a shallow trench isolation structure 168 and a volume of sacrificial material 132 within one of the vias recesses. 112. Referring to Fig. 8, a bonded treated semi-conductive structure 170 may be formed by providing a layer of dielectric material 172 (an intermediate layer dielectric material, e.g.) over a surface of 169 of the semiconductor structure 160 of FIG. 7 in and / or on which the transistor (s) 162 and the shallow trench isolation structure (s) 168 have been formed ( e) s, and forming first portions 174 vias through the wafer in them.

The layer of dielectric material 172 may be formed on or deposited over surface 169, and may have a sufficiently large average thickness to cover the gate structure 165 of transistor 162, as shown in FIG. Dielectric material 172 may comprise a dielectric material such as an oxide, a nitride, an oxynitride, etc. Continuing to refer to FIG. 8, first portions 174 of vias through the wafer may be formed in the semiconductor structure 170. The first portions 174 of via vias through the wafer may include a conductive material such as a metal or more, doped polysilicon, etc. The first portions 174 of vias through the wafer may be formed by forming vias recesses 176 through the layer of dielectric material 172, through the shallow trench isolation structures 168, and through through any bonding material 148 to the sacrificial material 132 in the through-hole recesses 112 within the material 102. In some embodiments, the shallow trench isolation structures 168 may be unsuitable. extend completely through the thin layer of semiconductor material 152, and vias recesses 176 may also extend through at least a portion of the thin layer of semiconductor material 152. The hole recesses interconnection 176 may be formed, for example, by means of a masking and etching process. A mask layer may be provided over the exposed main surface 178 of the dielectric material layer 172. The mask layer may be shaped to form holes or apertures extending through the mask layer to locations where it is desired to form the vias recesses 176. The apertures in the mask layer may have a cross-sectional dimension and shape corresponding to a cross-sectional dimension and shape of the vias recesses 176 to be trained. The semiconductor structure 170 may then be exposed to one or more etching agents that will etch the various materials through which the vias recesses 176 must extend without etching the mask layer (in a significant proportion). . For example, a wet chemical etching method or a dry reactive ion etching method can be used to form vias recesses 176 through dielectric material layer 172, shallow trench isolation structures. 168, and any bonding material 148 to the sacrificial material 132. In some embodiments, the vias 66 may have a mean aspect ratio (i.e. the average height to the average dimension in cross section) in a range from about 0.5 to about 10.0. After formation of vias recesses 176, conductive material may be provided within vias recesses 176. For example, one or more metallic material may be deposited within hole recesses interconnection 176 by means of an electroless plating process and / or an electrolytic plating process. The first portions 174 of vias through the wafer, such as the shallow trench isolation structures 168 through which they extend, may be vertically aligned (i.e., aligned in one direction perpendicular to the major surfaces of the semiconductor structure 170, such as the surface 134, for example) with the vias 112 and the sacrificial material 132 contained therein. In other words, the first portions 174 of the vias recesses and the sacrificial material 132 may be arranged relative to each other so that a straight line can be drawn at least substantially perpendicular to the main surfaces of the semiconductor structure 170, such as the surface 134, for example, which passes through a first portion 174 of a through-hole through the wafer and a volume of sacrificial material 132 within one of the Recesses of vias 112. After the formation of the first portions 174 of vias through the wafer, another treatment may be performed to form additional device structures, such as conductive vias, e.g. lines, traces and connection pads above the exposed main surface 178 of the layer of dielectric material 172. Such treatments can understand those known in the art of Back End Of Line (BEOL) treatments. For example, Fig. 9 illustrates a treated and bonded semiconductor structure 180 that can be formed by fabricating a plurality of device structures 182 within a surrounding dielectric material 184 or more. The device structures 182 may include one or more conductive vias, lines, traces and bond pads comprising a conductive material such as one or more metal or doped polysilicon. The surrounding dielectric material (s) 184 may comprise an oxide, a nitride, an oxynitride, and the like. The various device structures 182 and the surrounding dielectric material 184 may be lithographically (i.e. layer-by-layer) formed above the main surface 178 of the dielectric material layer 172 by means of known treatments in art. After the formation of device structures 182 above the dielectric material layer 172, as seen in the foregoing with reference to FIG. 9, a portion of the material 102 may be removed from the semiconductor structure 180 so as to expose the sacrificial material 132 through the material 102 as shown in the treated and bonded semiconductor structure 190 of FIG. 10. The portion of the material 102 can be removed from the exposed main surface 103 (FIG. 9) of the material 102 on the side of the semiconductor structure 180 opposite the active surface 186. By way of example and not limitation, the part of the material 102 can be eliminated by means of, for example, one or more than one chemical etching process, a mechanical polishing process or a chemical mechanical polishing (CMP) process. If a dielectric material 122 is disposed between the sacrificial material 132 and the material 102, as shown in FIG. 9, a portion of the dielectric material 122 may also be removed so as to expose the sacrificial material 132 to the outside of the semiconductor structure 190, as shown in FIG. 10. Alternatively, the active surface 186 of the semiconductor structure 180 of FIG. 9 may be bonded to a carrier substrate 192, as shown in FIG. removing the material 102 so as to expose the sacrificial material 132 and thereby facilitate the manipulation of the semiconductor structure while removing the material 102. After exposing the sacrificial material 132 to the outside of the semiconductor structure as shown in FIG. 10, the sacrificial material 132 can be removed from the inside of the vias 112 to form the semiconductor structure. Processed and bonded 200 shown in Fig. 11. By way of example and not limitation, a wet chemical etching process may be used to remove sacrificial material 132 from within vias recesses 112. An agent engraving material which will etch (eg remove) the sacrificial material 132 from the semiconductor structure 200 at a faster rate than a rate at which the etching agent will remove the dielectric material 122 and any Bonding material 148 may be used to remove sacrificial material 132. In other words, an etching agent that is selective for sacrificial material 132 (and optionally with respect to optional dielectric material 122) and in relation to any which bonding material 148 may be used to remove the sacrificial material 132. In embodiments in which the sacrificial material comprises a polysilicon material The etching agent may comprise a mixture of nitric acid, hydrofluoric acid and water. In embodiments in which the sacrificial material 132 comprises another dielectric material such as, for example, silicon dioxide, the sacrificial material 132 may be selectively etched by means of an etching solution comprising hydrofluoric acid or a plasma etching method (using, for example, an SF6 sulfur hexafluoride etching chemical composition). As shown in Fig. 12, conductive material may be provided within vias recesses 112 (within the vacant space by removal of sacrificial material 132) to form seconds. 212 portions of vias through the wafer 214. The vias through the wafer 214 include the first portions 174 and the second portions 212. Direct electrical and physical contact can be established between the first portions 174 and the second portions 212 vias through the wafer 214. The conductive material of the second portions 212 of the vias through the wafer 214 may comprise a conductive material such as one or more metal, doped polysilicon, etc. In some embodiments, the conductive material of the second portions 212 of vias through the wafer 214 may be at least substantially identical to the conductive material of the first portions 174 of vias through wafer 214. The conductive material may be provided within vias recesses 112, 176. For example, one or more metallic material may be deposited within vias recesses 176 by an electroless plating process. and / or an electrolytic plating process.

The vias through the wafer 214 include the first portions 174 and the second portions 212 thereof. As a result of the formation of the first portions 174 and the second portions 212 during separate processes at different sequential periods during the fabrication of the semiconductor structure 210, there may be an identifiable discrete boundary 216 in the microstructure between the first portions 174 and the second portions 212 of the vias through the wafer 214 in some embodiments of the invention. The identifiable limit 216 may be placed near a major surface of the thin layer of semiconductor material 152. For example, the identifiable boundary 216 may be coplanar with the bonding material 148 disposed at a major surface of the thin layer of semiconductor material 152. On the other hand, the semiconductor structure 210 may be oriented parallel to the active surface 186, as shown in FIG.

In some embodiments, the vias through the wafer 214 may have an average aspect ratio (i.e., the ratio of the average height to the average cross-sectional dimension) in a range. ranging from about 0.5 to about 10.0.

After formation of vias through wafer 214 as seen in the foregoing, carrier substrate 192 can be removed from bonded and bonded semiconductor structure 210 of FIG. 12 to form the semi structure. Figure 13. As shown in Figure 13, conductive bumps 222 may be structurally and electrically coupled to the exposed ends of the second portions 212 of vias through wafer 214 at the the rear surface 224 of the semiconductor structure 220 opposite the active surface 186. The conductive bumps 222 may comprise a conductive material such as, for example, a conductive solder alloy. The semiconductor structure 220 shown in Figure 13 may further be optionally processed and packaged where required or desirable. The semiconductor structure 220 can then be structurally and electrically coupled to another structure, such as a printed circuit board, another semiconductor structure (another wafer or other wafer, for example), etc., by means of 222. In additional embodiments, the semiconductor structure 220 may be structurally and electrically coupled to another structure by means of other devices and other methods known in the art such as, for example, means of conducting wires, an anisotropically conductive thin layer, etc. Referring again to FIG. 10, in some embodiments of the invention, it may be relatively difficult to selectively etch the sacrificial material 132 within vias recesses 112 without etching another material of the invention. semiconductor structure 190. In such embodiments, it may be desirable to protect other materials of the semiconductor structure 190 prior to etching the sacrificial material 132 as seen in the foregoing. For example, Fig. 14 illustrates a semiconductor structure 230 that can be formed by depositing a mask layer 232 over the surfaces of the semiconductor structure 190 of Fig. 10 so as to cover at least substantially all the surfaces exposed to the semiconductor structure 230, with the possible exception of certain surfaces of the carrier substrate 192. The mask layer 232 may comprise a ceramic material such as an oxide (silicon dioxide (SiO 2) or aluminum oxide (Al 2 O 3 ), for example), a nitride (silicon nitride (Si3N4) or boron nitride (BN), for example), or an oxynitride. As shown in FIG. 15, the mask layer 232 may be shaped to form apertures 242 that extend through the mask layer 232, thereby providing the treated and bonded semiconductor structure 240 of FIG. Masking and photolithographic etching such as are known in the art can be used to form apertures 242 through mask layer 232. Apertures 242 can be sized, shaped and placed to expose material sacrificial 132 in the through-hole recesses 112 through the openings 242. The semiconductor structure 240 may then be subjected to a wet or dry etching process using an etching agent which is selective for the material. sacrificial 132 with respect to the material of the mask layer 232.

Such an etching process leads to the removal of the sacrificial material 132 from the inside of the vias 112, thus giving the semiconductor structure 250 of FIG. 16. The mask layer 232 can then be removed from the semiconductor structure 250 of Figure 16 to form a semiconductor structure at least substantially identical to the semiconductor structure 200 of Figure 11. In additional processes, during the thinning of the material 102 as it is As seen in the foregoing with reference to FIGS. 9 and 10, the material 102 may be recessed relative to the sacrificial material 132, and / or the optional dielectric material 122, to form the semiconductor structure 260 of FIG. By way of example and not limitation, the material 102 may be recessed relative to the sacrificial material 132, and / or the optional dielectric material 122 of about 2000 angstroms. formation of the semiconductor structure 260 of Fig. 17, a mask layer 272 may be deposited over the semiconductor structure 260 to form the semiconductor structure 270 of Fig. 18. The mask layer 272 may comprise a ceramic material such as an oxide (silicon dioxide (SiO2) or aluminum oxide (Al2O3), for example), a nitride (silicon nitride (Si3N4) or boron nitride (BN), for example), or an oxynitride. As shown in FIG. 18, the semiconductor structure 270 may comprise a main surface 274 on a side thereof opposite the carrier substrate 192. The main surface 274 of the semiconductor structure 270 of FIG. to a planarization process, such as a chemical mechanical polishing (CMP) process, for removing the portion of the mask layer 272 (and portions of any dielectric material 122) above the volume of sacrificial material 132 within the vias 112 to form the treated and glued semiconductor structure 280 of FIG. 19. As shown in FIG. 19, the sacrificial material 132 can be exposed through the mask 272 after planarization of the main surface 274 (Figure 18). When the sacrificial material 132 is exposed, the semiconductor structure 280 can then be subjected to a wet or dry etching process using an etching agent which is selective for the sacrificial material 132 with respect to the material. of the mask layer 272.

Such an etching process results in the removal of the sacrificial material 132 from within the vias 112, thereby providing the treated and bonded semiconductor structure 290 of FIG. 20. The mask layer 272 can be then removed from the semiconductor structure 290 of Fig. 20 to form a semiconductor structure at least substantially identical to the semiconductor structure 200 of Fig. 11, which can then be processed as seen in what follows. above. The formation of vias across the wafer in a multi-step process (a two-step process, for example), as seen in the above with reference to vias across the wafer 214, can improve the efficiency of semiconductor structures satisfactory from the point of view of their operation during manufacture, since the aspect ratios of the different parts of the vias through the wafer are lower than the aspect ratios. full vias through the wafer, which may lead to a simplification of the etching of the vias recesses in which the different portions of vias across the wafer are formed, to an improvement of the coverage of insulating dielectric materials over exposed surfaces inside vias recesses, and improvement of conductive material within the vias of vias to form the different vias of the vias through the wafer. On the other hand, the fabrication of transistors, such as transistors 162 described herein, can subject the semiconductor structure to temperatures of more than about 400 ° C. If a conductive metal were disposed in vias recesses during the treatment of the semiconductor structure at such elevated temperatures, the metal atoms could diffuse into other regions of the semiconductor structure, such diffusion. which can negatively affect the operation of the semiconductor structure. In addition, a mismatch between the thermal expansion coefficients of such a metallic material and surrounding dielectric and semiconductor materials could lead to structural deterioration of the semiconductor structure. By providing a sacrificial material within vias recesses in a semiconductor structure prior to fabrication of the transistors, and replacing the sacrificial material with another conductive material after fabrication of the transistors, it is possible to prevent such structural deterioration or to "reduce the likelihood that such structural deterioration may occur. Additional non-limiting embodiments of the invention are described as follows: Embodiment No. 1: A method of manufacturing a semiconductor structure comprising: providing a sacrificial material within a at least one interconnecting hole recess 10 extending partially through a semiconductor structure; forming a first portion of at least one vias through the wafer in the semiconductor structure, and aligning the first portion of the at least one vias through the wafer with the at least one via hole recess; and replacing the sacrificial material within the at least one vias recess with a conductive material and forming a second portion of the at least one vias through the wafer in electrical contact with the first portion of the at least one via via the wafer. Embodiment 2: A method according to embodiment 1, wherein forming a first portion of at least one via via the wafer in the semiconductor structure further comprises the extension of the first portion of the at least one via hole through the wafer through a dielectric material. Embodiment 3: The method of claim 1 wherein providing the sacrificial material within the at least one via hole recess extending partially through the semiconductor structure comprises: at least one blind via recess extending partially through the semiconductor structure from a surface thereof; and providing at least one of polysilicon, silicon-germanium (SiGe) material, III-V semiconductor material and a dielectric material within the at least one blind via recess . Embodiment 4: A method according to claim 3, wherein the supply of at least one of polysilicon, silicon-germanium (SiGe) material, III-V semiconductor material and a dielectric material to the interior of the at least one blind via recess comprises providing polysilicon material within the at least one blind via recess. Embodiment 5: A method according to Embodiment 3, further comprising forming the at least one via hole recess through a bulk silicon material. Embodiment 6: A method according to embodiment 4, further comprising providing a dielectric material between the bulk silicon material and the polysilicon material within the at least one via hole recess blind. Embodiment 7: A method according to embodiment 3, further comprising providing a thin layer of semiconductor material over a surface of the semiconductor structure after supplying the polysilicon material to the interior of the at least one blind via recess.

Embodiment 8: A method according to embodiment 7, wherein providing the thin layer of semiconductor material over the surface of the semiconductor structure comprises: implanting ions into a substrate comprising a semiconductor material for forming a fracture plane in the substrate; bonding the substrate to the surface of the semiconductor structure; and fracturing the substrate along the fracture plane and separating the thin layer of semiconductor material from a remaining portion of the substrate, the thin layer of semiconductor material remaining adhered to the surface of the semiconductor structure . Embodiment 9: A method according to embodiment 8, wherein bonding the substrate to the surface of the semiconductor structure comprises bonding the substrate directly to the surface of the semiconductor structure. Embodiment 10: A method according to embodiment 7, further comprising forming at least a portion of a device structure by means of the thin layer of semiconductor material. Embodiment 11: The method according to Embodiment 10, wherein forming the at least a portion of the device structure by means of the thin layer of semiconductor material comprises forming at least a portion of a transistor by means of the thin layer of semiconductor material. Embodiment 12: A method according to embodiment 7, wherein providing the thin layer of semiconductor material over the surface of the semiconductor structure comprises forming the thin layer so as to have an average thickness of about three hundred nanometers (300 nm) or less.

Embodiment 13: A method according to embodiment 12, wherein providing the thin layer of semiconductor material over the surface of the semiconductor structure comprises forming the thin layer so as to have an average thickness of about one hundred nanometers (100 nm) or less. Embodiment 14: A method according to any one of embodiments 1 to 13, further comprising thinning the semiconductor structure after forming the first portion of the at least one through hole through the wafer and before replacing the sacrificial material with the conductive material and forming the second portion of the at least one via via the wafer. Embodiment 15: A method according to embodiment 14, wherein the thinning of the semiconductor structure comprises exposing the sacrificial material to an exterior of the semiconductor structure. Embodiment 16: A method according to embodiment 14, further comprising: attaching the semiconductor structure to a carrier substrate prior to thinning the semiconductor structure; and removing the carrier substrate from the semiconductor structure after thinning the semiconductor structure. Embodiment 17: A method of manufacturing a semiconductor structure comprising: providing a sacrificial material within at least one via hole recess extending in a surface of a semiconductor structure; providing a layer of semiconductor material over the surface of the semiconductor structure; fabricating at least one device structure by means of the layer of semiconductor material; forming a first portion of at least one vias through the wafer extending through the layer of semiconductor material; thinning the semiconductor structure from a side thereof opposite the semiconductor material layer; the removal of the sacrificial material from the inside. at least one vias recess in the semiconductor structure and exposing the first portion of the at least one vias through the wafer within the vias recess; and providing conductive material within the via hole recess and forming a second portion of the at least one vias through the wafer. Embodiment 18: A method according to embodiment 17, wherein providing the sacrificial material within the at least one via hole recess comprises supplying polysilicon material within the at least one vi a vias recess.

Embodiment 19: A method according to embodiment 17 or 18, further comprising providing a dielectric material between the sacrificial material and the semiconductor structure within the at least one hole recess. interconnection. Embodiment 20: A method according to any one of embodiments 17 to 19, wherein the supply of the layer of. Semiconductor material above the surface of the semiconductor structure comprises transferring the layer of semiconductor material from a substrate to the semiconductor structure. Embodiment 21: A method according to embodiment 20, wherein the transfer of the semiconductor material layer from a substrate to the semiconductor structure comprises: implanting ions into the substrate; bonding the substrate to the semiconductor structure; and fracturing the substrate along a plane defined by the ions implanted inside the substrate, and separating the layer of semiconductor material from a remaining portion of the substrate. Embodiment 22: A method according to any one of embodiments 17 to 21, wherein providing the layer of semiconductor material over the surface of the semiconductor structure comprises selecting the layer of semiconductor material so as to have an average thickness of about one hundred nanometers (100 nm) or less.

Embodiment 23: A method according to any one of embodiments 17 to 22, further comprising: attaching the semiconductor structure to a carrier substrate prior to thinning the semiconductor structure; and removing the carrier substrate from the semiconductor structure after thinning the semiconductor structure. Embodiment 24: A method according to any one of embodiments 17 to 23, further comprising forming a conductive bump on the at least one vias through the wafer. Embodiment 25: Semiconductor structure, comprising: a sacrificial material within at least one via hole recess extending partially through a semiconductor structure from a surface of the semi structure -conductive; a semiconductor material disposed above the surface of the semiconductor structure; at least one thin device structure comprising at least a portion of the semiconductor material disposed above the surface of the semiconductor structure; a first portion of at least one via via the wafer extending through the semiconductor material disposed above the surface of the semiconductor structure, the first portion of the at least one interconnecting across the wafer being aligned with the at least one via hole recess. Embodiment No. 26: Semiconductor structure according to Embodiment 25, further comprising a volume of dielectric material at least partially surrounded by the semiconductor material disposed above the surface of the semiconductor structure, the first portion of the at least one via hole therethrough extending through and being in direct contact with the volume of dielectric material. Embodiment No. 27: Semiconductor structure according to Embodiment 26, wherein the volume of dielectric material comprises a shallow trench isolation structure. Embodiment 28: A semiconductor structure according to any one of embodiments 25 to 27, wherein the sacrificial material comprises a polysilicon material. Embodiment No. 29: A semiconductor structure according to any one of embodiments 25 to 28, wherein the at least one device structure comprises at least one transistor. Y '+ Embodiment No. 30: Semiconductor structure according to any one of Embodiments 25 to 29, wherein the sacrificial material is exposed to an exterior of the semiconductor structure on one side of that it is opposed to the semiconductor material disposed above the surface of the semiconductor structure. Embodiment 31: A semiconductor structure according to any one of embodiments 25 to 30, further comprising a carrier substrate attached to the semiconductor structure. Embodiment 32: A semiconductor structure according to any one of embodiments 25 to 31, wherein the semiconductor material disposed above the surface of the semiconductor structure comprises a layer of semi-conductive material conductor having an average thickness of about three hundred nanometers (300 nm) or less. Embodiment 33: A semiconductor structure according to embodiment 32, wherein the layer of the semiconductor material has an average thickness of about one hundred nanometers (100 nm) or less. Embodiment 34: Semiconductor structure, comprising: an active surface; a back surface; at least one transistor placed inside the semiconductor structure between the active surface and the rear surface; at least one via via the wafer extending at least partially through the semiconductor structure from at least one of the active surface and the back surface, the at least one via through the wafer comprising: a first part; a second part; and an identifiable boundary between a microstructure of the first portion and a microstructure of the second portion. Embodiment No. 35: Semiconductor structure according to Embodiment 34, wherein the at least one transistor comprises at least a portion of a thin layer of semiconductor material. Embodiment 36: Semiconductor structure according to Embodiment 35, wherein the thin layer of semiconductor material has an average thickness of about one hundred nanometers (100 nm) or less. Embodiment 37: Semiconductor structure according to embodiment 35 or 36, wherein the identifiable boundary is placed in proximity to a major surface of the thin layer of semiconductor material. Embodiment 38: A semiconductor structure according to any one of embodiments 34 to 37, wherein the identifiable boundary is oriented parallel to at least one of the active surface and the back surface.

Claims (33)

REVENDICATIONS1. A method of manufacturing a semiconductor structure comprising: providing a sacrificial material within at least one via hole recess partially extending through a semiconductor structure; forming a first portion of at least one vias through the wafer in the semiconductor structure, and aligning the first portion of the at least one vias through the wafer with the at least one via hole recess; and replacing the sacrificial material within the at least one vias recess with a conductive material and forming a second portion of the at least one vias through the wafer in electrical contact with the first part of the at least one via via the wafer. The method of claim 1, wherein forming a first portion of at least one interconnecting hole through the wafer in the semiconductor structure further comprises extending the first portion of the at least one via hole through the wafer through a dielectric material. 30 The method of claim 1, wherein providing the sacrificial material within the at least one via hole recess extending partially through the semiconductor structure comprising: forming at least one blind via recess extending partially through the semiconductor structure from a surface thereof; and providing at least one of polysilicon, silicon-germanium (Site) material, III-V semiconductor material and a dielectric material within the at least one blind via recess . The method of claim 3, wherein providing at least one of polysilicon, silicon-germanium (SiGe) material, III-V semiconductor material and dielectric material within the at least one blind via recess comprises providing polysilicon material within the at least one blind via recess. The method of claim 3, further comprising forming the at least one vias recess through a bulk silicon material. The method of claim 5, further comprising providing a dielectric material between the bulk silicon material and the polysilicon material within the at least one blind via hole recess. The method of claim 3, further comprising providing a thin layer of semiconductor material over a surface of the semiconductor structure after supplying the polysilicon material within the at least one recess. of blind interconnection hole. The method of claim 7, wherein providing the thin layer of semiconductor material over the surface of the semiconductor structure comprises: implanting ions into a substrate comprising a semiconductor material for forming a fracture plane in the substrate; bonding the substrate to the surface of the semiconductor structure; and fracturing the substrate along the fracture plane and separating the thin layer of semiconductor material from a remaining portion of the substrate, the thin layer of semiconductor material remaining adhered to the surface of the semiconductor structure. conductive. 20 The method of claim 8, wherein bonding the substrate to the surface of the semiconductor structure comprises direct bonding of the substrate to the surface of the semiconductor structure. 25 The method of claim 7, further comprising forming at least a portion of a device structure by means of the thin layer of semiconductor material. 30 The method of claim 10, wherein forming the at least a portion of the device structure by means of the thin layer of semiconductor material comprises forming at least a portion of a transistor by means of the thin layer of semiconductor material. The method of claim 7, wherein providing the thin layer of semiconductor material over the surface of the semiconductor structure comprises forming the thin layer so as to have an average thickness of about three. hundred nanometers (300 nm) or less. The method of claim 12, wherein providing the thin layer of semiconductor material over the surface of the semiconductor structure comprises forming the thin layer so as to have an average thickness of about one hundred nanometers (100 nm) or less. The method of claim 1, further comprising thinning the semiconductor structure after forming the first portion of the at least one vias through the wafer and prior to replacing the sacrificial material with the conductive material. and forming the second portion of the at least one via via the wafer. The method of claim 14, wherein thinning the semiconductor structure comprises exposing the sacrificial material to an exterior of the semiconductor structure. The method of claim 14, further comprising: attaching the semiconductor structure to a carrier substrate prior to thinning the semiconductor structure; andeliminating the carrier substrate from the semiconductor structure after thinning the semiconductor structure. A method of manufacturing a semiconductor structure comprising: providing a sacrificial material within at least one via hole recess extending in a surface of a semiconductor structure; providing a layer of semiconductor material over the surface of the semiconductor structure; fabricating at least one device structure by means of the layer of semiconductor material; forming a first portion of at least one vias through the wafer extending through the layer of semiconductor material; thinning the semiconductor structure 20 from a side thereof opposite the semiconductor material layer; removing the sacrificial material from within the at least one via hole recess in the semiconductor structure and exposing the first portion of the at least one vias through the wafer inside of the via hole recess; and providing conductive material within the vias recess and forming a second portion of the at least one vias through the wafer. The method of claim 17, wherein providing the sacrificial material within the at least one via hole recess comprises supplying polysilicon material within the at least one via hole recess. . The method of claim 17 further comprising providing a dielectric material between the sacrificial material and the semiconductor structure within the at least one via hole recess. The method of claim 17, wherein providing the layer of semiconductor material over the surface of the semiconductor structure comprises transferring the layer of semiconductor material from a substrate to the semiconductor structure. -conductrice. The method of claim 20, wherein the transfer of the semiconductor material layer from a substrate to the semiconductor structure comprises: implanting ions into the substrate; bonding the substrate to the semiconductor structure; and fracturing the substrate along a plane defined by the ions implanted inside the substrate; and separating the layer of semiconductor material from a remaining portion of the substrate. The method of claim 17, wherein providing the layer of semiconductor material over the surface of the semiconductor structure comprises selecting the layer of semiconductor material to have an average thickness of about one hundred nanometers (100 nm) or less. 23. The method of claim 17, further comprising: attaching the semiconductor structure to a carrier substrate prior to thinning the semiconductor structure; and removing the carrier substrate from the semiconductor structure after thinning the semiconductor structure. 10 The method of claim 17, further comprising forming a conductive bump on the at least one vias through the wafer. 15 A semiconductor structure comprising: a sacrificial material within at least one via hole recess extending partially through a semiconductor structure from a surface of the semiconductor structure; A semiconductor material disposed above the surface of the semiconductor structure; at least one device structure comprising at least a portion of the semiconductor material disposed above the surface of the semiconductor structure; A first portion of at least one vias through the wafer extending through the semiconductor material disposed above the surface of the semiconductor structure, the first portion of the at least one interconnecting across the wafer being aligned with the at least one via hole recess. The semiconductor structure of claim 25, further comprising a volume of dielectric material at least partially surrounded by the semiconductor material disposed above the surface of the semiconductor structure, the first portion of the at least one hole interconnection through the wafer extending through and being in direct contact with the volume of dielectric material. The semiconductor structure of claim 26, wherein the volume of dielectric material comprises a shallow trench isolation structure. The semiconductor structure of claim 25, wherein the sacrificial material comprises a polysilicon material. The semiconductor structure of claim 25, wherein the at least one device structure comprises at least one transistor. 20 The semiconductor structure of claim 25, wherein the sacrificial material is exposed to an exterior of the semiconductor structure on a side thereof opposite the semiconductor material disposed above the surface of the semiconductor structure. the semiconductor structure. 31. The semiconductor structure of claim 30, further comprising a carrier substrate attached to the semiconductor structure. The semiconductor structure of claim 25, wherein the semiconductor material disposed above the surface of the semiconductor structure comprises a layer of semiconductor material having an average thickness of about three hundred nanometers (300 nm) or less. The semiconductor structure of claim 32, wherein the layer of the semiconductor material has an average thickness of about one hundred nanometers (100 nm) or less.