FR2964245A1 - Method for planarizing sealing layer of dimensional substrate used in semiconductor industry, involves polishing sacrificial layer and surface irregularities of sealing layer, where sacrificial layer is formed of material - Google Patents

Method for planarizing sealing layer of dimensional substrate used in semiconductor industry, involves polishing sacrificial layer and surface irregularities of sealing layer, where sacrificial layer is formed of material Download PDF

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Publication number
FR2964245A1
FR2964245A1 FR1056862A FR1056862A FR2964245A1 FR 2964245 A1 FR2964245 A1 FR 2964245A1 FR 1056862 A FR1056862 A FR 1056862A FR 1056862 A FR1056862 A FR 1056862A FR 2964245 A1 FR2964245 A1 FR 2964245A1
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Prior art keywords
layer
sacrificial layer
polishing
method according
surface irregularities
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FR1056862A
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French (fr)
Inventor
Gregory Riou
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Soitec Silicon on Insulator Technologies SA
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Soitec Silicon on Insulator Technologies SA
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Priority to FR1056862A priority Critical patent/FR2964245A1/en
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • H01L21/31053Planarisation of the insulating layers involving a dielectric removal step

Abstract

The present invention relates to a method of flattening a covering layer (40) of a substrate (30), the covering layer (40) having surface irregularities (42) corresponding to surface irregularities (32). substrate (30), characterized in that it comprises steps of: (a) depositing a sacrificial layer (50) on the cover layer (40); (b) polishing the sacrificial layer (50) and surface irregularities (42) of the cover layer (40), the sacrificial layer (50) being made of a material more resistant to polishing than the layer material covering (40).

Description

GENERAL TECHNICAL FIELD

The present invention relates to the field of three-dimensional substrates used in the semiconductor industry.

More specifically, it relates to a planarization process.

STATE OF THE ART

Semiconductor structures serve as a basis for the electronics industry. To improve performance, methods for increasing the density of engraved circuits per unit area have been developed. However, we are getting closer to a physical limit. This is why three-dimensional integration methods have emerged: instead of always reducing the size of the circuits, they are stacked in 3D structures and connected by vertical interconnections. The circuits, which are in relief, are embedded in a layer of dielectric material. The problem is that the surface of the dielectric layer remains in accordance with the initial topology of the substrate on which it is deposited: the tracks of the circuits generate peaks on the surface of the dielectric. However, if one wants to be able to stick solid layers between them, these layers must be perfectly flat. FIG. 1 shows a substrate 30 comprising circuits, the tracks of which form surface irregularities 32, covered by a covering layer 40 made of dielectric material. The deposition of the covering layer 40 must therefore be followed by a flattening of the surface by polishing, many techniques being known to those skilled in the art. In an ideal case, this step makes it possible to obtain a surface of the covering layer 40 having no topology as shown in FIG. 2 (perfect surface 41). The covering layer 40 can thus be assembled to another substrate by molecular bonding. In fact, polishing has limitations. The Xiaolin Xie et al. Paper, "Re-Examining the Physical Basis of Pattern Density and Step Height CMP Models," MRS 2003 CMP Symposium, highlights that even after polishing, there is still a residual topology. Indeed, numerical simulations show that the peaks are initially polished faster than the hollows, but that when the topology decreases, the polishing rates of the peaks and hollows meet (the polishing speed of the peaks being always greater than that of the poles). hollow), thus maintaining a residual topology. FIG. 3 illustrates this phenomenon, the profiles of the topologies on the plates being plotted for successive polishing times of 5 seconds. The control of the uniformity of thickness of the dielectric layer after polishing thus remains very difficult, even at the cost of the removal of a very large amount of material on the covering layer 40. Indeed, one of the only solutions is to deposit a thick layer of coating, and polish it long enough to achieve the desired leveling. Such a method is long and very expensive since large amounts of the material of the covering layer 40 are wasted. Even more the removal of material necessary for the surface planarization is important, worse is the uniformity in thickness of the covering layer. In addition, the formation of interconnections (or "vias") between components formed in different levels of integration is realized, after assembly of two processed plates and thinning of one of them, by deep etching through the layers bonding, and filling these "vias" thus formed by a conductive material, typically copper. In order to allow the realization of these interconnections reliably over the entire surface of the plate, it is essential that the thickness of the covering layer is as uniform as possible, for example by limiting the thickness variations of the coating layer. covering at 15% of its average thickness.

PRESENTATION OF THE INVENTION

The present invention aims to solve these difficulties by proposing a method for obtaining a quasi-uniformity of thickness of the covering dielectric layer. An ancillary purpose of this process is to achieve this result with much less material removal than in the known processes. For this purpose, the present invention relates to a method for flattening a substrate covering layer, the covering layer having surface irregularities corresponding to surface irregularities of the substrate, characterized in that comprises steps of: (a) conformally depositing a sacrificial layer on the cover layer; (b) polishing the sacrificial layer and surface irregularities of the cover layer, the sacrificial layer consisting of a material such that the material removal rate of the sacrificial layer is less than or equal to the speed of removal of material from the covering layer during polishing.

Contrary to the phenomena described in the Xiaolin Xie et al. Paper, "Re-Examining the physical basis of pattern density and step height CMP models", MRS 2003 CMP Symposium, thanks to this sacrificial layer, when the surface irregularities of the layer The polishing rate becomes selective: the polishing speed of the peaks remains lower than the polishing speed of the cavities, filled with the stronger material which protects the covering layer. A very rough surface is obtained, with removal of material from the minimum covering layer, since only the peaks have been etched. According to other advantageous and nonlimiting characteristics: the polishing performed in step (b) is a chemical-mechanical polishing; the material removal rate of the polishing is greater than 50 A / s for the covering layer, and is between 20 and 40 A / s for the sacrificial layer; the polishing carried out in step (b) is a partial polishing, the remainders of the sacrificial layer being left in recesses present between the surface irregularities of the covering layer; the partial polishing is carried out until the variation of the thickness of the covering layer is less than 5%; - The method further comprises a step (c) of selectively removing the remainders of the sacrificial layer; step (c) consists of an etching with phosphoric acid; the covering layer consists of a material chosen from one of the following materials: tetraethoxysilane, silane; the sacrificial layer consists of an oxide, a nitride or an oxynitride, aluminum, silicon or hafnium; the cover layer and / or the sacrificial layer is deposited by plasma-assisted chemical vapor deposition at a temperature below 400 ° C .; - Surface irregularities of the substrate are remaining portions of a conductive layer initially covering the substrate and partially removed; surface irregularities consist of copper; The substrate is made of a material chosen from one of the following materials: Si, SiC, SiGe, glass, a ceramic, a metal alloy; the thickness of the sacrificial layer is between 1 and 3 times the height of the surface irregularities of the substrate. 30 PRESENTATION OF THE FIGURES

Other features and advantages of the present invention will appear on reading the following description of a preferred embodiment. This description will be given with reference to the accompanying drawings in which: - Figure 1 previously described is a diagram of a cross section of a substrate candidate for the planarization process according to the invention; - Figure 2 previously described is a diagram of a cross section of a substrate after polishing theoretically perfect; FIG. 3 is a graph illustrating the topologies of a substrate measured every 5s during a known planarization process; FIGS. 4 to 7 are cross-sectional diagrams of a substrate during the successive steps of an embodiment of a planarization method according to the invention.

DETAILED DESCRIPTION Structure of the initial substrate

The thinning process according to the invention is intended for any semiconductor substrate composed of a substrate 30 covered with a covering layer 40, the substrate 30 having surface irregularities 32, as described above. By way of example, the surface irregularities 32 are conductive lines that connect the components that one wishes to integrate directly inside the semiconductor structure. It is these lines, slightly raised in relation to the surface 34 of the substrate, which are the main contribution to the topology of the surface of the substrate 30. Their thickness ranges from about ten Angstroms to a few thousand Angstroms. The process according to the invention is particularly applicable for thicknesses of surface irregularities 32 of a few hundred Angstroms. This conductive material, which is advantageously copper for its very good conductivity, is generally derived from an initial layer of copper covering the substrate 30 and partially removed in a predetermined pattern. Many selective etching techniques allowing this partial elimination are known to those skilled in the art. Alternatively, it is possible to deposit a surface layer, to etch it selectively to form cavities, and then to fill them with copper, in particular by electrodepositing electrolysis. The invention is however not limited to any of these methods. The substrate 30 may consist of all the materials usually used in the semiconductor industry, in particular based on silicon (Si, SiC, SiGe), glass, ceramic, or a metal alloy.

The choice of the material can be made according to the desired electrical properties (insulator / conductor) and materials envisaged for the upper layers, to the appreciation of those skilled in the art. The covering layer 40 which covers the substrate 30 and the conductive lines which form the irregularities 32, is advantageously insulating. Of the dielectric materials, some are preferred, such as tetraethoxysilane (TEOS) or silane, for their physicochemical properties: they can be advantageously deposited by PECVD. PECVD, a plasma-enhanced chemical vapor deposition (PECVD), is a known method of depositing a thin layer on a substrate from a gaseous state that allows to obtain small thicknesses equal to or even less than one micron. Thus, in a particularly advantageous embodiment, a 0.5 to 1 micron TEOS oxide coating layer 40 (depending on the thickness of the surface irregularities) is deposited by PECVD at a temperature below 400 ° C. in order not to deteriorate the covered components. Copper diffusion can actually occur from 420 ° C. As previously explained and shown in the figures, the surface irregularities 32 generate the same surface irregularities 42 for the cover layer 40.

Deposit of the sacrificial layer

The process according to the invention starts with the conformal deposition of a sacrificial layer 50 on the covering layer 40. By conforming means that the surface of the sacrificial layer 50 follows the topology of the surface of the covering layer 40 In other words, the surface irregularities 42 in turn generate the same irregularities 52 for the sacrificial layer 50, as shown in FIG. 4. The thickness of this sacrificial layer 50 is advantageously between 1 and 3 times the height of the surface irregularities 32 of the substrate 30, counted from the surface 34. It should be understood that it is necessary to be sure of at least covering the irregularities 42 of the covering layer 40, but it is useless for it to be too thick since it is a sacrificial layer, and therefore doomed to be eliminated. The material of the sacrificial layer 50 must be of a different nature from that of the material of the covering layer 40, and in particular be at least as resistant to polishing. In other words, the sacrificial layer 50 is made of a material such that the material removal rate of the sacrificial layer 50 is less than or equal to the material removal rate of the cover layer 40 during polishing. Advantageously, the rate of removal of material by polishing the sacrificial layer 50 is 20% lower than the material removal rate by polishing the covering layer 40. This allows, as will be seen below, a polishing selective very effective on the peaks.

The materials that are advantageous for the sacrificial layer 50 are hard materials that are easily deposited in a thin layer, in particular oxides, nitrides and oxynitrides of metals such as aluminum, silicon or hafnium (Al 2 O 3, AlN, Si3N4, SiON, HfO2 ...). These materials are advantageously deposited by PECVD, in the same way as for the covering layer 40. Thus, in a particularly preferred embodiment, the sacrificial layer consists of Si3N4 silicon nitride with a thickness of about 3000A and deposited by PECVD in a temperature range always below 400 ° C to also not damage the buried components.

Polishing After the deposition of the sacrificial layer 50, polishing is carried out. Advantageously, this polishing is a chemical mechanical polishing (CMP). Polishing CMP, "Chemical-Mechanical Polishing" in English terminology consists of a hybrid polishing by the combination of a chemical action and a mechanical force. A fabric, the "pad", is applied with pressure to the rotating surface of the material. A chemical solution, "slurry", advantageously containing suspended microparticles, typically colloids, is applied to the material. The slurry circulates between the surface and the pad and increases the effectiveness of polishing.

The CMP technology makes it possible to precisely adjust the polishing speeds by choosing the slurry / pad pair depending on the material to be polished. In particular, the material removal rate of the chemical mechanical polishing used in the process according to the invention is advantageously greater than 50 A / s for the covering layer 40, and between 20 and 40 A / s for the layer. At the beginning of the polishing step, only the sacrificial layer 50 is etched. In accordance with the phenomena presented above, a residual topology is maintained as the polishing proceeds, until the surface irregularities 42 of the covering layer 40 are reached. The polishing then allows a material removal at least as important at the peaks as the hollows since the zones 42 are exposed to the polishing step without the zones 44 are. This intermediate situation is thus schematized in FIGS. 5 and 6. Continuing the polishing in the case where the covering layer 40 is made of a material that is less resistant to polishing than that of the sacrificial layer 50, a phenomenon called the "dishing" (of dish , plate, in English terminology) may occur: the removal of material at the peaks becomes greater than at the level of the hollows, and cuvettes appear between the remains 54 of the sacrificial layer 50, as can be see figure 7.

Depending on the choice of the material of the sacrificial layer 50 and its thickness, it is possible to delay the maximum dishing, and theoretically obtain a perfect surface state when the entire surface layer 50 finishes being eliminated by polishing. Alternatively, the polishing is partial. In order not to affect and risk damaging the covering layer 40, it is then preferable not to continue the polishing and to stop while there is still a remainder of material 54 of the sacrificial layer 50 in the recesses 44 present between the surface irregularities 42 (which have however already been eliminated at this time). Advantageously, the polishing is continued until the uniformity, characterized by the variation of the thickness of the covering layer 40, is below 5%, or even below 3%.

Engraving In the case of partial polishing, the residues 54 of the sacrificial layer 50 are advantageously selectively removed, for example by means of selective etching. Those skilled in the art will be able to adapt the chemistries used for this etching to the materials of the sacrificial layer 50 and the covering layer 40. Advantageously, use will be made of hot phosphoric acid (H 3 PO 4), especially if the sacrificial layer is made of silicon nitride. This step makes it possible to remove the remains of the sacrificial layer 50 without affecting the covering layer 40, whose surface state has remarkably improved. It is possible to repeat the flattening method according to the invention as many times as desired if it is desired to further improve the topology and reach the perfect surface state 41 of FIG. 2. Advantageously, it is possible to lastly a step called "mirror polishing" (polishing with soft tissue) which aims to reduce the micro roughness to a final value of the order of Angstrom (on a scan size of 2 by 2 microns). This finishing polishing step leads to a very low material removal (for example 200A) without deteriorating the uniformity of the covering layer 40.

Use of the Flattened Substrate After the surface of the substrate thus prepared, this substrate can be assembled by molecular bonding with another, according to known techniques. Reinforcement annealing of the bonding interface may be carried out at a moderate temperature of less than 400 ° C. One of the two substrates can then be thinned, mechanically and / or chemically. The steps of finalizing the components (vias formation, interconnections, possible overlays of other layers) can finally continue in a manner conventionally known per se.

Claims (14)

  1. REVENDICATIONS1. A method of flattening a cover layer (40) of a substrate (30), the cover layer (40) having surface irregularities (42) corresponding to surface irregularities (32) of the substrate (30) , characterized in that it comprises steps of: (a) conformally depositing a sacrificial layer (50) on the cover layer (40); (b) polishing the sacrificial layer (50) and surface irregularities (42) of the cover layer (40), the sacrificial layer (50) being made of a material such as the material removal rate of the sacrificial layer (50) is less than or equal to the material removal rate of the cover layer (40) during polishing.
  2. 2. Method according to the preceding claim, wherein the polishing performed in step (b) is a chemical mechanical polishing.
  3. 3. Method according to one of claims 1 and 2, wherein the material removal rate of the polishing is greater than 50 A / s for the covering layer (40), and is between 20 and 40 A / s For the sacrificial layer (50).
  4. 4. Method according to one of the preceding claims, wherein the polishing performed in step (b) is a partial polishing, the remainders (54) of the sacrificial layer (50) being left in recesses 30 (44) present between the surface irregularities (42) of the covering layer (40).
  5. 5. Method according to the preceding claim, wherein the partial polishing is performed until the variation of the thickness of the covering layer (40) is less than 5%.
  6. 6. Method according to one of claims 4 and 5, further comprising a step (c) of selective removal of the remainders (54) of the sacrificial layer (50).
  7. 7. Method according to the preceding claim, wherein step (c) consists of an etching with phosphoric acid.
  8. 8. Method according to one of the preceding claims, wherein the covering layer (40) is made of a material selected from one of the following materials: tetraethoxysilane, silane.
  9. 9. Method according to one of the preceding claims, wherein the sacrificial layer (50) consists of an oxide, a nitride or an oxynitride, aluminum, silicon or hafnium.
  10. The method according to one of claims 8 and 9, wherein the cover layer (40) and / or the sacrificial layer (50) is deposited by plasma-enhanced chemical vapor deposition at a temperature below 400 ° C. .
  11. The method according to one of the preceding claims, wherein the surface irregularities (32) of the substrate (30) are remaining portions of a conductive layer initially covering the substrate (30) and partially removed.
  12. 12. Method according to the preceding claim, wherein the surface irregularities (32) consist of copper. 20 25 30 5
  13. 13. Method according to one of the preceding claims, wherein the substrate (30) is made of a material selected from one of the following materials: Si, SiC, SiGe, glass, a ceramic, a metal alloy.
  14. 14. Method according to one of the preceding claims, wherein the thickness of the sacrificial layer (50) is between 1 and 3 times the height of the surface irregularities (32) of the substrate (30).
FR1056862A 2010-08-30 2010-08-30 Method for planarizing sealing layer of dimensional substrate used in semiconductor industry, involves polishing sacrificial layer and surface irregularities of sealing layer, where sacrificial layer is formed of material Withdrawn FR2964245A1 (en)

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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0678914A2 (en) * 1994-04-18 1995-10-25 Advanced Micro Devices Inc. Method for planarizing an integrated circuit topography
US5532191A (en) * 1993-03-26 1996-07-02 Kawasaki Steel Corporation Method of chemical mechanical polishing planarization of an insulating film using an etching stop
US5618381A (en) * 1992-01-24 1997-04-08 Micron Technology, Inc. Multiple step method of chemical-mechanical polishing which minimizes dishing
US5721172A (en) * 1996-12-02 1998-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned polish stop layer hard masking method for forming planarized aperture fill layers
WO1999046081A1 (en) * 1998-03-11 1999-09-16 Strasbaugh Multi-step chemical mechanical polishing process and device
US5981354A (en) * 1997-03-12 1999-11-09 Advanced Micro Devices, Inc. Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process
JP2000100819A (en) * 1998-09-24 2000-04-07 Sanyo Electric Co Ltd Flattening method of insulating film
US6180510B1 (en) * 1992-11-27 2001-01-30 Nec Corporation Method of manufacturing a substantially flat surface of a semiconductor device through a polishing operation

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5618381A (en) * 1992-01-24 1997-04-08 Micron Technology, Inc. Multiple step method of chemical-mechanical polishing which minimizes dishing
US6180510B1 (en) * 1992-11-27 2001-01-30 Nec Corporation Method of manufacturing a substantially flat surface of a semiconductor device through a polishing operation
US5532191A (en) * 1993-03-26 1996-07-02 Kawasaki Steel Corporation Method of chemical mechanical polishing planarization of an insulating film using an etching stop
EP0678914A2 (en) * 1994-04-18 1995-10-25 Advanced Micro Devices Inc. Method for planarizing an integrated circuit topography
US5721172A (en) * 1996-12-02 1998-02-24 Taiwan Semiconductor Manufacturing Company, Ltd. Self-aligned polish stop layer hard masking method for forming planarized aperture fill layers
US5981354A (en) * 1997-03-12 1999-11-09 Advanced Micro Devices, Inc. Semiconductor fabrication employing a flowable oxide to enhance planarization in a shallow trench isolation process
WO1999046081A1 (en) * 1998-03-11 1999-09-16 Strasbaugh Multi-step chemical mechanical polishing process and device
JP2000100819A (en) * 1998-09-24 2000-04-07 Sanyo Electric Co Ltd Flattening method of insulating film

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