FR2957191A1 - Electrical interconnection support structure i.e. interposer, fabricating method for e.g. micro electromechanical system integrated circuits, involves depositing electric contact point on upper face at level of wire, and removing backplate - Google Patents

Abstract

The method involves forming conductive plugs on upper and lower faces of a substrate (1) i.e. wafer. A backplate is integrated with one of the plugs. A recess (6) traversing thickness of the substrate, is formed. A conductive wire (4) is formed inside the recess, where the wire connects the plugs. The recess is filled with insulating material (5) to electrically insulate the wire from the substrate. A portion of conductive wire is removed from the recess. An electric contact point (23) is deposited on the upper face at the level of the wire. The backplate is removed. An independent claim is also included for an integrated circuit interconnection support structure comprising a substrate.

Description

ELECTRICAL INTERCONNECTION SUPPORT STRUCTURE FOR INTEGRATED CIRCUITS, AND METHOD FOR MANUFACTURING THE SAME

The invention relates to the field of electrical interconnection supports for integrated circuits, also called "interposera" in English. More specifically, the invention relates to an interconnection support structure and to a method for manufacturing such a support structure for integrated circuits, in particular of the MEMS type (English acronym for "microelectromechanical system" in English). or "electromechanical microsystem" in French).

15 Prior art

In general, an "interposer" or electrical interconnection carrier (or "interposera" in English) is a part intended to receive integrated circuits (or chips) and to provide an electrical connection of these circuits. In other words, this support is an electrical connection interface between circuits.

Such a support is generally made in a substrate provided with vias (or electrical interconnections or "vias" in English), for example of the type TSV (acronym for "Through Silicon Vias"). These "vias" are vertical conductive elements traversing the entire thickness of the substrate and allowing electrical connection from one point to another across the substrate layer. This interconnection support makes it possible, in particular, to adapt an integrated circuit to different transfer modes on a standard electronic card, but also allows the assembly, wiring and connection of integrated circuits. Thus, it is possible to interconnect the circuits together by performing a stack of chips of different or identical nature, such as, for example, a stack of memory capacities, the transmission of the electrical signals being done via these vias. . This feature has the advantage of reducing the space occupied by the circuits connected to each other, and therefore reducing the size of the housing containing these circuits.

A method of manufacturing such an interconnection support may consist in making recesses (or holes) traversing the entire thickness of the substrate constituting the support, in covering the walls of these recesses with a dielectric layer, and in filling these gaps. recesses of a conductive material to form the conductive elements (or vias). This last step is critical. Indeed, when the conductive material does not homogeneously deposit in the recess, the conductive elements may include cavities, in the form of air bubbles, which degrade the conductivity. In addition, since a single air bubble has formed in one of the vias of an interconnection support made according to this manufacturing process, this support is more reliable and therefore more usable. Therefore, poorly controlled, this manufacturing process is likely to generate a lot of waste.

For example, the conductive material may be polycrystalline silicon (Si-poly).

Si-poly electrical interconnections can be made by progressively growing layers of Si-poly from the walls of the recesses, by chemical vapor deposition under reduced pressure or LPCVD (acronym for "low pressure chemical vapor deposition"). "). This method, applicable to silicon substrates, makes it possible to obtain a high-temperature-resistant interconnection support, and thus allows subsequent modifications, for example to directly produce MEMS-type components in the interconnection support. However, the electrical conductivity of the conductive elements (or vias) thus formed is limited to the conductance of the polycrystalline silicon. Too much doping, which could reduce this resistivity, causes particular stresses likely to generate cracks-like defects in the substrate or electrical break of the via. In addition, because of the small thickness of the dielectric layer for electrically isolating the conductive elements of the substrate, parasitic capacitances can appear between these conductive elements and the substrate, inducing errors in the signals. Furthermore, the manufacturing process becomes long and expensive when one seeks to make larger diameter recesses and an insulating layer of greater thickness.

To minimize the electrical resistance of these vias, one solution is to replace the polysilicon with a metal. In this case, the walls of the recesses are covered with an electrically insulating adhesion layer, and are then filled by electroplating. However, this method is long and complex to perform, does not eliminate stray capacitances, and does not offer the same advantages related to resistance to high temperatures.

Presentation of the invention

In this context, the purpose of the present invention is in particular to propose a new method for manufacturing an interconnection support structure for integrated circuits that is free from at least one of the limitations mentioned above. The object of the invention is notably to propose a cheaper and easier manufacturing method, making it possible to obtain a compact interconnection support structure having negligible parasitic capacitances and vias of low resistivity.

These and other objects are achieved by the invention which relates to a method of manufacturing an interconnection support structure for integrated circuits, comprising at least: - the realization of at least a first conductive pad on the upper face of a substrate, and at least one second conductive pad on the underside of said substrate; - securing a counterplate at least said second conductive pad; - Making at least one recess passing through the thickness of the substrate and opening on the second conductive pad; - Making a conductive wire inside the recess, said conductive wire connecting the second conductive pad to the first conductive pad; Filling the recess with an insulating material, so as to electrically isolate the conductive wire from the substrate; eliminating the portion of conductive wire outside the recess; depositing an electrical contact point on the upper face, at the level of the conducting wire, the second conductive pad forming another electrical contact point; And - the elimination of the counterplate.

In other words, the manufacturing method according to the invention consists in particular in making a recess, in drawing a conductive wire between a conductive pad made on one side of the substrate and another conductive pad made on another face of the substrate, and filling the recess of a material to electrically insulate the conductive wire of the substrate.

This manufacturing method, which is simple to implement, makes it possible to obtain an electrical interconnection support (or "interposer") whose recess has a thickness of insulating layer that is relatively large compared with the diameter of the conducting wire to considerably reduce the capacitances. parasites. In addition, this method is compatible with silicon substrates and therefore allows subsequent modifications of the support for the purpose of integrating or directly making MEMS-type components in the silicon interconnect carrier. Moreover, the conducting wire made in this manufacturing process is of a certain continuity and thus ensures optimum conductivity.

The invention also relates to an interconnection support structure for integrated circuits comprising at least: a substrate; - A recess opening on both sides of the upper and lower faces of the substrate; a conductive element disposed in the recess electrically connecting first and second electrical contact points disposed respectively on the upper and lower faces of the substrate; and a volume of insulating material disposed around the conductive element to electrically isolate the conductive element from the substrate. According to the invention, the conductive element is a conductive wire having a solder ball, preferably of the ball-bonding type, at one of its ends.

Preferably, the ratio of the diameter of the recess to the diameter of the conductive element is greater than or equal to 5.

Such a ratio makes it possible to better electrically isolate the conductive wire from the substrate and thus to limit the parasitic capacitances.

BRIEF DESCRIPTION OF THE DRAWINGS Other characteristics and advantages of the invention will emerge clearly from the description which is given below, by way of indication and in no way limitative, with reference to the appended figures, in which: FIG. schematic of the electrical interconnection support structure provided with several electrical connections through or vias, according to one embodiment of the invention; and FIGS. 2 to 10 are diagrams illustrating the steps of the method of manufacturing an interconnect support structure according to an embodiment of the invention.

Detailed presentation of a particular embodiment

With reference to FIG. 1, an electrical interconnection support structure (or "interposera") according to one embodiment of the invention comprises in particular: a substrate 1 which may be a wafer, for example, of oxidized silicon , comprising for example a conductive layer 10 interposed between two dielectric layers 11, 12; - recesses 6 opening on either side of the upper and lower surfaces AV 20 AR of the substrate 1, each recess 6 containing: - a conductive element 4 (or vias) disposed substantially vertically and opening on either side faces of the substrate, as well as a volume of insulating material disposed around the conductive element to electrically isolate the conductive element 4 from the substrate 1, the assembly formed by the conductive element 4 and the volume of the insulating material 5 filling the recess 6; and first and second electrical contact points 23, 24 respectively disposed on the upper face AV and the lower face AR of the substrate 1, each conductive wire 4 connecting one of the first electric contact points 23 to one of the second electrical contact points 24. For example, the diameter of the recess is equal to 2001um and the conductive wire may have a diameter of 20 to 40 microns. Preferably, the ratio of the diameter of the recess to that of the conductive element is greater than or equal to 5. Preferably, the ratio of the thickness of the insulator to the diameter of the conductive wire is greater than or equal to 2 By thickness of the insulation is meant the average value of the distance separating the conductive wire from the wall of the recess. In the case of a wire and a cylindrical recess, this average thickness corresponds substantially to half the difference in the diameters of the recess and the wire. For example, the diameter of the recess is equal to 2001um, and the conductive wire may have a diameter of 20 to 40 microns, the volume of insulating material occupying the rest of the space in the recess. For example, the insulating layer may have an average thickness of 80 to 90 μm.

The method of manufacturing such a support structure according to one embodiment is illustrated in FIGS. 2 to 10, and consists first of all in producing (FIG. 3) a plurality of first conductive pads 21 on the upper face AV of the substrate 1. (Figure 2), and to make several second conductive pads 22 on the lower face AR of the substrate 1. For example, the substrate 1 may have a silicon layer of the order of 3001um and oxide layers of the order of 2μm each. Preferably, the first conductive pads 21 are offset from the second conductive pads 22, that is to say that the first conductive pads 21 are not opposite the second conductive pads 22. The first and second conductive pads 21, 22 may be made by a deposition of a metal layer on the lower surfaces AR and upper AV of the substrate 1, for example a chromium-gold alloy, then by photolithography and etching of these metal layers to form the first and second pads conductors 21, 22.

In practice, a counterplate 3, for example a silicon substrate, is secured (FIG. 4) to the second conductive pads 22, these second conductive pads 22 being found between the counterplate 3 and the dielectric layer 12 of the substrate 1.

Recesses 6 opening on the lower surfaces AR and upper AV substrate 1 are then made (Figure 5), for example by photolithography and deep reactive ion etching (or DRIE acronym for "Deep Reactive 30 Ion Etching"). Each recess 6 emerges on one of the second conductive pads 22. For the sake of clarity, a single recess has been shown in FIGS. 5 to 10.

The next step is to arrange (Figure 6) in each recess 6, a conductive wire 4 forming the conductive element extending from the second conductive pad 22 associated with the recess 6 to a first conductive pad 21. The conductive wire 4 can be a gold wire of micrometric dimensions, made according to a technique of contact transfer better known under the name of "wire-bonding" in English. In practice, one end of the conductive wire 4 is welded to the bottom of the recess 6 on the second conductive pad 22, according to the so-called "bail bonding" technique - a technique that consists of initially producing a solder ball 40 by fusion. ends of the wire, to weld the ball on a metal pad by thermo compression, then pull the conductive wire 4 vertically and weld its other end to the first conductive pad 21. In this particular embodiment, the minimum diameter of the recess 6 is limited by the size of the instruments used to achieve the "wire bonding". Of course, other techniques, such as electrical welding or wedge-bonding, can also be used to weld the conductive wire to the bottom of the recess. The conductive wire 4 of each recess 6 is kept substantially centered between the walls of the recess 6, and an insulating material 5 in liquid form is poured (FIG. 7) into each recess 6 so as to fill said recesses and form a layer for electrically insulating the conductive wire 4 of the substrate 1. A hardening step of the insulating material deposited in liquid form follows, this curing being obtainable, for example, by polymerization, drying or solidification, depending on the type of insulating material used. The upper surface AV of the substrate 1 is then polished (FIG. 8) in such a way as to cut the conducting wire 4, and to remove any residues on the upper surface AV of the substrate 1. A metal layer is then deposited on this upper surface AV to realize (FIG. 9) the first electrical contact points 23 at the level of the conducting wires 4.

Finally, the counterplate 3 is eliminated (FIG. 10). The lower face AR of the substrate 1 is then polished and a metal layer is deposited on this lower face AR in order to take up the contacts on the conductive wires 4. For example, the second electrical contact points 24 are made on the lower face AR of the substrate 1 by photolithography of the metal layer.

It follows from the foregoing that the manufacturing method of the invention makes it possible to obtain a compact interconnect support structure having negligible parasitic capacitances, as well as vias of low resistivity. In addition, this manufacturing method avoids the appearance of air bubble, making the interconnection structure thus produced more reliable, thus providing a better manufacturing rate. The manufacturing process of the invention is therefore less expensive and easier. In addition, this method can be implemented in mass production, which reduces production costs.

The use of this structure allows the connection of different technology circuits and allows in particular to increase the integration density of integrated circuits. The components or products incorporating this support structure manufactured according to the method of the invention can therefore be more compact. In addition, the lengths of electrical interconnection between the circuits being reduced, the signal transmission speed is improved.

Claims (3)

REVENDICATIONS1. A method of manufacturing an interconnection support structure for integrated circuits, characterized in that it comprises at least: - the production of at least a first conductive pad (21) on the upper face (AV) of a substrate (1), and at least one second conductive pad (22) on the underside (AR) of said substrate (1); - securing a counterplate (3) to said second conductive pad (22); the production of at least one recess (6) passing through the thickness of the substrate (1) and opening onto the second conductive pad (22); - Making a conductive wire (4) inside the recess (6), said conductive wire (4) connecting the second conductive pad (22) to the first conductive pad (21); filling the recess (6) with an insulating material (5) so as to electrically isolate the conductive wire (4) from the substrate (1); - Eliminating the portion of conductive wire (4) outside the recess (6); - Deposition of an electrical contact point on the upper face (AV) at the conductive wire (4), the second conductive pad (22) forming another electrical contact point; and removing the counterplate (3). 2. Interconnect support structure for integrated circuits comprising at least: - a substrate (1); A recess (6) opening on either side of the upper (AV) and lower (AR) faces of the substrate (1); - a conductive element (4) disposed in the recess (6) electrically connecting first and second electrical contact points (23, 24) respectively disposed on the upper face (AV) and lower (AR) of the substrate (1); and a volume of insulating material (5) disposed around the conductive element (4) for electrically isolating the conductive element (4) from the substrate (1), characterized in that the conductive element (4) is a conductive wire having a ball (40) solder at one of its ends. Interconnect carrier structure according to Claim 2, characterized in that the ratio of the diameter of the recess (6) to the diameter of the conductive element (4) is greater than or equal to 5.5.