FR2951576B1 - Circuit integre comprenant une borne non dediee de reception d'une haute tension d'effacement programmation - Google Patents

Circuit integre comprenant une borne non dediee de reception d'une haute tension d'effacement programmation

Info

Publication number
FR2951576B1
FR2951576B1 FR0905025A FR0905025A FR2951576B1 FR 2951576 B1 FR2951576 B1 FR 2951576B1 FR 0905025 A FR0905025 A FR 0905025A FR 0905025 A FR0905025 A FR 0905025A FR 2951576 B1 FR2951576 B1 FR 2951576B1
Authority
FR
France
Prior art keywords
undeeded
erration
terminal
receiving
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0905025A
Other languages
English (en)
Other versions
FR2951576A1 (fr
Inventor
Francois Tailliet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR0905025A priority Critical patent/FR2951576B1/fr
Priority to EP10009123A priority patent/EP2317519A1/fr
Priority to EP10013613A priority patent/EP2317520A1/fr
Priority to US12/907,746 priority patent/US8351261B2/en
Priority to US12/907,710 priority patent/US8351260B2/en
Priority to CN201010530530.9A priority patent/CN102044302B/zh
Publication of FR2951576A1 publication Critical patent/FR2951576A1/fr
Application granted granted Critical
Publication of FR2951576B1 publication Critical patent/FR2951576B1/fr
Priority to US13/706,132 priority patent/US8654581B2/en
Priority to US13/706,152 priority patent/US8565017B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)
FR0905025A 2009-10-20 2009-10-20 Circuit integre comprenant une borne non dediee de reception d'une haute tension d'effacement programmation Expired - Fee Related FR2951576B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR0905025A FR2951576B1 (fr) 2009-10-20 2009-10-20 Circuit integre comprenant une borne non dediee de reception d'une haute tension d'effacement programmation
EP10009123A EP2317519A1 (fr) 2009-10-20 2010-09-02 Circuit intégré comprenant une borne non dédié de réception d'une haute tension d'effacement programmation
EP10013613A EP2317520A1 (fr) 2009-10-20 2010-10-13 Dispositif pour fournir une haute tension d'effacement programmation à un circuit intégré
US12/907,710 US8351260B2 (en) 2009-10-20 2010-10-19 Integrated circuit comprising a non-dedicated terminal for receiving an erase program high voltage
US12/907,746 US8351261B2 (en) 2009-10-20 2010-10-19 Device for supplying a high erase program voltage to an integrated circuit
CN201010530530.9A CN102044302B (zh) 2009-10-20 2010-10-20 包括用于接收擦除编程高电压的非专用端子的集成电路
US13/706,132 US8654581B2 (en) 2009-10-20 2012-12-05 Integrated circuit comprising a non-dedicated terminal for receiving an erase program high voltage
US13/706,152 US8565017B2 (en) 2009-10-20 2012-12-05 Device for supplying a high erase program voltage to an integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0905025A FR2951576B1 (fr) 2009-10-20 2009-10-20 Circuit integre comprenant une borne non dediee de reception d'une haute tension d'effacement programmation

Publications (2)

Publication Number Publication Date
FR2951576A1 FR2951576A1 (fr) 2011-04-22
FR2951576B1 true FR2951576B1 (fr) 2011-12-16

Family

ID=42122927

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0905025A Expired - Fee Related FR2951576B1 (fr) 2009-10-20 2009-10-20 Circuit integre comprenant une borne non dediee de reception d'une haute tension d'effacement programmation

Country Status (1)

Country Link
FR (1) FR2951576B1 (fr)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR920006991A (ko) * 1990-09-25 1992-04-28 김광호 반도체메모리 장치의 고전압발생회로
JP5143413B2 (ja) * 2006-12-20 2013-02-13 オンセミコンダクター・トレーディング・リミテッド 半導体集積回路

Also Published As

Publication number Publication date
FR2951576A1 (fr) 2011-04-22

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Effective date: 20200910