FR2949031A1 - Method for synchronization of external event processes on e.g. synchronous time division multiplexing network, involves delaying event process at time during application of phase correction on signal representing event - Google Patents

Abstract

The method involves locating an event, and transmitting a signal representing the event and a time measured by a source, to a destination. Compensation of a phase difference between source subnetworks, by a destination subnetwork is measured. Phase correction is applied on the signal representing the event from the source. The destination delays an event process at a time equal to sum of the time measured by the source and the compensation of the phase difference for a source network, during application of the phase correction. Independent claims are also included for the following: (1) a device for synchronization of event processes on a network, comprising a signal transmitting unit (2) a computer program comprising instructions for performing a method for synchronization of event processes on a network (3) an information medium comprising instructions for performing a method for synchronization of event processes on a network.

Description

The present invention relates to a method and device for synchronizing external events. It applies, in particular, to multimedia communication networks and more particularly synchronous synchronous time division multiplexing (TDM) type networks and isochronous networks. We speak of synchronous networks when the clocks of a network are strictly synchronized in phase and in frequency with a reference clock. Examples of these are SDH-type telecommunication networks (acronym for Synchronous Digital Hierarchy) or home-based audio / video networks for the general public based on the interconnection of several buses as defined by the IEEE1394.1-2004 standard called Standard for High Performance Serial Bus Bridges (standard for high performance serial bus gateways). It should be noted that, in the case where we observe a constant relative phase difference, we speak of mesochronous network (mesochronous, in English) although, by misuse of language, we also use the term synchronous. A TDM type network is a network for conveying several virtual channels on the same communication medium, by channel aggregation, by using time multiplexing on the elementary samples of each of these channels. Thus, the time is divided into time slots (English time slot) of equal and fixed duration, successively intended for different channels, to carry an elementary sample. A TDM cycle comprises a time slot per virtual channel, or VC (for virtual chanel in English) carried on the communication medium. Thus, the cycle is repeated with new elementary samples for each of the virtual channels.

A synchronous TDM type network therefore benefits from the characteristics and properties of a TDM type network and a synchronous type network. An isochronous network is a synchronous network which, like the IEEE Standard 1394a-2000 bus, is characterized by its ability to transmit elementary samples, having a different size per channel but fixed in time, at an appropriate frequency in order to obtain a constant flow of information. One can thus see a synchronous TDM network as an isochronous network of which all the elementary samples have the same size and the same frequency of appearance on the communication medium. The present invention relates more particularly to a synchronous network adapted to the simultaneous presentation of information on several terminals (application type one-to-many or one-tomany in English) or several synchronous information from several terminals to destination of a common terminal (application of many-to-one or many-to-one type in English). The present invention has applications in multi-camera capture systems and distributed displays. If, in a general manner, the field of the present invention is that of synchronous communication networks, more precisely, the invention relates to a synchronous presentation technique of a multiple-detected event within a network interconnection. synchronous TDM type. In the context of the invention, several synchronous TDM subnetworks, or PANs (acronym for Personal Area Network for Personal Area Network) are interconnected via PBN (acronym for PAN Bridge Network for PAN gateway network) , in order to establish connections and to be able to transmit data between the terminals hosted by the different subnets.

Each subnetwork is clocked by a TDM cycle generated by a clock of its own, during interconnection, a technique of the state of the art consists of going through a transitional step to synchronize the TDM cycles in phase, slaving the slave subnetwork clock to the master subnet clock. However, this transient stage disrupts the cycles of the slave subnetworks, and thus disturbs the current data exchanges on the subnetwork at the time of the interconnection. Indeed, a TDM cycle can be lost, generating overflows or gaps in the buffers used for the transfer. To overcome this drawback, the invention is placed in the context where the slave sub-network clocks are slaved to that of the master subnet, for example by maintaining the shifts between constant TDM cycles. Each TDM cycle of each subnet at the same time, but they do not start simultaneously. In the context of the invention, some TDM subnetworks host one or more audio / video sources, and other TDM subnetworks host one or more audio / video destinations. For example, a set of cameras film a scene, and some streams from these cameras are displayed on one or more screens. On simultaneous detection by all cameras of a common event, we want to generate a synchronized action at the screens. The present invention aims, in particular, to solve the following problem: in a network composed of PANs, hosting several sources and audio / video destinations, interconnected via a backbone network (backbone network), the TDM cycles of PAN hosting the sources being synchronized in constant phase, and the TDM cycles of the NAPs hosting the destinations being possibly synchronized in the null phase, how to trigger a simultaneous action at the level of several destinations, by a common event detected simultaneously at the level of several sources? In the state of the art, patent application US 2005/0175037 describes a network composed of several modules connected to one another via optical fibers and radio communications. The clocks of the inputs and outputs of each module are not synchronized, but the network output application clock must be synchronized in zero phase with the network input application clock. To do this, each module calculates a phase shift value between its output clock and its input clock. These phase shifts are then accumulated by the output module to power a PLL (acronym for Phase Loop Locked for locking by phase lock) which slaves the output clock of the network on the input clock of the network. This technique is not applicable to the problem underlying the present invention because it does not describe how to synchronize the instants of processing event notifications.

The present invention aims to remedy these disadvantages. For this purpose, according to a first aspect, the present invention aims at a method for synchronizing event processing on a network comprising at least two so-called source subnetworks each hosting at least one signal source representative of an event and at least one two subnetworks said destinations each hosting at least one destination of said signal representative of an event, said subnetworks having the same cycle duration, characterized in that it comprises: - an event tracking step, during from which each source measures a time elapsed between the beginning of a cycle of the source subnet hosting said source and the detection of an event common to several sources, - a step of transmitting, to each destination, a representative signal of the event and of the duration measured by each source, - a phase difference compensation measurement step between the sub-networks es, by each destination subnet and - at each reception, by a destination, a signal representative of an event from a source, a phase correction application step, during which said destination delays processing of said event by a duration equal to the sum of said duration measured by said source and phase difference compensation for the source network hosting said source.

The present invention offers the advantage of being transparent for the final application, that is to say that no particular protocol is to be implemented at the application level. In addition, the implementation of the present invention does not depend on the number of connected subnets nor the number of destinations or sources. It adapts to different topologies of the network. The present invention, as briefly described above, applies in particular in the context where the cycles of the subnetworks hosting the destinations (destination cycles) are synchronized in zero phase, but not those of the subnetworks hosting the sources. . Before processing a received event notification, a delay consisting of compensation for the offsets between the cycles of the sources, and the time between the beginning of the cycle of the source and the detection of the event is expected. Offset compensation between the cycles of the subnets hosting the sources (source cycles) is calculated by each destination at the initialization of the system. When an event is picked up by a device (audio / video source, for example), it is marked relative to the beginning of the current cycle at the time of detection. The value of a counter, reset at the beginning of each cycle, represents the time between the beginning of the cycle and the event. An event notification composed of this value t as well as the type of event is then inserted into one or more virtual control channels associated with the audio / video data stream. Upon receipt of this event notification, from the beginning of the cycle following the reception, the processing of the event of the aforementioned delay is delayed. The cycle starts of the different networks hosting the sources being shifted, for the same event each source measures a different value t. These differences are balanced by the application of phase difference offsets between the subnets hosting the sources.

According to particular features, the phase difference compensation measurement step between subnetworks hosting sources comprises, for each destination subnet: a phase of determining the phase difference between the rising edges of the clock cycle of said destination subnetwork and the rising edges of each source subnetwork, - a step of selecting a so-called reference source subnetwork and - a step of determining the offset between rising edges between the source subnetwork of reference and each other source subnet. According to particular features, during the step of transmitting said measured duration, each source performs an insertion of information relating to the event into a dedicated virtual data flow control channel, the data flow control and following the same routing and transmission delays as the virtual data flow channels. Thanks to these provisions, the measure is relevant for event notifications. According to particular features, the method that is the subject of the present invention, as succinctly set forth above, comprises, when two ports are connected, each connected to a sub-network switch, for the port, called a slave whose clock is provided by the other port, said master, a step of generating synchronization signal to the switch connected to said slave port, meanwhile, after reception by said slave port of a rising edge from said master port, during a duration equal to a measurement of the duration between a rising edge of a signal from the master port and a rising edge of a signal from said switch. The subnets are thus synchronous and maintain a constant phase difference. According to particular features, during the step of compensating for phase differences between source subnetworks, each port taken in order on a path followed by said signal representative of an event determines an additional duration to said compensation measure equal to the latency induced by the offset of the cycles undergone during the crossing of said port. The measurement is thus carried out for all the ports of the path followed by the event notifications.

According to particular features, during the phase difference compensation measurement step between source subnetworks, each destination subnet sends an offset measurement message to each source subnet and each source subnet. sends a response to the offset measurement message including a field for said measurement, to said destination subnet on said path, each port on said path performing: a step of receiving a response from the preceding port on said path; step of updating the response, by adding the additional duration measured by said port to the value already present in said field and - a step of sending said updated response to the next port on said path. The measurements are thus simultaneous and performed in the order of the ports encountered by an event notification. According to particular features, the phase difference compensation measurement step between source sub-networks comprises, for each port on said path, whether the synchronization signal of said port is not in phase with that of the switch to which said port is connected: - a step of determining if the response arrives from said switch, - if the response does not arrive from said switch: - if the offset between the cycles of the port and said switch is less than a period value of the cycle - interval of guard, the additional duration is equal to the value of a cycle period added to the value of the offset between the cycles of the port and the switch, - if the offset between the cycles of the port and said switch is greater than or equal to a value period of the guard interval cycle, the additional duration is equal to the value of the offset between the port and switch cycles - if the response comes from the switch: - if the offset between the port and switch cycles is greater than or equal to the guard interval value, the additional duration is equal to the value of two cycle periods minus the offset value between the port and switch cycles. switch and - if the offset between the port and switch cycles is less than the guard interval value, the additional duration is equal to the value of one cycle period minus the offset value between the port and switch cycles . According to particular features, the method which is the subject of the present invention, as succinctly set forth above, further comprises: a time offset measurement step between the beginnings of the cycles of the destination sub-networks and a step of adding said offset to the sum of said measured duration and the phase difference compensation for the source network hosting said source to form a delay implemented by each destination to delay the processing of the event. The present invention thus also applies to the context in which the destination cycles are also synchronized in constant but non-zero phase, additional compensations overcoming the discrepancies existing between the beginnings of the destination cycles. The determination, by each source, of a compensation of the offsets between destination cycles, seen from a source, provides a delay applied at the destination level, between the beginning of the treatment cycle of the event and the processing itself. This ensures a simultaneous processing of an event notification even if the destination cycles are not synchronized in zero phase.

According to particular features, the time offset measurement step between the beginnings of the cycles of the destination subnets is performed by each source subnet and, during the adding step, said offset measured by the source that emitted the signal representative of the event. According to particular characteristics, during the time offset measurement step between the beginnings of the cycles of the destination sub-networks, said measurement is determined with respect to the most important time offset with the cycle of said source.

Thus, preferentially, these compensations are aligned on the longest, which reduces the delay applied to all event notifications. According to particular features, during the time offset measurement step between the beginnings of the cycles of the destination subnets: each source subnet transmits an offset cumulative message to each destination, each port taken in order on a path followed by said shift accumulation message determines a duration additional to said measurement equal to the latency induced by the crossing of said port and - upon receipt of the shift accumulation message, each destination subnet returns a response to said source subnet, said response containing the cumulation thus determined. The cumulation measurement is thus performed for all the ports, in the order of the path followed by the event notifications.

According to a second aspect, the present invention aims at a device for synchronizing event processing on a network comprising at least two so-called source subnetworks each hosting at least one signal source representative of an event and at least two subnetworks said destinations each hosting at least one destination of said signal 3o representative of an event, said sub-networks having the same cycle duration, characterized in that it comprises: an event tracking means, during which each source measures a time elapsed between the beginning of a cycle of the source subnet hosting said source and the detection of an event common to several sources, - means for transmitting, at each destination, a signal representative of the source event and of said duration measured by each source, - a means for measuring phase difference compensation between the source sub-networks, by each the destination subnetwork; and a means for applying phase corrections adapted, at each reception, by a destination, of a signal representative of an event coming from a source, to apply a phase correction to delay processing said event of a duration equal to the sum of said measured duration for said source and phase difference compensation for the source network hosting said source. According to particular features, the device that is the subject of the present invention, as succinctly set forth above, further comprises: a means for measuring the time shift between the beginnings of the cycles of the destination subnetworks and a means for adding said offset to the sum of said measured duration and the phase difference compensation for the source network hosting said source to form a delay implemented by each destination to delay the processing of the event.

According to a third aspect, the present invention is directed to a computer program that can be loaded into a computer system, said program containing instructions for implementing the method that is the subject of the present invention, as briefly described above. According to a fourth aspect, the present invention aims at a support of information readable by a computer or a microprocessor, removable or not, retaining instructions of a computer program, characterized in that it allows the implementation of the method object of the present invention as succinctly set forth above. Since the advantages, aims and characteristics of this device, of this computer program and of this information carrier are similar to those of the method that is the subject of the present invention, as briefly described above, they are not recalled here. Other advantages, aims and features of the present invention will emerge from the description which follows, made for an explanatory and non-limiting purpose with reference to the appended drawings, in which: FIG. 1 represents, schematically, an application for which 2 is a schematic representation of a particular embodiment of the device that is the subject of the present invention, in a TDM switch; FIGS. 3a and 3b represent, in block diagram form, an interconnect type communication port; FIG. 4 represents, in the form of a logic diagram, an initialization of an offset management module illustrated in FIG. 3a; FIGS. 5a and 5b represent, in the form of logic diagrams, a measurement of the offset and generation of an offset SDPC signal; FIGS. 6a and 6b represent, in the form of logic diagrams, an operating algorithm of a memory 3b, FIGS. 7a and 7b represent, in the form of a logic diagram, an operating algorithm of a buffer memory illustrated in FIG. 3b; FIG. 8 represents compensations to be made in the case where the FIG. TDM cycles destinations are synchronized in zero phase, - Figures 9a and 9b represent, in the form of logic, an algorithm implemented on a network node hosting a destination, - Figure 10 represents, in the form of a logic diagram, a algorithm implemented on adapter nodes connected to nodes hosting sources; FIG. 11 represents, in the form of a logic diagram, steps of processing of accumulated shift messages by ports; FIG. , in the form of a logic diagram, steps of generation of event notification, - FIG. 13 represents, in the form of a logic diagram, stages of transmission of the event information, - FIG. represents, in the form of a logic diagram, an application of calculated compensations; - FIG. 15 represents, in the form of a logic diagram, in the case of destinations in constant phase, steps of compensation of the TDM offsets of destination nodes and - FIG. 16 represents, in the form of a logic diagram, in the case of constant phase destinations, steps of re-alignment and compensation of TDM offsets of source nodes. Figure 1 shows an example of use of the invention. A set of cameras 112 to 116 and microphones 107 to 111 capture a scene in which a subject 106 moves. Cameras 112 to 116, synchronized by a synchronization signal 117, are each connected to a PAN subarray 119, respectively. 123 (via not shown adapters nodes), themselves interconnected, via a set of PBN 118, in order to establish connections and to be able to transmit data between the terminals hosted by them. different subnets. Also interconnected to this set of PBN, two PAN 124 and 125 which are attached (via not shown adapter nodes) two screens 126 and 127. A set of sensors 100 to 104 can track the movements of a As a function of the status of these sensors 100 to 104, data from a subset of two camera-microphone pairs are routed and displayed on both screens 126 and 127. For example, when subject 106 located between the sensors 101 and 102, the data from the camera 113 is routed to the PAN 124 and displayed on the screen 126, and those from the camera 114 are routed to the PAN 125 and displayed on the screen 127. The passage of the subject 106 to the area between the sensors 102 and 103 generates an event intercepted by the adapter nodes connected to the cameras, in particular the cameras 113 and 114. Each adapter node connected to a camera issues a notification of which is transmitted, in combination with the control of the audio / video data flow. The adapter nodes linked to the screens 126 and 127 thus receive the event notifications generated by the adapter nodes respectively linked to the cameras 113 and 114. The simultaneous processing of these events causes the routing and the simultaneous display of the data coming from the cameras 114 and 115 to the screens 126 and 127 respectively. With reference to FIG. 2, we will now describe a communication device 200 that implements the present invention as implemented in the PBN interconnection equipment and the adapter nodes. This communication device 200 includes an internal bus 201 enabling the exchange of information between components referenced 202 to 207. A central unit 202 allows the execution of the instructions of a program stored in a non-programmable memory 204 or on a system nonvolatile storage 206, such as a hard disk. This program contains, in particular, instructions for executing all or part of the steps of the flowcharts described below. The nonvolatile memory 206 also contains the configuration data that can be updated by the user through an interface 205. A random access memory (RAM) 203 is the main memory of a central processing unit 202 which executes thereon. program instructions after their transfer from the non-programmable memory 204 or the non-volatile memory 206, after turning on the power. The communication device 200 has a local connectivity interface 209 adapted to connect audio / video equipment such as, for example, an HDMI interface (acronym for High Definition Multimedia Interface for, in French, High Definition Multimedia Interface).

The communication device 200 also has extended connectivity to a TDM network via an interface module 208 which formats the information to be exchanged between the internal bus (from or to a destination). application running on the CPU 202) or the local connectivity interface and the communication ports 210, 211 and 212 with the TDM network. The switching module 207 performs notably filtering and circuit establishment (routing) operations between the communication ports 210, 211 and 212 and the interface module 208. The switching module 207 is configurable by the central unit 202, via the internal bus 206. The interface module 208 is a communication port that allows the adaptation of traffic (for example by performing segmentation and re-assembly operations) with the applications, while the communication ports 210, 211 and 212 are limited to transmitting and receiving the information adequately on a medium. The number of communication ports as well as the number of interface modules 208 in the present description, respectively set at 3 and 1, are in no way limiting and are, on the contrary, sized according to the characteristics of the system. In the remainder of the description, the terms commutator or switch-type communication device are used interchangeably as described with reference to FIG. 2. The block diagram of FIG. 3a represents an example of communication port 210 which allows to make a serial interconnection link (also called Interconnect). An interconnection link is obtained by connecting, in point-to-point, two communication ports by means of a cable which carries signals 320 to 326. The data coming from the switch 207 is, initially, stored in a buffer memory 314 before being encapsulated by a function block 301, to form a data frame, and before being serialized and encoded by a function block 302. The data thus formatted are then transferred to a buffer memory ( LVDS (Low Voltage Differential Signaling) 305 providing high speed transmission via a Data_out signal 321.

The reception chain of this communication port 210 carries out the inverse successive operations, namely the reception of data through the Data_in signal 322 in the LVDS reception buffer buffer 305, an inverse operation called de-serialization and de-serialization. decoding, by a function block 304, and finally extraction of the data by a functional block 303. These data are then delivered, via a buffer memory 315, to the switch 207 according to the mechanisms as described with reference to FIG. 3b. Note that the CLK p / n 320 signal connected to the LVDS buffer 305 is the bit clock (data bit clock of data) of the data transmitted or received on the signals 321 and 322. The signal 320 is configurable input or output, depending on the user-configured clock distribution. This communication port has a signaling module 310 for exchanging control information with the remote or master port of the Interconnect. A functional block 311 applies a serialization before transmission on the CTL_OUT signal 323. In reception, the reverse de-serialization operation 312 is carried out on the CTL_IN signal 324, for processing by the signaling module 310. This signaling module 310 contributes in particular, the dissemination of information for the distribution of the clock in the network, and the verification that the connection between the two communication ports connected in point-to-point is still active. The communication port 210 allows, via the TDM shift management module 313, the delivery of the reference clock signal of the TDM cycle from the switch 207 as an output signal SDPC_OUT 326. It also allows delivering, to this same switch 207, the reference clock signal of the TDM cycle received from the remote switch (via the Interconnect) in the form of a signal SDPC_IN 325. As a function of the clock distribution configured by the user, only one of these two signals is taken as a reference. The block diagram of FIG. 3b shows in more detail the operation of the buffers 314 and 315 and the TDM shift management module 313. These elements allow the transmission of the data, despite the difference that may exist between the SDPC signals coming from the switch. 207 and those from the remote port, or master, of the Interconnect. In the case where the switch 207 provides the TDM clock to the Interconnect through the current port of the Interconnect, the signal SDPC_decaled 338 is false, which means that there is no offset between the SDPC signals of the switch. connected to the current port of the Interconnect and those of the Interconnect. The data is then exchanged between the encapsulation and de-encapsulation modules 301 and 303, on the one hand, and the switch 207, on the other hand, without passing through the buffers 314 and 315. Similarly, the signals SDPC_IN 325 and In_SDPC 337 are not modified by the TDM 313 offset management module. In cases where the TDM clock is supplied to the Interconnect by the remote or master port of the Interconnect, there is a discrepancy between the SDPC signal received by the port from the Interconnect and the signal received by the port from the switch (connected to the local or slave port of the Interconnect). The signal SDPC_décalés 338 is then true. The In_SDPC signal 336 to the switch is thus generated by a function block 333 according to the detailed algorithm with reference to FIG. 5b, on the basis of the SDPC signal IN 325 and the offset measured by a functional block 334. The signal SDPC_OUT 326 receives a copy of the signal IN_SDPC 325. In addition, the buffer 314 receives and stores a TDM frame from the switch 207 at each rising edge of the signal In_SDPC 336 corresponding to the TDM cycle of the switch 207. A 3o TDM frame consists of the aggregation of the virtual data channels to be transmitted from the switch to the port under consideration during a TDM cycle (and vice versa, that is, there is one TDM frame per communication direction). This same TDM frame is then delivered to the module 301 on the rising edge of the signal SDPC_IN 325 corresponding to the TDM cycle of the Interconnect. Similarly, the buffer memory 315 receives and stores a TDM frame from the Interconnect at each rising edge of the signal SDPC_IN 325 corresponding to the TDM cycle of the Interconnect. This same TDM frame is then delivered to the switch on the rising edge of the In_SDPC signal 336 corresponding to the TDM cycle of the switch. The buffers 314 and 315 operate according to the algorithm detailed with reference to FIGS. 6 and 7. The multiplexer 330 makes it possible to send to the encapsulation module 301 the data coming from either the switch 207 if the signal SDPC_decaled 338 is false, or buffer 314 otherwise.

The multiplexer 331 makes it possible to send to the switch 207 the data coming either from the decapsulation module 303 if the SDPC_decaled signal 338 is false or else from the buffer memory 315 else. The multiplexer 332 makes it possible to send to the switch 207 and the buffers 314 and 315 the signal SDPC from either the signal SDPC_IN 325 of the Interconnect if the signal SDPC_décalés 338 is false or the SDPC generator module 333 otherwise. The multiplexer 335 makes it possible to send to the signal SDPC_OUT 326 of the Interconnect the signal SDPC either from the signal SDPC_IN 325 of the Interconnect if the signal SDPC_décalés 338 is true or the switch 207 otherwise. When connecting a cable between two ports, the ports that it connects are initialized as illustrated with reference to FIG. 4. In a step 401, the port configuration is checked to determine whether the TDM clock of port is provided by the switch or by the remote port, or master, of the Interconnect.

In the first case, there is no difference between TDM cycles of the switch and the port, so there is nothing special to do at the port.

In the second case, the function block 334 measures the offset according to the algorithm detailed with reference to FIG. 5a, during a step 403. Then the generation of the signal SDPC to the switch starts during a step 404. following the algorithm detailed with reference to Figure 5b.

During a step 405, the switch is re-parameterized, through the configuration registers, for the switch to take the current port as a reference for its TDM cycle. FIG. 5a illustrates the method used to measure the gap existing between the TDM cycle of the Interconnect and that of the switch 207. During a step 500, a rising edge is expected on the signal SDPC_IN 325 of the Interconnect. This rising edge triggers the start of a counter during a step 501. Then, during a step 502, the next rising edge is expected on the Out_SDPC signal 337 from the switch. This rising edge causes, during a step 503, the stopping of the counter, the value of which then represents the value of the offset. During a step 504, it is determined whether this value is greater than or equal to the period of the SDPC signal. If yes, we are in the case where the two signals SDPC are very little offset (the offset is less than the period of the clock used for the counter). During a step 505, it is then considered that the offset value is zero. If the result of step 504 is negative or following step 505, the measured offset value is stored in memory, in a step 506, and a ready signal 339 is enabled, in the course of time. a step 507, to inform the SDPC signal generator 333 that it can start. FIG. 5b illustrates the method used to generate the In_SDPC signal 336 shifted to the switch 207. In a first step, the validation of the ready signal 339 is awaited during a step 510, then the next rising edge is waited on. the signal SDPC_IN 325 of the Interconnect, during a step 511. Once this rising edge received, it is expected, during a step 512 a delay equal to the measured offset value (for example using a counter having the same clock as that used to measure the offset). Once this time has passed, during a step 513, a rising edge is generated on the In_SDPC signal 336, before resuming the next rising edge on the signal SDPC_IN 325 of the Interconnect to start the cycle again. step 511.

FIG. 6a illustrates the process governing the writing in the buffer memory 315. At initialization, during a step 600, an index counter N is initialized to 0. The next rising edge is then waited on the signal SDPC_IN 325 of the Interconnect, during a step 601. This rising edge triggers the incrementation of the index N, during a step 602, and the beginning of receiving and storing a TDM frame, in a step 603. Then returning to step 601. FIG. 6b illustrates steps related to reading the data stored in the buffer memory 315. We start by waiting the next rising edge on the signal In_SDPC 336 of the switch 207, during a step 610. In the implementation described and shown, a variation of the period of the TDM cycles of a microsecond is tolerated. When transmitting a TDM frame, the entire period of the cycle is not available to transmit the data. A guard interval is defined at the end of each cycle to ensure that all data is correctly transmitted despite variations in the TDM period. During a step 611, it is determined whether the measured offset is greater than or equal to the TDM period minus the guard interval. If the offset measured between the TDM cycles is less than the guard interval TDM period, all data in a frame may not have been stored in the buffer at the beginning of the TDM cycle of the switch. We then wait for the next cycle. During a step 612, it is determined if N is strictly greater than 1. If no, we return to step 610. If yes, we transmit the data received during the previous cycle, N-1 index of Interconnect, in a step 613. 3o If the measured offset between the TDM cycles is greater than or equal to TDM period-guard interval, all the data of a frame was stored in the buffer at the time of the start of the TDM cycle of the switch. They are transmitted to the switch during a step 614. FIG. 7a illustrates steps related to the writing in the buffer memory 314. At the initialization, during a step 700, an index counter N is initialized to 0. The next rising edge is then waited on the In_SDPC signal 336 of the switch 207 during a step 701. This rising edge triggers the incrementation of the index counter N during a step 702 and the start of reception. and storing a TDM frame during a step 703. Next, returning to step 701.

FIG. 7b illustrates steps related to the reading of the data stored in the buffer memory 314. It begins by waiting for the next rising edge on the signal SDPC_IN 325 of the Interconnect, during a step 710. During a step 711, it is determined whether the offset is strictly less than the guard interval. Indeed, in the case of this buffer, the data comes from the switch and is transmitted to the Interconnect. To ensure that all data transmitted during a switch cycle has been correctly stored in the buffer, the offset between cycles must be less than the guard interval. If the result of step 711 is positive, the data received during the current cycle of the switch is transmitted to the Interconnect, in a step 714. Otherwise, the data corresponding to the previous cycle is transmitted in the course of step 714. Step 713. Figure 8 is now described which relates to compensations to be made in the case where the destination TDM cycles are synchronized in zero phase. When a set of audio / video data streams is transmitted by a set of sources to a set of destinations, the different paths taken by these streams generate time differences of 3o transport (latency differences) and therefore presentation times. , for data transmitted at the same time, different on the destinations. In the case where all the PANs are synchronized in zero phase, these latency differences are expressed as a whole number of TDM cycles. The use of an appropriate topology, with the same number of PBNs and the same latencies of Interconnect on all paths, solves this simple problem. In the present case, the existing offsets between the TDM cycles of the different PANs and the mechanisms they imply induce additional latency, specific to each path. For a particular path, this additional latency is the sum of the cycle offsets experienced during the crossing of the different port / switch interfaces encountered on the path, for which there is an offset between the SDPC signals of the switch and the port. It can be decomposed in the form a * TDM + b period, in which formula: - a is an integer representing the number of TDM whole cycles of latency induced by the previously mentioned treatments, and - b represents the latency due to the difference between TDM cycles of the source and those of the destination. The value of b is therefore less than the period of a TDM cycle. To ensure simultaneous presentation of the event notifications to the different applications, a different additional compensation for each stream, more accurate than the TDM period, is calculated and applied at the destination adapter nodes to compensate for the differences between the additional latencies of the different paths. As a first step, suppose that the TDM cycles of the subnetworks hosting the destinations (TDM destinations cycles) are synchronized in the null phase, but not those of the subnetworks hosting the sources. Before processing a received event notification, it is necessary to wait for a compound delay: - a compensation of the offsets between the TDM cycles of the sources, and - a time interval separating the start of the TDM cycle from the source and the detection of the event.

Figure 8 shows an illustration of this compensation. The time axis 800 corresponds to the events relating to the PANs hosting the destinations. Note that in Figure 8, a single axis is sufficient because, at first, TDM cycles destinations are synchronous. The time axes 801, 802, and 803 correspond to the events relating to three PANs hosting sources, called PAN 1, PAN 2 and PAN 3. Event 809 corresponds to the start of the virtual start cycle of source application data in the event that all TDM cycles were in phase. Event 810 corresponds to the start of the actual start cycle (i.e., taking into account the offset between TDM cycles) of the source data connected to PAN 1. Event 811 corresponds to the start of the actual data start cycle of the source connected to PAN 2. Event 812 corresponds to the start of the actual data start cycle of the source connected to PAN 3. The different corresponding additional latency values are respectively represented by the durations 804, 805 and 806. The principle of calculating the offset compensations of the source TDM cycles consists in measuring, by the method described hereinafter, in a first step, the latencies induced by TDM cycle offsets between sources and destinations. These measurements are made by each destination, for each source. The TDM destinations cycles being synchronous, the results obtained are identical. This makes it possible to select the source for which the cumulative offset of TDM cycles on the path (also called cumulative path offset thereafter) is the largest, as a reference source. Event notifications generated by this source do not need to be compensated. On the other hand, those from the other sources will have to be compensated to adjust their processing times to that of the event notifications generated by the reference source.

This compensation is calculated in a second step, as explained with reference to FIG. 9a, and corresponds to the difference between the computed path offset calculated for the event notification from the reference source and that calculated for the notification of event from the source concerned. In Figure 8, this gives the duration 807 for the event notification from the source hosted by the PAN 2, and the duration 808 for the event notification from the source hosted by the PAN 3.

FIG. 9a illustrates steps of the process implemented by the adapter nodes hosting the destinations (also called destination nodes in the remainder of the description). During a step 900, the destination node selects a source. During a step 901, the destination node constructs an offset measurement message for the adapter node hosting a selected source and sends this message. The steps 900 and 901 are preferably performed simultaneously (or with a small time difference, for example of the order of a few TDM cycles) for all the sources connected to the destination node. During a step 902, the responses to these messages are intercepted by each port crossed on their return path (thus in the direction that will follow the event notification, from the source to the destination), and each port adds the delay, as a consequence of the TDM cycle offsets, experienced by the data during the crossing of this port (that is to say, as a function of the offset of the TDM cycles, plus possibly the taking into account of the guard interval) , to the cumulative value already contained in the answer. The responses, one per node hosting a source, are received in step 903. Once the accumulated path offset values for each source are extracted from these responses, the source corresponding to the highest cumulative path offset (also called offset_ref in the following) is elected reference source during a step 904. For each source, selected during a step 905, the compensation to be applied is then calculated, during a step 906, as follows : offset_of_shift_src_i = shift_ref ù shift_src_i.

In this formula, offset_src_i is the accumulated path offset value calculated for the current i source (this value is zero for the reference source). The compensation_de_décalage_src_i value is then stored in a compensation table 910 illustrated in FIG. 9b, during a step 907. Each entry in this table 910 corresponds to a data stream to which an event notification, identified by the field 911 containing the list of virtual channels (in English VC for Virtual chanel) by which the event notifications can arrive. Each entry of this table also includes an offset compensation field 912, which receives the value calculated in step 906. FIG. 10 represents steps of a process triggered by the reception of an offset measurement message by a node to which a source is connected, during a step 1000. A response message to the offset measurement message is constructed and returned to the destination during a step 1001. This response includes in particular a cumulate field of latency, which is then filled by the different ports traversed, in step 902. Figure 11 shows steps taken by the ports when they intercept a response to an offset measurement message, in step 902. These messages are detected according to the virtual channel on which they circulate and according to their header. When one of these messages is intercepted, during a step 1100, the port determines, during a step 1101, if the signal SDPC_décalés 338 is true. If the signal SDPC_decaled 338 is false (ie the signal SDPC of the port is in phase with that of the switch to which it is connected) there is no particular treatment to be done. The message is therefore transmitted to its destination during a step 1102. In the opposite case, the offset accumulated value contained by the message is extracted, during a step 1103. During a step 1104, it is determined whether the message arrives from the switch. If the result of step 1104 is negative, the message arrives from the remote or master port of the Interconnect in the direction of the switch. During a step 1105, it is determined whether the offset between the TDM cycles of the port and the switch is greater than or equal to the value TDM period - guard interval. If the result of step 1105 is negative, in a step 1106, the value extracted from the message is added the value of a TDM period and the value of the offset between TDM cycles of the port and the switch. Note that in FIGS. 6a and 6b, a cycle plus the offset is expected before outputting the data from the buffer memory. Then, the latency cumulation value thus calculated is reinserted in the message, during a step 1108 before the latter is transmitted to its destination, during step 1102.

If the result of step 1105 is positive, ie if the offset between the TDM cycles of the port and the switch is greater than or equal to the value TDM period - guard interval, the value extracted from the message is added, in a step 1109, the value of the offset between the TDM cycles of the port and the switch. Note that in Figures 6a and 6b, the offset is expected before outputting the data from the buffer. Then the cumulated offset value thus calculated is reinserted in the message during step 1108 before the latter is transmitted to its destination, in step 1102. If the result of step 1104 is positive , ie if the message arrives from the switch towards the remote port, or master, of the Interconnect, during a step 1110, it is determined whether the offset between the TDM cycles of the port and the switch is less than the value of the guard interval. If the result of step 1110 is negative, the value extracted from the message is added, in a step 1111, the value of two TDM periods minus the value of the offset between TDM cycles of the port and the switch. Note that in FIGS. 7a and 7b, a cycle plus the complement of the offset is expected before outputting the data from the buffer memory, the offset being always measured between a rising edge of the signal SDPC of the port and the next rising edge of the SDPC signal from the switch. Then the cumulative offset value thus computed is re-inserted into the message during step 1108 before the latter is transmitted to its destination during step 1102.

If the result of step 1110 is positive, i.e. if the offset between TDM cycles of the port and the switch is less than the value of the guard interval, the value retrieved from the message is added during a step 1112, the value of a TDM period minus the value of the offset between TDM cycles of the port and the switch. Note that, in FIGS. 7a and 7b, the complement of the offset is awaited before outputting the data from the buffer memory, the offset being always measured between a rising edge of the signal SDPC of the port and the next rising edge of the signal SDPC of the switch. Then the accumulated offset value thus calculated is reinserted in the message, in the course of the step 1108, before the latter is transmitted to its destination, during the step 1102. FIG. 12 represents the processing done at the level of the messages. source adapter nodes, to generate an event notification. When an event is picked up by a device (audio / video source for example), it is marked relative to the beginning of the current TDM cycle at the time of detection. The value of a counter Cpt, reset at each start of the TDM cycle, represents the time between the start of the TDM cycle and the event. This counter is incremented on each rising edge of a clock (called counter clock) of very short period with respect to the period of the TDM cycle, for example a counter clock of period 30 ns, for a TDM cycle of period 125 ps. The shorter the period of this counter clock, the better the tracking accuracy of the event. During the initialization of the adapter node, during a step 1200, the beginning of the first TDM cycle is waited for to initialize the value Cpt of the counter at 0, during a step 1202. Then one waits for one of the following detections during a step 1203. If a rising edge is detected on the counter clock during a step 1204, the counter value Cpt is incremented during a step 1205, then it is returned to the counter. If a new start of TDM cycle is detected during a step 1201 by the rising edge of the TDM clock, the counter value Cpt is reset to zero during a step 1202, then returns to step 1203.

If an event is detected during a step 1206, the variable t takes the current value Cpt of the counter during a step 1207, and an event notification composed of the value t as well as the type of event is inserted in one or more so-called virtual control channels associated with the audio / video data stream during a step 1208. Then, we return to step 1203. FIG. 13 represents the way in which the TDM cycle is organized for the transmission of the event notification, on a time axis 1300. All the available bandwidth is shared in synchronous virtual channels. The samples of channels, of identical size, are interlaced in time and thus form a TDM sequence, also called TDM cycle. The bandwidth thus allocated to each virtual channel is therefore constant and characterized by the frequency of appearance of the TDM cycle and the size of the samples.

For example, for a TDK cycle frequency of 8 kHz, a period of 125 ps, and a sample size of 48 bits, each virtual channel offers a bandwidth of 384 Kbps (kilobits per second). Thus, a TDM cycle comprising 1024 virtual channels offers a global bandwidth of 384 Mbps (megabits per second).

The signals SDPC, 1302 and 1303, mark the appearance of the first symbol representative of the first sample of the TDM cycle. The period of this signal is equal to the period of the TDM cycle. Sets of virtual channels 1304 and 1305 respectively represent the virtual channels reserved for the transmission of video and audio data of an audio / video stream. The positioning of these virtual channels and their number depends on the configuration of the network and the allocated bandwidth. A set of virtual channels 1306 represents the control data associated with the data stream formed by the sets of virtual channels 1304 and 1305. Among these control data is the event notification, for example at the beginning of the control data. It is composed of: - a flag field 1307 which is equal to 1 If an event notification is present, and 0 otherwise; an event type field 1308 containing the type of the notified event, and a field value t 1309 containing the value t determined as set out with reference to FIG. 12. The other control values are found subsequently in FIG. Field 1310. Fields 1307 to 1310 are present for each TDM cycle. The value of the flag field 1307 indicates whether the event type and value t fields are to be taken into account. If multiple audio streams are transmitted in the same TDM cycle, each one has its own set of control channels. Figure 14 shows the processing done upon receipt of an event notification by a destination adapter node. In the case where multiple streams are transmitted in the TDM cycle, this processing is done for each event notification received independently of each other. During a step 1400, it is determined whether the flag field 1307 corresponding to a stream being received is 1. Otherwise, return to step 1400. If yes, the value t is extracted from the field 1308, then it is added to the compensation value (corresponding to the flow) contained in the table described in FIG. 9b. This addition gives the value t ', during a step 1401. It then waits for the start of the next cycle TDM, during a step 1402, then waiting for a time equal to the duration of t' clock cycles counter during a step 1403, as illustrated in FIG. 12, before processing the event, during a step 1404. The nature of the processing depends on the type of event and the application scenario. As explained with reference to FIG. 8, the means described until now correspond to the case where the TDM cycles of the subnetworks hosting the destinations are synchronized in the null phase, but not those of the sub-networks containing the sources.

In the case where the destination TDM cycles are also synchronized in constant but non-zero phases, additional compensations compensate for the discrepancies existing between the beginning of the destination TDM cycles. A first processing consists in determining a compensation of offsets between TDM cycles destinations, this determination being made by each source. This first compensation, as described above, consists of a delay, applied at the destination level, between the start of the TDM cycle of processing the event and the processing itself. Each source therefore determines a first compensation value for each destination. Call Compl_SRCi_DESTk this first compensation determined by the source i for the destination k. It is applied by destination k to events from source i. Consequently, when these first compensations are applied, an event notification generated by a given source is processed at the same time regardless of its destination. The calculation of this compensation value is detailed with reference to FIG. 15. This calculation is executed at each source adapter node, as illustrated by step 1500. During a step 1501, it is determined, for each destination , the offset between the TDM cycles of the source PAN and those of the destination PAN. This determination is made on the same principle as that described with reference to FIGS. 9 to 11: the source adapter node sends a shift accumulation message to the destination. Each port crossed intercepts the message and processes it in accordance with the process described with reference to FIG. 11 (with the difference that here the processing is applied to the shift accumulation message itself, and not to the response to this message. ). On receipt of this message, the destination node returns a response to the source adapter node, containing the accumulation thus determined. Once all the responses have been received, the destination adapter node having the largest TDM offset with the source adapter node is elected as the reference destination, in a step 1502. For each destination k, as illustrated by a step 1503, the value Compl_SRCi_DESTk is then calculated by subtracting the cumulative value obtained for the destination k from the cumulative value obtained for the reference destination, during a step 1504, before being transmitted to the destination, during a step 1505, through a message. Figure 16 describes the processing applied at the destination adapter nodes. This second treatment consists of a re-alignment of the previous corrections to the one that is the longest. Indeed, after applying Compl_SRCi_DESTk compensation, an event notification generated by a given source it will be processed at the same time dl regardless of its destination, and an event notification generated by a given source i2 will be processed at the same time d2 whatever its destination. The processing illustrated in FIG. 16 aims at aligning the instants d1 and d2. These moments being common to all destinations, the realignment can be done on a single destination and then distributed to others. The way this unique destination is chosen does not affect the process, so the choice method used is free (choice of the user, default setting at the time of initialization, etc ....). Figure 16 depicts the processing applied at this destination adapter node k. After receiving all the Compl_SRCi_DESTk values (one per source), as illustrated by steps 1600 and 1601, the destination adapter node calculates the maximum value of Compl_SRCj_DESTk corresponding to all the sources j, determined during a step 1602. Then this node calculates a second compensation Comp2_SRCi for each source i, as illustrated by a step 1603, subtracting the value Compl_SRCi_DESTk to the maximum value of the Compl_SRCj_DESTk, during a step 1604. Consequently, the application of these seconds offsets, if the source TDM cycles were in phase, event notification processing would be synchronous. Since the source TDM cycles are not in phase, a final point consists in determining a compensation of the offsets between source TDM cycles. This determination is made in a step 1605, using the same means as those described with reference to Figures 9 to 11, with the difference that, here, it is performed only by the single adapter node k.

Finally, these compensations are transmitted to the other adapter nodes, to apply them, during a step 1606. These compensations are expressed in numbers of counter clock cycles. Each PBN node, or adapter, integrates one of these counters whose cycle time is conventionally derived from the frequency of a quartz. The quartz located on the different nodes have the same frequency. The compensation application is done in a manner similar to that described with reference to FIG. 14. After receiving an event notification and extracting the value t, it is added to it the compensation values Compl_SRCi_DRSTk (corresponding to the flow related to event notification), Comp2_SRCi and Comp3_SRCi. The start of the next TDM cycle is then waited for in step 1402, then a delay equal to the duration of the counter clock cycles is expected, as discussed with reference to FIG. 12, before processing. event during step 1404. The nature of the processing depends on the type of event and the application scenario.

Claims (1)

CLAIMS1 - A method of synchronization of event processing on a network (118) comprising at least two subnetworks (119 to 123) said sources each hosting at least one signal source representative of an event and at least two subnetworks (124, 125) said destinations each hosting at least one destination of said signal representative of an event, said sub-networks having the same cycle duration, characterized in that it comprises: a step (1200 to 1207) of identification of event, during which each source measures a time elapsed between the beginning of a cycle of the source subnet hosting said source and the detection of an event common to several sources, - a transmission step (1208), at each destination, a signal representative of the event and of said duration measured by each source, - a step (500 to 506) for compensating for phase differences between the sub-elements. source networks, by each destination subnet and - at each receipt, by a destination, a signal representative of an event from a source, a step (1403) of phase correction application, during wherein said destination delays the processing (1404) of said event by a duration equal to the sum of - said time measured by said source and - the phase difference compensation for the source network hosting said source. 2 - Process according to claim 1, characterized in that the step of compensating for phase differences between subnetworks hosting sources comprises, for each sub-network destination: a step of determining the phase difference between the fronts clock cycle amounts of said destination subnet and the rising edges of each source subnet; - a step of selecting a so-called reference source subnet; and - a step of determining the offset between rising edges. between the reference source subnet and each other source subnet. 3. Process according to claim 1, wherein during the step of transmitting said measured duration, each source performs an insertion of information relating to the event into a virtual channel of Dedicated data flow control, data flow control and the same routing and transmission delays as the virtual data flow channels. 4 - Process according to any one of claims 1 to 3, characterized in that it comprises, when connecting two ports, each connected to a subnetwork switch, for the port, said slave whose clock is provided by the other port, said master, a step of generating synchronization signal to the switch connected to said slave port, meanwhile, after reception by said slave port of a rising edge from said master port, during a duration equal to a measurement of the duration between a rising edge of a signal from the master port and a rising edge of a signal from said switch. 5. Process according to any one of claims 1 to 4, characterized in that, during the phase difference compensation measuring step between source sub-networks, each port taken in order on a path. followed by said signal representative of an event determines a duration additional to said compensation measure equal to the latency induced by the offset of the cycles incurred during the crossing of said port. A method according to claim 5, characterized in that, during the step of compensating for phase differences between source subnets, each destination subnet sends an offset measurement message to each sub-network. source network and each source subnet 3o sends a response to the offset measurement message comprising a field for said measurement, to said destination subnet on said path, each port on said path performing: a step of receiving an answer of the preceding port on said path, - a step of updating the response, by adding the additional duration measured by said port to the value already present in said field and - a step of sending said updated response to the next port on said path. 7. The method according to claim 6, wherein the step of compensating for phase differences between source subnetworks comprises, for each port on said path, whether the synchronization signal of said port is not in effect. phase with that of the switch to which said port is connected: - a step of determining if the response arrives from said switch, - if the response does not arrive from said switch: - if the offset between the cycles of the port and said switch is less than one value cycle period - guard interval, the additional duration is equal to the value of a cycle period added to the value of the offset between the port and switch cycles, - if the offset between the cycles of the port and said switch is greater than or equal to a cycle period value - guard interval, the additional duration equals the offset value between the port and switch cycles - if the response from the switch: - if the offset between the port and switch cycles is greater than or equal to the guard interval value, the additional duration is equal to the value of two cycle periods minus the offset value between the cycles of the switch. port and switch and - if the offset between the port and switch cycles is less than the guard interval value, the additional duration is equal to the value of one cycle period minus the offset value between the port cycles The method according to any one of claims 1 to 7, characterized in that it further comprises: - a time offset measurement step between the beginnings of the cycles of the sub-networks destinations and - a step of adding said offset to the sum of said measured time and the phase difference compensation for the source network hosting said source to form a delay implemented by each destination to delay processing of the event. 9. The method as claimed in claim 8, characterized in that the step of measuring the time shift between the beginnings of the cycles of the destination subnetworks is performed by each source subnet and, during the adding step, said offset measured by the source having emitted the signal representative of the event is added. 10. Process according to claim 9, characterized in that, during the time offset measurement step between the beginnings of the cycles of the destination sub-networks, said measurement is determined with respect to the most important time offset with the cycle. of said source. 11. The method as claimed in claim 9, wherein, during the step of measuring the time shift between the beginnings of the cycles of the destination subnets: each source subnet sends a message cumulative offset to each destination, - each port taken in order on a path followed by said shift accumulate message determines a duration additional to said measurement equal to the latency induced by the crossing of said port and - upon receipt of the message of shift accumulation, each destination subnet returns a response to said source subnet, said response containing the thus determined accumulation. 12 - Device for synchronizing event processing on a network comprising at least two so-called source subnetworks each hosting at least one signal source representative of an event and at least two subnetworks said destinations each hosting at least one destination said signal representative of an event, said sub-networks having the same cycle duration, characterized in that it comprises: - an event tracking means, during which each source measures a time elapsed between the beginning of a cycle of the source subnet hosting said source and the detection of an event common to several sources; means for transmitting, at each destination, a signal representative of the event and of said duration measured by each source; a phase difference compensation measuring means between the source subnetworks, by each destination subnetwork and a means of application of phase corrections adapted, at each reception, by a destination, of a signal representative of an event coming from a source, to apply a phase correction to delay the processing of said event of a duration equal to the sum - said measured time for said source and - phase difference compensation for the source network hosting said source. 13 û Device according to claim 12, characterized in that it further comprises: a time offset measurement means between the beginning of the cycles of the destination sub-networks and a means of adding said offset to the sum of said measured duration and phase difference compensation for the source network hosting said source to form a delay implemented by each destination to delay the processing of the event. 14 - computer program loadable in a computer system, said program containing instructions for carrying out the method according to any one of claims 1 to 11. 15 - Support for information readable by a computer or a microprocessor, removable or not, retaining instructions of a computer program, characterized in that it allows the implementation of the method according to any one of claims 1 to 11.