FR2945665A1 - PROCESS FOR COATING A SEMICONDUCTOR SUBSTRATE BY ELECTRODEPOSITION - Google Patents

Abstract

The invention relates to a method of treating a semiconductor substrate comprising the steps of: etching (S1) to form at least one pattern forming a hollow, in particular of the "via via" type, with respect to the surface of said substrate semiconductor; depositing (S2) an insulating dielectric layer on said surface of said semiconductor substrate; depositing (S3) a phosphorus in-situ doped silicon layer on said insulating dielectric layer; coating (S4) of said phosphorus in-situ doped silicon layer with a layer of metallic copper, the coating step (S4) comprising electroplating using an electroplating solution adapted for growth of the metallic copper on silicon doped in situ with phosphorus.

Description

Method of coating a semiconductor substrate by electrodeposition

FIELD OF THE INVENTION The present invention generally relates to an electrocoating composition for coating a surface of a substrate with copper, especially a surface made of an electrically resistive material.

STATE OF THE ART The invention is essentially applicable in the field of microelectronics for the metallization of through vias (called through silicon vias or via wafer vias or through wafer interconnect in English) keystone of the integration of electronic chips (called chip or die in English) in three dimensions (3D) or vertical integration. Today's electronic systems consist, for the most part, of several integrated circuits, or components, and each integrated circuit performs one or more functions. For example, a computer has at least one microprocessor and several memory circuits. Each integrated circuit usually corresponds to an electronic chip in its own package (called package in English). The integrated circuits are brazed or plugged on, for example, a printed circuit board (referred to as printed circuit board or PCB in English) which provides the connection between the integrated circuits. Since several generations of integrated circuits, the permanent need to increase the density of functionality led to the design of systems according to the concept of system on chip (called system on chip in English). All components and circuit blocks necessary for the implementation of all the system functions are then made on the same chip, without using the support of a printed circuit. In practice, however, it is very difficult to obtain a high-performance system-on-chip because the processes for manufacturing logic and memory circuits, for example, differ very substantially. The system-on-a-chip approach therefore leads to compromise on the performance of the different functions performed on the same chip. In addition, the size of such chips and their manufacturing efficiency reach the limits of their economic feasibility.

Another approach is to manufacture in the same housing a module providing the interconnection of several integrated circuits, which can then come from the same semiconductor substrate or different substrates. The thus obtained housing or multi-chip module (called multi chip module or MCM in English) is thus in the form of a single component. There are different technologies of MCM substrate e.g. laminated, ceramic. In all cases, the MCM approach provides a higher interconnection density and therefore a better performance than a conventional PCB approach. Nevertheless, it does not differ fundamentally. In addition to the size and weight of the housing, the performance of an MCM is limited by the parasitic elements associated with the length of the connections of the substrate and the connection son (called wire bonding in English) connecting the substrate or the chips to the pins (called pins in English) of the case.

Thanks to the implementation of a three-dimensional integration (3D) or vertical integration, the chips are superimposed (called stacked in English) and interconnected by vertical interconnections. The stack obtained has several layers or layers of active components or chips, it constitutes a three-dimensional integrated circuit (called 3D integrated circuit or 3D IC in English).

The benefits of 3D integration include: (1) improved performance eg reduced delay and power dissipation, increased system uptime associated with faster communication between functional blocks , increase of the bandwidth of each functional block, increase of the immunity to the noise, (2) of the improvement of the costs eg increase of the density of integration, better production efficiency thanks to the use of the generation of the most appropriate electronic chip for each functional block, improved reliability, and (3) the possibility of producing highly integrated systems by stacking heterogeneous technologies (or co-integration) ie involving different materials and / or different functional components. Today 3D integration is proving to be an indispensable alternative to conventional approaches, which reach their limits in terms of performance, diversification of features and cost of implementation. After stacking, for example by gluing, the chips can be individually connected to the housing pins by connection wires. Nevertheless, the interconnection of the chips with one another with a high interconnection density can only be obtained by using through vias. The fundamentals and advantages of 3D integration have been described for example in: AW Topol, DC The Tulip, L. Shi, DJ Frank, K. Bernstein, SE Steen, A. Kumar, Singco GU, AM Young, KW Guarini and Mr. Leong, "Three-dimensional Integrated Circuits" IBM Journal Res. & Dev., Vol. 50, No. 4/5, July / September 2006, pages 491-506. The thinning of the silicon wafers, the alignment between the layers, the bonding of the layers, the etching and the metallization of the through vias within each layer are the necessary elementary technologies. to the realization of integrated circuits in three dimensions. The three-dimensional circuits can be made by thinning the silicon wafer prior to fabrication of through vias (e.g., U.S. Patent Nos. 7,060,624; 7,148,565). Etching and metallization of the vias can also be done prior to thinning the silicon wafer (e.g., U.S. Patent No. 7,060,624; 7,101,792). In this case the vias are etched in the silicon, then metallized to the desired depth before thinning the silicon wafer. During their metallization the vias are closed or blind (called blind vias in English). The good electrical conductivity of copper and its high resistance to the phenomenon of electromigration, that is to say the low migration of copper atoms under the effect of the electrical current density may be a major cause of failure, make it in particular a material of choice for the metallization of through vias. The through vias are generally made in a manner similar to the Damascene process (used in the field of microelectronics for the manufacture of interconnection elements of integrated circuits) according to a succession of steps comprising: - the engraving of the vias in or through the silicon wafer; depositing an insulating dielectric layer (generally consisting of oxide or silicon nitride, for example); depositing a barrier or liner layer (generally consisting of tantalum (Ta), titanium (Ti), tantalum nitride (TaN), titanium nitride (TiN), tungsten titanate (TiW), nitride or tungsten carbide (WON) or combinations of these materials, for example) to prevent migration of copper; depositing a thin layer of metallic copper, called the seed layer; filling the vias by copper plating; and elimination of excess copper by chemical mechanical polishing. This integration scheme for the manufacture of through vias has a major weak point. Indeed, the anisotropic etching of silicon (e.g. U.S. Patent No. 5,501,893) most often leads to a barrel profile (referred to as bowing in English), rough, grooved or streaked (referred to as scalloping in English). Thus the flanks of the vias may be partially uncoated or covered with an insufficient thickness of barrier layer and seed layer, thus causing a subsequent imperfect filling with defects in material (called voids in English). In addition, the barrier and germination layers formed on the sidewalls of the patterns are inherently different from those deposited on the flat surface of the substrate. These disadvantages make very difficult the use of physical or chemical deposition processes from a vapor phase (PVD or Physical Vapor Deposition and CVD or Chemical Vapor Deposition in English, respectively) which can be used for the deposition of the barrier layer and the seed layer. Under these conditions, the present invention aims to solve the new technical problem consisting in the development of a new integration scheme used for the manufacture of through vias, to overcome the technical difficulties arising from etching anisotropic silicon.

SUMMARY OF THE INVENTION To this end, there is provided a method of treating a semiconductor substrate comprising the steps of: etching (S1) to form at least one pattern forming a hollow, particularly of the through-via type, relative to on the surface of said semiconductor substrate; depositing (S2) an insulating dielectric layer on said surface of said semiconductor substrate; depositing (S3) a phosphorus in-situ doped silicon layer on said insulating dielectric layer; coating (S4) of said phosphorus in-situ doped silicon layer with a layer of metallic copper, the coating step (S4) comprising electroplating using an electroplating solution adapted for growth of the metallic copper on silicon doped in situ with phosphorus.

Such a treatment method has the advantage of forming semiconductor substrates having a flat profile in which defects related to etching are not present at the copper layer. Indeed, the deposition of silicon doped in-situ with phosphorus has the advantage of not being influenced by the defects on the surface of the substrate so that the surface of the resistive layer formed by silicon doped in-situ with phosphorus is flat, or at least without substantial defect. The subsequent electroplating step which is adapted to allow deposition of metallic copper on such a phosphor-doped in-situ silicon layer makes it possible to form a stack without apparent defects.

Preferred but non-limiting variants of this treatment method are the following: the coating step (S4) comprises the following successive substeps: contacting (S4-O) of said doped silicon layer in situ to the phosphorus with the electroplating solution, and o polarization (S4-2) of said phosphorus in-situ doped silicon layer to an electrical potential allowing the electroplating of metallic copper on said phosphorus-in-situ doped silicon layer . the coating step (S4) furthermore comprises a substep of maintaining (S4-1), for a determined duration, of said phosphorus in-situ doped silicon layer in contact with the electrodeposition solution without polarization said sustain substep (S4-1) being performed between the substep of contacting (S4-0) and the substep of polarization (S4-2). the coating step (S4) further comprises a hot exit sub-step (S4-3) during which said phosphorus in-situ doped silicon layer is separated from the electroplating solution while it is still under electrical polarization, said hot output substep (S4-3) being performed after the polarization substep (S4-2). the coating step (S4) comprises a preliminary pre-wetting step comprising contacting the semiconductor substrate with a liquid solution. the contacting of the semiconductor substrate with the liquid solution is carried out by a physicochemical technique comprising the use of jets to send the liquid solution at high pressure, and / or the use of ultrasound, and / or the use of vacuum. the method further comprises an annealing step (S5) carried out after the coating step (S4), said annealing (S5) being carried out at a temperature chosen to allow diffusion of the copper in the in-situ doped silicon layer; phosphorus, so as to form a copper silicide. the electroplating solution comprises, in solution in a solvent: copper ions in a concentration of between 14 and 120 mM, and o ethylenediamine, where the molar ratio between ethylenediamine and copper is between 1.80 and 2.03, and the pH of said composition being between 6.6 and 7.5.35. According to another aspect, there is provided a multilayer stack characterized in that it comprises: a semiconductor substrate with a surface having a pattern forming at least one trough, in particular through-through type, - an insulating dielectric layer covering said surface, - a phosphor-in-situ doped silicon layer covering said insulating dielectric layer, and - a metallic copper layer covering said silicon layer doped in-situ with phosphorus.

According to a preferred embodiment, the copper layer of such a stack fills the at least one hollow and comprises a flat outer surface.

DESCRIPTION OF THE FIGURES Other features and advantages of the invention will become apparent from the description which follows, which is purely illustrative and not limiting and should be read with reference to the accompanying drawings, in which: FIG. 1 is a schematic diagram illustrating the steps of an embodiment of the treatment method according to the invention; FIG. 2 is a schematic diagram illustrating the substeps of one embodiment of the coating step of the treatment method according to the invention; FIG. 3 represents the galvano-pulsed protocol used for the growth of the seed layer; FIG. 4 represents a cross-sectional view with a scanning microscope of a 50 μm × 200 μm size via covered with a seed layer as deposited in example 4; FIG. 5 represents a sectional view under a scanning microscope of the bottom of a via of size 50 μm / 300 μm covered with a seed layer as deposited in example 5; FIG. 6 represents a sectional view under a scanning microscope of the bottom of a 50 μm-400 μm-size via covered with a seed layer as deposited in example 5.

DETAILED DESCRIPTION OF THE INVENTION It has been discovered, and this forms the basis of the present invention, that it was possible to solve the above-mentioned technical problem by replacing the deposition steps of the barrier layer and the seed layer. by new steps. Figure 1 is a schematic diagram illustrating the steps of an embodiment of the treatment method according to the invention. Thus, according to a first aspect, the deposition of a barrier layer may advantageously be replaced by the deposition of a phosphorus-doped in-situ silicon layer, called an ISDP layer (in situ doped polysilicon with phosphorus). , whose function is to smooth the defects related to the anisotropic etching of silicon. Deposition of the seed layer is replaced by an electroplated copper growth step made from a specific electrodeposition composition adapted for the metallic copper to grow on the phosphorus in-situ doped silicon layer. Preferably, the electroplating solution used is a mixture based on copper and ethylenediamine precisely chosen. In particular, it comprises in solution in a solvent: copper ions in a concentration of between 14 and 120 mM; ethylenediamine; the molar ratio between ethylenediamine and copper being between 1.80 and 2.03; the pH of said composition being between 6.6 and 7.5. Electrodeposition is here understood to mean a process which makes it possible to cover a surface of a substrate with a metal or organometallic coating, in which the substrate is electrically polarized and placed in contact with a liquid containing precursors of said metal or organometallic coating, so as to forming said coating. When the substrate is electrically conductive, the electroplating is for example carried out by passing a current between the substrate to be coated constituting an electrode (the cathode in the case of a metal or organometallic coating) and a second electrode ( the anode) in a bath containing a source of precursors of the coating material (for example metal ions in the case of a metal coating) and optionally various agents intended to improve the properties of the coating formed (regularity and fineness of the deposit, resistivity, etc.), possibly in the presence of a reference electrode. By international convention the current and the voltage passing or applied to the substrate of interest, that is to say to the cathode of the electrochemical circuit, are negative. Throughout this text, when these currents and voltages are mentioned by a positive value, it is implicit that this value represents the absolute value of said current or of said voltage. The electrodeposition compositions presented can be used for any sequence of realization of the three-dimensional circuits (metallization prior to or after the step of thinning the silicon wafer). Such electrodeposition compositions make it possible to obtain a copper growth layer resulting in a particularly high coverage rate of the substrate (greater than 99%), including in the most critical zones, even when the structure has a high form (aspect ratio greater than 3: 1, or even of the order of 10 to 15: 1) and a relatively high volume of via (0.8.101 to 5.106 pm3). These compositions are therefore perfectly compatible with use on an industrial scale. A preferred family of compositions include those whose copper ions are present in a concentration of between 16 and 64 mM.

Another preferred family of compositions include those whose molar ratio of copper ions to ethylenediamine is between 1.96 and 2.00. Although there is no principled restriction on the nature of the solvent (provided it sufficiently solubilises the active species of the solution and does not interfere with electrodeposition), it will preferably be water.

In general, the electrodeposition composition according to the invention comprises a source of copper ions, in particular of Cu + Cu ions. Advantageously, the copper ion source is a copper salt such as in particular copper sulphate, copper chloride, copper nitrate, copper acetate, preferably copper sulphate, and preferably still copper sulphate pentahydrate. According to one particular characteristic, the copper ions are present in the electroplating composition in a concentration of between 14 and 120 mM; preferably between 16 and 64 mM. Excellent results have been obtained with compositions in which the source of copper ions is present in a concentration of between 16 and 32 mM. In the electrodeposition composition used, the molar ratio between the copper ions and the ethylenediamine is advantageously between 1.80 and 2.03, preferably between 1.96 and 2.00. In general, the electroplating composition used has a pH of between 6.6 and 7.5. This value is normally reached when the electrodeposition composition consists solely of copper ions and ethylenediamine in the proportions mentioned above.

The pH of the composition can optionally be adjusted within the aforementioned pH range by means of a buffer such as one of those described in: David R. Lide, CRC Press, Handbook of Chemistry and Physics at 84th Edition. wherein the electrodeposition composition according to the invention comprises compounds other than the source of copper ions and ethylenediamine. A presently preferred electrocoating composition comprises, in aqueous solution: copper ions, in a concentration of between 16 and 64 mM; ethylenediamine; the molar ratio between the ethylenediamine and the copper ions being between 1.96 and 2.00; the pH of said composition being between 6.6 and 7.5.

The process of coating the phosphorus in-situ doped silicon layer with metallic copper can be carried out by a simple electroplating step using the specific electrocoating solution presented above. According to this electroplating process, the in-situ phosphorus-doped silicon layer formed on the semiconductor substrate is first contacted with the specified electroplating solution, and then the surface of said doped silicon layer is polarized. in-situ to phosphorus for a time sufficient to form said copper coating. Prior to the electrodeposition process, pre-wetting having the function of forcing the penetration of the electroplating solution into the through vias may be necessary in certain cases, for example in the case of through vias with very high form factors. important. This pre-wetting can be carried out with the electroplating solution itself or with acidic solutions, neutral or basic, such as deionized water. Said substrates are brought into contact with said liquid solutions by using various physicochemical techniques capable of forcing the penetration of liquid solutions into through vias. These physico-chemical techniques can be jets for sending liquids at high pressure, ultrasound or the use of vacuum. According to a preferred embodiment as illustrated in FIG. 2, the step of coating the phosphorus in-situ doped silicon layer with metallic copper is carried out according to the electroplating method comprising: a step (S4-1) said cold inlet during which the surface of the phosphor in-situ doped silicon layer to be coated is brought into contact without electrical polarization with an electroplating bath containing the specified electroplating solution and is preferably maintained in this state for a period of at least 1 minute; a step (S4-2) of formation of the coating, that is to say copper growth, during which said surface is polarized for a time sufficient to form said coating; a so-called hot-outlet step (S4-3) during which said surface is separated from the electrodeposition bath while it is still under electrical polarization. In the electroplating process, the copper growth step as such, by electrodeposition, is conducted for a time sufficient to form the desired coating. This duration can be determined by those skilled in the art, considering that the growth of the film is a function of the charge which is equal to the time integral of the electric current passed in the circuit during the deposition time (Faraday's law).

During the coating forming step, the surface to be coated may be polarized, either in galvanostatic mode (fixed imposed current), or in potentiostatic mode (imposed and fixed potential, possibly with respect to a reference electrode), still in pulsed mode (current or voltage). In general, it has been observed that a particularly satisfactory coating can be obtained by pulsed mode polarization, preferably so as to impose current pulses. In general, this step can be carried out by imposing current slots corresponding to a current per unit of maximum area in a range of 0.6 mA / cm 2 to 10 mA / cm 2, and more particularly to 1 mA / cm 2 at 5 mA / cm 2 and at a current per unit area minimum in a range of 0 mA / cm 2 to 5 mA / cm 2, and preferably 0 mA / cm 2. More particularly, the polarization time at the maximum current can be between 2.10-3 and 1.6 seconds, preferably between 0.1 and 0.8 seconds, for example of the order of 0.35 seconds, while the polarization time at the minimum current may be between 2.10-3 and 1.6 seconds, preferably between 0.1 and 0.8 seconds, for example of the order of 0.25 seconds. The number of cycles to be performed during this coating step depends on the desired thickness of the coating. This embodiment of the invention has made it possible to produce copper nucleation layers having a thickness of between 50 nm and 2 μm on highly resistive substrates of via-through type structures, whose square resistance can reach 1000 ohm / square, or even a few mega ohms / square.

Following deposition of the copper layer, annealing is preferably performed to improve adhesion between the copper layer and the doped silicon layer. This annealing is carried out at a temperature permitting diffusion of the copper in the silicon to form a copper silicide. This temperature, as described in many metallurgical works, must be of the order of 550 ° C. The manufacturing scheme for stacks with through vias resulting from the present invention is therefore generally divided into a succession of steps comprising: etching (S1) the vias in or through the silicon wafer; deposition (S2) of an insulating dielectric layer (generally consisting of oxide or silicon nitride, for example); the deposition (S3) of a phosphorus-doped in-situ silicon layer making it possible to smooth the defects resulting from the etching of the vias in or through the silicon wafer; - Deposition (S4) of a thin layer of copper metal, called seed layer in a process of electroplating, and possibly the filling of the vias by the same copper electrodeposition process; and elimination of excess copper by chemical mechanical polishing.

According to a second aspect, the present invention relates to the manufacture of a cross-over type structure in the manufacture of interconnections for integrated circuits. The dimensions of these via-through type structures have a high form factor (aspect ratio greater than 3: 1, or even of the order of 10 to 15: 1) and a relatively high volume of via (0.8.101 at 5.106 pm3). These compositions are therefore perfectly compatible with use on an industrial scale. This manufacturing method is particularly useful for the production of vias covered by an insulating dielectric layer having a thickness which may be of the order of 10 nm to 10 μm, preferably 200 nm to 2 μm, for example 1.5 μm, of a phosphorus in-situ doped silicon layer having a thickness which may be of the order of 10 nm to 10 μm, preferably of 200 nm to 2 μm, for example of the order of 1.5 μm. pm, and a copper seed layer having a thickness which may be of the order of 50 nm to 2 μm, preferably 200 to 1.5 μm, for example of the order of 300 nm. The present invention will now be illustrated by the following nonlimiting examples, in which the succession of steps according to the invention is used to manufacture through vias coated with an insulating dielectric layer, a silicon layer doped in-situ with phosphorus and a copper germination layer.

These examples find particular application in the manufacture of copper interconnection structures for integrated circuits.

EXAMPLE 1: Preparation of a copper seed layer on an ISDP layer using an electroplating composition based on a mixture of copper and ethylenediamine.

A. Material and Equipment Al. Substrate: The substrate used in this example consists of a silicon wafer 150 mm in diameter and 675 μm thick. This plate is covered with a silica layer having a thickness of 1.6 μm, itself coated with a phosphor doped polysilicon (ISDP) layer of 1.5 μm thickness. A2. Electrodeposition Solution: The electrodeposition solution used in this example is an aqueous solution containing 8.4 mL / L (or 128 mM) of ethylenediamine and 16 g / L (or 64 mM) of Cu 504 (H 2 O ) 5, having a pH of 7.2. A3. Equipment: In this example, electrolytic deposition equipment representative of those employed in the microelectronics industry capable of processing plates 150 mm in diameter was used. This equipment comprises an electrolytic deposition cell in which the deposition of the seed layer is performed and a rinsing / drying station used after deposition. The electrolytic deposition cell comprises a copper anode, the silicon plate coated by the ISDP layer constituting the cathode of this cell. This cell further comprises a stabilized power supply for supplying up to 120 V and 15 A and a device for electrically contacting the cathode physically isolated from the solution by a seal. This electrical contacting device is generally annular in shape and allows a supply of the substrate at a plurality of contact points arranged in a regular manner thereon. It also comprises a support device for the plate to be coated with means for rotating said predetermined speed plate.

B. Experimental protocol B1. Step 1: Prewetting In this example, no prewetting of the substrate has been carried out.

B2. Step 2: Cold Entry This step can be broken down into two sub-steps: B2-1. The aforementioned substrate is introduced into the electrolytic deposition cell so that the face comprising the ISDP layer comes into contact with the electrical contacting device, the latter still not being electrically powered.

B2-2. The assembly formed by the electrical contacting device and the substrate, which will be hereinafter referred to as a cathode assembly, is brought into contact by dipping with the electroplating solution. This contacting, whose duration is generally less than or equal to 5 seconds (for example 2 seconds) is performed while the device is still not electrically powered. Preferably, the cathode assembly is then maintained in the electrodeposition solution without polarization for a period of at least 1 minute. B3. Step 3: Formation of the copper coating The cathode assembly is then polarized in galvano-pulsed mode and simultaneously rotated at a speed of 20 to 100 revolutions per minute (20 rpm, for example). FIG. 3 describes in detail the galvano-pulsed protocol that can be used, with a total period P of between 10 ms and 2 s (0.6 s in the example), a polarization time ToN of between 2 ms and 1.6 s (0.24 s in the example) by imposing a current per unit area generally between -0.6 mA / cm2 and -10 mA / cm2 (- 1.34 mA / cm2 in the example ), a non-polarization rest period of between 2 ms and 1.6 s (0.36 s in the example). The duration of this step depends, as understood, on the desired thickness of the seed layer. This duration can be easily determined by those skilled in the art, the growth of the film being a function of the charge in the circuit.

Under the aforementioned conditions, the deposition rate is about 1.6 nm per coulomb of charge passed in the circuit, which gives a duration of the electroplating step of the order of 60 minutes to obtain a coating having a thickness of 950 nm.

B4. Step 4: Cold Exit This step can be broken down into two sub-steps: B4-1. After the electroplating step, the polarization is cut off and the copper coated cathode assembly is removed from the zero rotational electrodeposition solution. The duration of this phase is about 2 seconds. The rotational speed is then increased to 500 rpm for 10 seconds, the polarization of the cathode assembly being cut off during this last phase. Pre-rinsing with deionized water is carried out in the cell.

B4-2. The substrate coated with the seed layer is then transferred to the rinse / dry module for rinsing with deionized water. The rinsing water is then evacuated and drying under a nitrogen sweep is carried out. Rotation is then stopped to allow removal of the coated and dried substrate. C. Results Obtained By applying the experimental protocol set out above, a copper layer of 950 nm and 400 nm thickness was obtained. The measurements and characterizations performed after deposition of the seed layer are presented in Examples 7 and 8.

EXAMPLE 2 Preparation of a copper seed layer on an ISDP layer freed of its native silicon oxide, using an electroplating composition based on a mixture of copper and ethylenediamine. A. Materials and Equipment Al. Substrate: The substrate used in this example consists of a silicon wafer 150 mm in diameter and 675 μm thick. This plate is covered with a silica layer having a thickness of 1.6 μm, itself coated with a phosphor doped polysilicon (ISDP) layer of 1.5 μm thickness. In this example, a chemical treatment of the substrate was carried out before starting the electroplating process. This treatment is intended to remove the silicon oxide formed on the surface of the ISDP. It consists, for example, in immersing the plate in an NH4F / HF liquid solution in volume proportions of 50: 1 for a period of 4 minutes.

A2. Electrodeposition solution: The electroplating solution used in this example is identical to that of Example 1. A3. Equipment: The equipment used in this example is identical to that of example 1.

B. Experimental Protocol The experimental protocol used in this example is identical to that of Example 1.

C. Results Obtained By applying the experimental protocol set out above, a copper layer 950 nm thick was obtained. The measurements and characterizations performed after deposition of the seed layer are presented in Examples 7 and 8.

EXAMPLE 3 Preparation of a copper seed layer on an ISDP layer using an electrodeposition composition based on a mixture of copper and ethylenediamine with increase in the deposition rate.

A. Materials and Equipment Al. Substrate: The substrate used in this example is identical to that of Example 1. A2. Electrodeposition solution: The electroplating solution used in this example is identical to that of Example 1. A3. Equipment: The equipment used in this example is identical to that of example 1.

B. Experimental protocol B1. Step 1: Prewetting In this example, no prewetting of the substrate has been carried out. B2. Steps 2: cold entry This step is identical to that of example 1.

B3. Step 3: Formation of the copper coating The cathode assembly is then polarized in galvano-pulsed mode and simultaneously rotated at a speed of 20 to 100 revolutions per minute (20 rpm, for example).

FIG. 3 describes in detail the galvano-pulsed protocol that can be used, with a total period P of between 10 ms and 2 s (0.2 s in the example), a polarization time ToN of between 2 ms and 1.6 s (0.1 s in the example) by imposing a current per unit area generally between -0.6 mA / cm2 and -10 mA / cm2 (-1.34 mA / cm2 in the example ), a non-polarized rest time of between 2 ms and 1.6 s (0.1 s in the example). The duration of this step depends, as understood, on the desired thickness of the seed layer. This duration can be easily determined by those skilled in the art, the growth of the film being a function of the charge in the circuit. Under the above conditions, the deposition rate is about 2.7 nm per coulomb of charge passed in the circuit, which gives a duration of the electroplating step of the order of 29 minutes to obtain a coating having a thickness of 1 μm. B4. Step 4: Cold Output This step is identical to that of Example 1.

C. Results Obtained By applying the experimental protocol set out above, a 1 μm thick copper layer was obtained. The measurements and characterizations performed after deposition of the seed layer are presented in Examples 7 and 8.

EXAMPLE 4: Preparation of a seed layer in cross-over-type structures using an electroplating composition based on a mixture of copper and ethylenediamine.

A. Material and Equipment Al Substrate: The substrate used in this example consists of a silicon plate 150 mm in diameter and 675 μm thick, etched with cylindrical patterns of type via through depth 200 μm and of diameter 50 pm.

This plate is covered with a silica layer having a thickness of 1.6 μm, itself coated with a phosphor doped polysilicon (ISDP) layer of 1.5 μm thickness. A2. Electrodeposition solution: The electroplating solution used in this example is identical to that of Example 1. A3. Equipment: The equipment used in this example is identical to that of example 1.

B. Experimental protocol B1. Step 1: Pre-Moisture Physico-chemical treatment is carried out before step 2 cold entry in order to increase the wettability of the electroplating solution in the vias and to expel the air bubbles. It consists of immersing the plate in an acidic or neutral solution (for example de-ionized water) and placing it in an ultrasonic tank for a period of at least 5 minutes (for example 10 minutes). This chemical treatment may vary according to the nature of the substrate and the size of the through vias. The wafer can thus be removed from the solution and introduced wet into the electroplating cell.

B2. Steps 2, 3, 4: These steps are identical to those of Example 1.

C. Results Obtained The measurements and characterizations performed after deposition of the seed layer by applying the experimental protocol set out above are presented in Example 9.

EXAMPLE 5 Preparation of a germination layer in cross-over type structures using a composition according to the invention based on a mixture of copper and ethylenediamine.

A. Material and equipment A1. Substrate: The substrate used in this example consists of a silicon wafer 150 mm in diameter and 675 μm thick, etched with cylindrical patterns of the via type having a depth of 300 μm and a diameter of 50 μm.

This plate is covered with a silica layer having a thickness of 1.6 μm, itself coated with a phosphor doped polysilicon (ISDP) layer of 1.5 μm thickness. A2. Electrodeposition solution: The electroplating solution used in this example is identical to that of Example 1. A3. Equipment: The equipment used in this example is identical to that of example 1.

B. Experimental protocol B1. Step 1: Pre-Moisture Physico-chemical treatment is carried out before step 2 cold entry in order to increase the wettability of the electroplating solution in the vias and to expel the air bubbles. This treatment is carried out in the rinsing / drying module also used in step 4. The substrate is inserted into this rinsing / drying module and rotated at a speed of 1 rpm for at least 1 minute (for example 7 minutes), then 100 rpm for at least 1 minute (for example 7 minutes) and finally 1 rpm for at least 1 minute (for example 7 minutes).

An acidic or neutral solution (for example de-ionized water) is sent onto the substrate during the entire period of rotation of said substrate, by means of spray nozzles located opposite each other. Following this treatment, the rotation is stopped to allow the removal of the substrate. The wafer is introduced wet into the electrodeposition cell B2. Steps 2, 3, 4: These steps are identical to those of Example 1.

C. Results Obtained The measurements and characterizations performed after deposition of the seed layer by applying the experimental protocol set out above are presented in Example 9.

EXAMPLE 6 Preparation of a seed layer in cross-over type structures using a composition according to the invention based on a mixture of copper and ethylenediamine.

A. Material and equipment A1. Substrate: The substrate used in this example consists of a silicon wafer 150 mm in diameter and 675 μm thick, etched with cylindrical patterns of the through type with a depth of 400 μm and a diameter of 50 μm.

This plate is covered with a silica layer having a thickness of 1.6 μm, itself coated with a phosphor doped polysilicon (ISDP) layer of 1.5 μm thickness. A2. Electrodeposition solution: The electroplating solution used in this example is identical to that of Example 1. A3. Equipment: The equipment used in this example is identical to that of example 1.

B. Experimental protocol B1. Step 1: Pre-Moisture Physico-chemical treatment is carried out before step 2 cold entry in order to increase the wettability of the electroplating solution in the vias and to expel the air bubbles. This treatment is performed in a specific cell where a vacuum can be performed.

The substrate is inserted into this cell and a vacuum is applied using a paddle pump (in the example the pressure is 1 mbar). Still under vacuum, an acidic or neutral solution (for example de-ionized water) is introduced into this cell and covers the substrate. When the entire wafer is immersed, the cell is slowly brought to atmospheric pressure. The wafer can thus be removed from the solution and introduced wet into the electroplating cell. B2. Steps 2, 3, 4: These steps are identical to those of Example 1.

C. Results Obtained The measurements and characterizations performed after deposition of the seed layer by applying the experimental protocol set out above are presented in Example 9.

EXAMPLE 7 Characterization of the resistivity of the seed layer obtained on the ISDP layer using an electrodeposition composition based on a mixture of copper and ethylenediamine.

A. Materials and Equipment The square resistance (called sheet resistance in English) was measured using a device of the 4-point measurement type (called point probe oven in English) well known to those skilled in the art for measuring electrical resistance of thin layers. It is expressed in ohm / square and is equivalent to the resistivity for a two-dimensional system, that is to say in which the current flows in the plane of the layer and not in a plane perpendicular to this layer. Mathematically, the value of the square resistance is obtained by dividing the resistivity of the material (expressed in ohm.m or micro-ohm.cm) constituting the layer by the thickness of this layer (expressed in mou nm). The anneals are carried out in a horizontal tubular furnace. It consists of a base supporting a cylindrical body, itself consisting of an inner ceramic tube around which is wound the heating element. A metal casing and cylindrical wire mesh envelop the whole to allow ventilation of the ceramic tube. The oven is used in conjunction with a quartz tube to receive the samples. This quartz tube fits into the ceramic tube. The quartz tube is provided at its left end with a removable break-in which is connected a flexible pipe for bringing a gas sweep (mixture N2 96% / H2 4%) in the tube. This makes it possible to perform N 2 / H 2 sample annealing with an extremely low rate of oxygen. Annealing may also be performed in various equipment such as RTP (Rapid Thermal Processing) or RTA (Rapid Thermal Annealing). In these fast annealing furnaces, the heating elements are lamps and the substrate is heated by infrared radiation.

B. Measurement method The square resistance value multiplied by the thickness of the seed layer gives the resistivity of the copper.

C. Results Obtained The copper resistivities obtained in Examples 1 to 3 above are indicated in Table 1.

Table 1: resistivity of the copper seed layers obtained according to Examples 1 to 3. Thickness layer Cu Resistivity Resistivity conditions after germination in (nm) before annealing annealing copper annealing obtained (pohm.com) (pohm.com) according to example 1 400 2.5 670 ° C 8min 3.6 example 1 950 2.4 670 ° C 8min 3.4 example 2 950 2.2 670 ° C 8min 4.3 example 3 1000 2.4 670 ° C 8min 6.3 An increase in resistivity of the seed layer is observed in all cases after annealing, related to the formation of copper silicide. These levels of resistivity measured before and after annealing are fully compatible with use on an industrial scale.

EXAMPLE 8 Characterization of the adhesion of the germination layer obtained on the ISDP coat with the aid of an electro-deposition composition based on a mixture of copper and ethylenediamine.

A. Materials and Equipment The equipment used in this example is identical to that of Example 7, but annealing may also be performed in various equipment such as RTP.

B. Measurement Method The adhesion or interface energy was measured using the so-called square test technique. A pattern representing 16 squares of 0.5cm side is plotted with a diamond tip in the seed layer. An adhesive tape is then placed on these squares, and a vertical tension force is manually applied by tearing off the adhesive tape. A count of the number of squares remaining on the sample is then made, representative of the adhesion energy between the ISDP substrate and the seed layer.

C. Results Obtained Table 2 below collates the results obtained in Examples 1 to 3 above.

Table 2: adhesion of the copper seed layers obtained according to Examples 1 to 3. Germination layer Thickness Conditions Adhesion after copper annealing obtained Cu (nm) annealing (X / 16 squares) according to Example 1 400 670 ° C 8min 11 Example 1 950 670 ° C 8min 11/16 Example 2 950 670 ° C 8min 16/16 Example 3 1000 670 ° C 8min 16/16 EXAMPLE 9: Characterization of the coverage of the seed layer obtained in structures of cross-over type using an electroplating composition based on a mixture of copper and ethylenediamine.

A. Materials and Equipment The coverage and compliance of the copper seed layer was evaluated from sectional observations under a scanning electron microscope, focusing on the bottom of the structures which is the most difficult area to cover. .

B. Method of measurement The percentage of coverage is measured in the lower zone of the structures, between the bottom of the vias and 4 pm above. A percentage of 100% corresponds to complete coverage i.e. in the lower zone the surface of the barrier is entirely covered with copper. A surface partially covered with copper is characterized by the fraction of the surface covered with copper, expressed in percent. When the coverage is complete, the percent compliance is calculated by relating the thickness of the seed layer to the vertical surfaces (profile or sidewall) of the via to that on the horizontal surfaces at the top of the via. The thickness on the vertical surfaces is measured at a given depth of the via (4 μm above the bottom of the via). A percentage of 100% corresponds to perfect compliance.

C. Results Obtained Table 3 below summarizes the results obtained on the copper germination layers prepared using the compositions of Examples 4 to 6 above. The observations with a scanning electron microscope are shown in FIG. 4 in the case of Example 4, Figure 5 in the case of Example 5 and Figure 6 in the case of Example 6. Table 3: Conformity and coverage of the copper seed layers obtained according to Examples 4 to 6. Cover germination layer (%) Conformity (%) copper obtained according to example 4 100 40-60 example 5 100 10-30 example 6 100 10-20

Claims (10)

REVENDICATIONS1. A method of processing a semiconductor substrate comprising the steps of: - etching (S1) to form at least one pattern forming a recess, especially a via-through type, with respect to the surface of said semiconductor substrate; depositing (S2) an insulating dielectric layer on said surface of said semiconductor substrate; depositing (S3) a phosphorus in-situ doped silicon layer on said insulating dielectric layer; coating (S4) of said phosphorus in-situ doped silicon layer with a layer of metallic copper, the coating step (S4) comprising electroplating using an electroplating solution adapted for growth of the metallic copper on silicon doped in situ with phosphorus. 2. The method of claim 1, wherein the coating step (S4) comprises the following successive sub-steps: - contacting (S4-0) of said phosphorus in-situ doped silicon layer with the solution of electroplating, and - biasing (S4-2) said phosphorus in-situ doped silicon layer to an electrical potential for electroplating copper metal onto said phosphorus in-situ doped silicon layer. 3. The method of claim 2, wherein the coating step (S4) further comprises a sub-step of maintaining (S4-1), for a determined duration, said phosphorus in-situ doped silicon layer in contact with the electrodeposition solution without electrical polarization, said substep of maintaining (S4-1) being performed between the substep of contacting (S4-0) and the substep of polarization (S4-2) . 4. Method according to one of claims 2 or 3, wherein the coating step (S4) further comprises a hot exit sub-step (S4-3) during which said doped silicon layer indoors. Phosphorus is separated from the electroplating solution while still under electrical bias, said hot exit substep (S4-3) being performed after the polarization substep (S4-2). 5. Method according to one of claims 1 to 4, wherein the coating step (S4) comprises a preliminary pre-wetting step comprising contacting the semiconductor substrate with a liquid solution. 6. The method of claim 5, wherein the contacting of the semiconductor substrate with the liquid solution is carried out by a physicochemical technique comprising the use of jets to send the high pressure liquid solution, and / or use of ultrasound, and / or the use of vacuum. 7. Method according to one of claims 1 to 6, further comprising an annealing step (S5) carried out after the coating step (S4), said annealing (S5) being carried out at a temperature chosen to allow diffusion of the copper in the silicon layer doped in-situ with phosphorus, so as to form a copper silicide. 8. Method according to one of claims 1 to 7, wherein the electroplating solution comprises, in solution in a solvent: - copper ions in a concentration between 14 and 120 mM, and - ethylenediamine, the molar ratio between ethylenediamine and copper being between 1.80 and 2.03, and the pH of said composition being between 6.6 and 7.5. 9. multilayer stack characterized in that it comprises: a semiconductor substrate with a surface having a pattern forming at least one hollow, in particular of the via-through type, an insulating dielectric layer covering said surface, a silicon layer; phosphorus in-situ doped coating covering said insulating dielectric layer, and a metal copper layer covering said phosphorus-in-situ doped silicon layer. The stack of claim 9, wherein the copper layer fills said at least one recess and comprises a planar outer surface.