FR2932040A1 - Electronic device for automatic switching of data in simulator circuit, has automatic switching unit arranged on line networks, and connection unit arranged between line networks for assuring switched connection between networks - Google Patents

Abstract

The device has an automatic switching unit arranged on logic networks (111) with two dimension, and a connection unit arranged between the logic networks for assuring switched connection between the networks. The logic networks offer possibilities of cabled logical operations on cojointed horizontal lines (160-165). A priority network (110) is connected to inlet/outlet of cells of a simulator circuit. The logic circuit comprises an initialization unit for initializing activation of signals.

Description

ELECTRONIC AUTOMATIC DATA DIALING DEVICE FOR THE SIMULATOR CIRCUIT

The present invention relates to a data referral device for simplifying the programming of the routing of data between cells of the simulator circuit object of the patent WO 2005/088839 referenced in [1]. In the electronic circuit [1], each cell output, internally, must be connected by instruction on an interconnection link. This greatly increases the size of the instructions with the size of the CIMTL and CPCE cells. On the other hand, the programmatic choice of links at each elementary cycle can prevent the transfer of conflicting data even in the event that the interconnection network is partially occupied. These two features make the circuit complex in programming and relatively inefficient. The device object of the present invention eliminates the need to schedule the assignment of each cell output on a link and makes the best use of all the interconnection links. It is a purely combinatorial operator that propagates the information through a mesh without the action of a clock and with multiple possibilities of logical operations Thanks to these provisions: the size of the instructions internal to the CIMTLs and CPCEs and therefore the complexity of the circuit [1] is reduced, the exchange of data from the CPCE cells is priority and without line deprivation, the loss of interconnection resources is reserved for exchanges between CIMTL cells to CIMTL or CIMTL to CPCE , more easily manageable by the schedule than the CPCEs with the input signals, the congestion situations that lead to the delays are less likely, the device supports logical operations with a large number of operands instead of CIMTL cells which leads to a performance gain and a simplification of the circuit programming.

The structure of the general network is divisible into interconnected networks. Thanks to these provisions: the size of the instructions is reduced, the internal network exchanges are independent and more dense by 5 their simultaneous operations. The connection points can be multiple on joint lines. Thanks to these arrangements, the transfer network offers possibilities for logic operations wired on joint lines only. The links are bi-directional and offer multiple combinations of links. With these provisions, the network allows multiple combinations of wired operations between cells (see Figure 9). Long signal paths require anticipatory functions on regular portions of the network to reduce delays. The size of these portions follows a compromise between the increased complexity due to the 15 anticipators and the reduction of the propagation delays: anticipators for too large portions increase their complexities and reduce their efficiencies, anticipators for too small portions increase the surpluses of complexity due to their number of these and reduces their efficiencies. Other advantages, aims and features of the present invention will emerge from the description of a particular embodiment, which will follow, made for an explanatory and non-limiting purpose with reference to the appended drawings in which: FIG. 1 schematically represents the internal interconnection device 25 with, for example, a 2-network structure, - Figure 2 shows, schematically, the connection between the CPCE and CIMTL cells within a single network. 3 represents the anticipated part of the links assigned to the source-side cells of the lattice of a lattice, FIG. 4 represents the Source Interconnect Cell: CIS, FIG. , the anticipating part, on the destination side, of the mesh of a network, - FIG. 6 represents the Interconnection Cell Destination: CID, - FIG. 7 represents the CIR Interconnection Cell, 35 - 1 FIG. 8 represents all the possible modes of bidirectional data transfer, FIG. 9 represents the chronology of the general network with respect to the circuit [1].

The principle of the network is to: connect the CPCE outputs (or inputs) on their horizontal lines: priority links, - connect the outputs (or inputs) of the CIMTL cells according to a pre-established order on horizontal lines not occupied by the CPCE outputs : mid-priority links, connect the horizontal lines on the vertical lines in priority to that useful for the CPCEs to the recipient cells, to - connect the following horizontal lines (including those assigned to the CIMTL) to the recipient cells, present signals to the cells accordingly recipients in the following order: CPCE signals in ascending topological order followed by CIMTL signals in ascending topological order on the designated inputs, by default connect the outputs of the cells to a part of their own inputs if they are not recipients: signal loopback, connect the cell outputs by default to another part of the inputs of other cells if they are not recipients: local links, connect the cell outputs to their inputs if they designate themselves as unique recipients: re-looping signals. As a result, the outputs of the cells are connected to the inputs of these cells or other cells according to a deterministic topology which depends only on the cell instructions. The exchange is spatial (no sequencing) and only clock cycle of the circuit [1]. A cell can address multiple recipient cells simultaneously on a single network (no recipients on multiple networks for simplicity). The addressing consists in designating several cell correspondents for a bidirectional exchange between CIMTL or CPCE cells: a signal output to one or more inputs, a signal input from one or more outputs, one or more outputs to several entries. In summary, signal routing operates on a principle of interception between vertical and horizontal requests and arrangements in a topological order. All logic operators used (gates) have only 2 states: 0 or 1 for OR, AND, OR exclusive and inverter gates, 15 20 0 or high impedance for so-called open collector gates. This avoids inevitable temporary (circuit) signal conflicts in the case of a 3-state operator: 0, 1 and high impedance. A pre-charge signal must first deactivate very quickly all the signals of the network according to the technology and the physical properties of the circuit [1]: see figure 9. Any activation takes place from 1 to 0 depending on the advantage given by the physical properties of semiconductors (mobility of positive charges greater than those of negative charges) to which the present invention is intended.

FIG. 1 describes the general principle of a network: the priority network 110 is connected on the inputs-outputs of all the CPCE cells of [1] so that they have horizontal lines 160 to 165, if a CPCE output 163 is activated by instruction: o a list of destination cells which concerns the destination cells of the network 110, is presented with, o the horizontal line 163 becomes a priority, where the CID cell 190 intercepts this request with the destination addressed to the connected cell 140 and connects the horizontal line 163 on the vertical line 140. if a CPCE output 160 is activated by instruction: o a list of destination cells which relates to the destination cells of the network 111, 25 o a horizontal line 160 becomes a priority with a transit indication in the network 110, where the CID cell 194 intercepts this request with the destination addressed to the cell connected to the vertical line 150 and connects the line horizontal 170 to the vertical line 150, 30 if a CIMTL output on the vertical line 120 is activated by instruction: o the horizontal line 165 which is the first available (not monopolized by the CPCE connected thereto) is connected on the vertical line 120 by the CIS 180 cell and becomes a mid-priority, where the CID cell 193 intercepts this request with the destination 35 addressed to the cell connected to the vertical line 141 and connects the horizontal line 165 to the vertical line 141, - the second output CIMTL on the vertical line 122 is activated by instruction, it is connected to the line 164 through the CIS 181 and the CID 192 according to the same principle. the second output CIMTL on the vertical line 133 is activated by instruction, it is connected to the line 142 through the CIS 183 and the CID 191 according to the same principle but with the difference that the horizontal line 162 is not a priority . A horizontal or vertical line is a group of signals that contain, in addition to the useful data, routing information. to Vertical lines also contain signal direction information. The CIS or CID cells are responsible for connecting two lines that intersect according to the information that these lines convey and the information that these cells exchange. The outputs of the CPCE cells consist of: an output connection request (or inputs) per output, the output signal with high impedance setting in the absence of activation, a group of signals of which a part addresses the destination network and the other list of all possible recipients per network with 20 wired operations indication. The outputs of the CIMTL cells consist of: an output connection request per output, the input-output signal, a direction signal, a selection of the recipient list: sharing of the recipient lists between outputs for reasons of resource saving a group of signals, one part of which addresses the destination network and the other a list of all the possible recipients per network; The inputs of the CIMTL or CPCE cells consist of: the input-output signal, a direction signal, a signal which indicates the use of the vertical line by the destination cell. The priority attribute for the horizontal lines means that they are made available primarily to the CPCEs or CIRs connected thereto. The mid-priority attribute means that the horizontal lines are successively made available outside the priority lines. 510 The other horizontal lines are made available successively once the two previous types have been allocated.

Network-specific signals, some of which are anticipated, propagate to organize connections. FIG. 2 represents the mesh of macro-cells which group interconnection cells with shared resources whose anticipators:

the CALLS (see FIG. 3) macro-cells (Anticipated Cells of Source Line Bindings) group together a CIS cell matrix (see FIG. 4) are connected to the CPCE and CIMTL cell outputs,

the macro cells (CALLD Anticipated Forward Link Cell) (see FIG. 5) group together a matrix of CID cells (see FIG. 6) are connected to the CPCE and CIMTL cell inputs. The information propagates from left to right and from bottom to top in the mesh. A column of CALLS macro cells corresponds to a CIMTL in this representation without this being an obligation.

A macro cell column CALLD possibly corresponds to a CPCE or CIMTL in this representation without this being an obligation.

20

Figure 3 shows the CALLS macro-cell.

The cells receive global signals:

from top to bottom concerning the requests for connections produced by the CIMTL cells: o connection requests on 2 signals for the CIS cells,

o sense of transfer,

o CIMTL input-output signals for CIS cells,

o selection of the list of recipients for the CIS cells,

o group of recipient lists common to the group at the CIS of the CALLS macro 30 cell. - from left to right concerning the requests for connections produced by the CIMTL or CPCE cells:

o indication of occupation for the CIS cells, o indication of wired operation in progress for the CIS cells, 35 o list of the recipients, common to the CIS by horizontal lines.

The destination selection modules 330 to 332 select a recipient list from those provided to all the CIS in the CALLS macro cell and provided by a CIMTL cell in this example. CIS cells 300 through 323 propagate information from bottom to top and from left to right. These signals include: CIS connection information, a wired operation in progress. The anticipator module 340 prepares the connection indication signals according to those received on the input of the CALLS macro cell before they propagate from the bottom upwards. The anticipator module 341 prepares the connection indication signals according to those received on the input of the CALLS macro cell before those propagate from left to right. Figure 4 depicts the CIS cell. This must connect the requesting signal from the CIMTL according to the following information: connection request from the CIMTL: o state 11 no request, 20 o state 00 simple connection request, o state 10 connection request in wired operation: see connections 811 and 812 in FIG. 8, o state 01 connection request in wired operation with polarity inversion: see links 811 and 812 in FIG. 8, indication of the direction of transfer: o 0: cell output, o 1: input cell, indication of line occupation of the left: o 1: available line, 30 o 0: line already taken. wired operation indication in progress from left: ^ 1: not in progress, o 0: in progress. bottom authorization indication: 35 o 1: unauthorized: unauthorized connection to this location, o 0: allowed: connection permitted from this location. The bottom-up authorization signal defines in the vertical direction the horizontal lines left available by the higher priority CPCEs. The CIS detects the limit of this zone with the gate 410 favorable to a connection request.

If, on the other hand, the horizontal line is taken but with a wired operation indication in progress, the gate 402 is a second indication favorable to a connection. If these indications are favorable for a connection (gate 403), the connection requests are taken into account. In this case: the door 411 indicates any request and the connection takes place, through the doors 405 to 407, with presentation of the list of recipients selected from the log2 (N) if there are N selection signals, the door 405 connects the vertical signal on the horizontal line in the output direction, the gate 405 connects the horizontal signal to the vertical line in the direction entered.

The right busy line signal is activated by the gates 412 and 413. The gate 420 indicates a wired operation request which propagates to the indication in the right course by the gate 401. This does or does not reverse the CIMTL signal by gate 421, according to the desired wired operation: - AND wired, OR wired, Logical comparison with a constant. 25 A wired operation on a horizontal line: begins or continues with a wired operation request: states 10 or 01 on the CIMTL request, ends with a simple connection request or no request: states 00 or 11 on the request CIMTL. The wired operation can only be done on co-applicant signals for the sake of simplicity.

Figure 5 shows the macro cell CALLD. The cells receive global signals from bottom to top which relate to: the requests for connections produced either by the CIMTL cells or by the CPCE cells, the transfer direction, the data signals of the vertical line, the given priority indications priority horizontal lines, the connection signals on the vertical line. Thus the cell receives the signal programmed by instruction.

The CID cells 500 to 523 receive global signals from left to right which concern: the data signal of the horizontal line, the selection specific to the recipient cell, the transit signal to inhibit any connection in this network. The CID cells 500 to 523 propagate signals, CID to CID, from left to right: the assignment indication already made on the horizontal line, the priority horizontal line indication to be considered.

The anticipator module 530 prepares the authorization signals before they propagate from bottom to top from the left assignments, low permissions, and global high priority indications to the CALLD cell macro. The anticipator modules 531 and 532 respectively prepare the high and right priority indications before they propagate from bottom to top and left to right from the global right and left priority indications to the cell macro CALLD. The anticipator module 533 prepares the right assigned indications before they propagate from left to right from the left assignment indications and low requests and authorizations.

Figure 6 shows the destination Interconnect Cell CID. Gate 621 indicates any selection on the cell assigned to the vertical line. Gate 602 allows this request if the network is selected. The gate 607 allows the connection if there is no more priority connection on the same vertical line: priority to 0. The gate 624 indicates an authorized connection: either because the topology allows it: authorization low to 0, or because there is a wired operation in progress: wired input low to 0. Since there is a request in progress from the destination cell (request to 0) and there is Since no connection has already been assigned to the horizontal line (assigned left to 1), gate 605 activates the connection through gates 604 and 660. This results in either: if the direction is 0, the signal copy horizontal data on vertical data if the selection 1, if the direction is 1, the opposite. inverting signals when copying if the selection is 1.

The connection indication: warns an assignment by gate 622 to prevent further connections on that horizontal line for the destination cell only, signals a connection on the vertical line through gate 662: if no connection is made signaled the re-looping of a cell output on the vertical line is validated by default, indicated by the gate 601 a wired operation in progress if the selection requests it by the gate 640: selections in the state 01 or 10: any other selection stops the current wired operation. The gates 610 and 623 propagate in the horizontal direction and in the vertical direction the priority domain reserved for the priority horizontal lines: the first connections are reserved for the priority lines in the left-hand direction in order to present to the destination cell the order next: priority sources and then non-priority sources. The priority signal indicates the presence of a higher priority connection reserved for the CID 20 which delimits the low limit of the priority domain (priority low to 0 and priority left to 1), by the gates 609 and 661. If the CID is in low limit of the priority domain or if there is a wired operation in progress, the gate 625 allows the connection. Gate 620 allows connection to upper CIDs if there has not already been connection. The pre-charge signal initializes the states before the automatic referral operations: see figure 10.

Figure 7 shows the interconnection cell between CIR networks. The decoder 700 takes a part of the selection of the horizontal line and deduces from this whether the attached network or its successive networks are addressed together with the gate 710. In this case the gates 711, 713, 730 and 732 pass the signal of given and selection to the attached network. The transit flag is set to 0 to inhibit any destination connection in the first network. The indication occupied on one of the networks gives priority to the horizontal line. 15 20 25 30 35 li

In the right / left direction, the resonance applies with the decoder 701 and the gates 720, 712, 714, 731 and 733 with the difference that the horizontal line is not priority. If a delay of passage from one network to another is too high, the possible introduction of registers on all the CIR signals sequences the operation in two elementary cycles of the circuit [1].

FIG. 8 shows all the possible connections between the cell of the circuit [1]: link 800: an output (or input) CPCE or CIR (see FIG. 7) which has priority 850 is connected to a single input (or output) by any cells recipients 830 to 831 (a horizontal line 870 for as many vertical lines 860 to 861 as destination cells) so that: o an output signal enters on several cells simultaneously, o that input signal receives several combined outputs: operation logic wired, o or more generally that there is a combination between the two previous situations. Binding 810: several outputs (or inputs) together of several cells CPCE or CIRC 851 to 852 are in different wired operation on several cells 832 and 833, by the horizontal lines 871 to 874 and vertical 862 to 863. Link 801: a cell CIMTL 834 is connected on several cells 835 to 836 by a source vertical line 863, a horizontal line 875 and a plurality of vertical lines 864 to 865. Link 811: several joint CIMTL outputs 837 to 838 are wired on the horizontal line 876 to destination of several cells 839 to 840. Link 812: several rows of CIMTL cells 841 to 842 and 843 to 844, are in different wired operations on the horizontal lines 877 to 878 and destined for several cells 845 to 846 for different wired operations . It is the most complex link. Binding 820: a cell 847 is looped back on itself on certain inputs if it is the only recipient without recourse to horizontal lines. Link 821: a cell 848 is in relation to another cell 849 by default on certain entries if the latter are not the subject of destinations.

Link 822: a cell 880 and in relation to another part of these entries if it is not a recipient.

Figure 9 shows the timing of the switching signals. Beforehand, the pre-charge signal common to the general network quickly initializes all the signals as shown in the timing diagram 900. As soon as deactivated, the instructions inside the cells choose the input-outputs and their destinations as well as the useful inputs-outputs. to refer the signals to the corresponding inputs. The CIS cells connect the source vertical lines to the horizontal lines left available by the inactivated CPCE or CIR outputs as shown in timing chart 901. The CID cells connect the horizontal lines to the vertical lines: the priority lines followed by the mid-priority lines then non-priority lines. The pre-charge phase can occur during the propagation of the signals in CPCE or CIMTL cells before storage as shown in the timing diagrams 901 to 903.

Claims (1)

CLAIMS1 - Electronic device for connecting the cells of the circuit object of the patent WO 2005/088839: a combinational logic network with two directions on a plane, a means of automatic connection separated between lines which follow two directions on a plane, a means of joint connections between lines which follow two directions on a plane for wired logic operations; - an automatic and rational switching means on a two-dimensional line network; - a connection means between two networks for common links between networks. An electronic device according to claim 1, characterized in that the connection network needle the data of the cells of the simulator circuit object of patent WO 2005/088839 on the only indications of destination cells for a precise destination on the inputs of each cell. said simulator circuit. 3 - electronic device according to claims 1 and 2, characterized in that the network 20 operates without sequencing of the switching operations, but on combinatorial operations. 4 - electronic device according to claims 1 to 3, characterized in that the logic network comprises anticipating means reducing the propagation time of the signals useful for the automatic referral of data. 5 - Electronic device according to claims 1 to 4, characterized in that the logic network comprises a signal initialization means followed by a rapid activation of these signals. Electronic device according to claims 1 and 2, characterized in that the network allows a variety of bidirectional links in cells. 7 - Electronic device according to claims 1 and 2, characterized in that the general communication network is fragmented into interconnected networks allowing a data transfer as many times denser than existing networks. 8. An electronic device according to any of claims 1, 2 and 4, characterized in that the network integrates a basic structure of anticipating modules with a single structure. 9- An electronic device according to any one of claims 1 to 5, characterized in that the network is made of repetitive and joint units.10- electronic device according to any one of claims 1 to 5, characterized in that the present network an alternation or not of type of macro-cells to adapt to the physical architecture of the circuit.