FR2898223B1 - Circuit de distribution d'un signal initial a structure en arbre protege contre les aleas logiques. - Google Patents

Circuit de distribution d'un signal initial a structure en arbre protege contre les aleas logiques.

Info

Publication number
FR2898223B1
FR2898223B1 FR0601832A FR0601832A FR2898223B1 FR 2898223 B1 FR2898223 B1 FR 2898223B1 FR 0601832 A FR0601832 A FR 0601832A FR 0601832 A FR0601832 A FR 0601832A FR 2898223 B1 FR2898223 B1 FR 2898223B1
Authority
FR
France
Prior art keywords
aleas
distributing
circuit
protected against
shaft structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0601832A
Other languages
English (en)
Other versions
FR2898223A1 (fr
Inventor
Philippe Roche
Francois Jacquet
Jong Jean Jacques De
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0601832A priority Critical patent/FR2898223B1/fr
Priority to US11/713,469 priority patent/US7741877B2/en
Publication of FR2898223A1 publication Critical patent/FR2898223A1/fr
Application granted granted Critical
Publication of FR2898223B1 publication Critical patent/FR2898223B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/0033—Radiation hardening
    • H03K19/00338—In field effect transistor circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
    • H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
    • H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
FR0601832A 2006-03-01 2006-03-01 Circuit de distribution d'un signal initial a structure en arbre protege contre les aleas logiques. Expired - Fee Related FR2898223B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0601832A FR2898223B1 (fr) 2006-03-01 2006-03-01 Circuit de distribution d'un signal initial a structure en arbre protege contre les aleas logiques.
US11/713,469 US7741877B2 (en) 2006-03-01 2007-03-01 Circuit for distributing an initial signal with a tree structure, protected against logic random events

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0601832A FR2898223B1 (fr) 2006-03-01 2006-03-01 Circuit de distribution d'un signal initial a structure en arbre protege contre les aleas logiques.

Publications (2)

Publication Number Publication Date
FR2898223A1 FR2898223A1 (fr) 2007-09-07
FR2898223B1 true FR2898223B1 (fr) 2008-07-11

Family

ID=37697862

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0601832A Expired - Fee Related FR2898223B1 (fr) 2006-03-01 2006-03-01 Circuit de distribution d'un signal initial a structure en arbre protege contre les aleas logiques.

Country Status (2)

Country Link
US (1) US7741877B2 (fr)
FR (1) FR2898223B1 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7616043B2 (en) * 2008-02-12 2009-11-10 Sony Computer Entertainment Inc. Methods and apparatus for managing LSI power consumption and degradation using clock signal conditioning
US8476972B2 (en) * 2010-06-11 2013-07-02 Taiwan Semiconductor Manufacturing Co., Ltd Method and apparatus for amplifying a time difference
US8917132B2 (en) 2013-03-11 2014-12-23 Micron Technology, Inc. Apparatuses, methods, and circuits including a delay circuit
US8947144B2 (en) 2013-06-18 2015-02-03 Micron Technology, Inc. Apparatuses and methods for duty cycle adjustment
US9503066B2 (en) 2013-07-08 2016-11-22 Micron Technology, Inc. Apparatuses and methods for phase interpolating clock signals and for providing duty cycle corrected clock signals
US9256246B1 (en) * 2015-01-29 2016-02-09 Qualcomm Incorporated Clock skew compensation with adaptive body biasing in three-dimensional (3D) integrated circuits (ICs) (3DICs)
US9997210B2 (en) 2015-03-27 2018-06-12 Honeywell International Inc. Data register for radiation hard applications
US10234891B2 (en) * 2016-03-16 2019-03-19 Ricoh Company, Ltd. Semiconductor integrated circuit, and method for supplying clock signals in semiconductor integrated circuit
CN105897243B (zh) * 2016-03-31 2017-06-06 中国人民解放军国防科学技术大学 一种抗单粒子瞬态的时钟驱动电路
CN106788379B (zh) * 2016-11-29 2019-10-01 合肥工业大学 一种基于异构双模冗余的抗辐射加固锁存器
US10444786B2 (en) * 2018-01-26 2019-10-15 Mediatek Singapore Pte. Ltd. Mesh-based clock distribution for low power and high speed synchronized applications

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6362676B1 (en) * 1999-04-30 2002-03-26 Bae Systems Information And Electronic Systems Integration, Inc. Method and apparatus for a single event upset (SEU) tolerant clock splitter
AU4496600A (en) * 1999-04-30 2000-11-17 Lockheed Martin Corporation Method and apparatus for a single event upset (seu) tolerant clock splitter
US6668342B2 (en) * 2000-04-28 2003-12-23 Bae Systems Information And Electronic Systems Integration, Inc. Apparatus for a radiation hardened clock splitter
US6614257B2 (en) * 2000-05-12 2003-09-02 Bae Systems Information And Electronics Systems Integration, Inc. Logic architecture for single event upset immunity
US6327176B1 (en) * 2000-08-11 2001-12-04 Systems Integration Inc. Single event upset (SEU) hardened latch circuit
US20020063583A1 (en) * 2000-09-29 2002-05-30 Eaton Harry A. Single event upset immune logic family
FR2827443B1 (fr) * 2001-07-11 2004-03-26 St Microelectronics Sa Circuit de protection contre les pics de courant ou de tension, et circuit d'horloge utilisant un tel circuit de protection
US6573774B1 (en) * 2002-03-25 2003-06-03 Aeroflex Utmc Microelectronic Systems, Inc. Error correcting latch
JP3718687B2 (ja) * 2002-07-09 2005-11-24 独立行政法人 宇宙航空研究開発機構 インバータ、半導体論理回路、スタティックランダムアクセスメモリ、及びデータラッチ回路
US20040130373A1 (en) * 2003-01-08 2004-07-08 Roy Aninda K. Low-swing impedance controlled unity gain differential clock driver

Also Published As

Publication number Publication date
US7741877B2 (en) 2010-06-22
FR2898223A1 (fr) 2007-09-07
US20070216464A1 (en) 2007-09-20

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20131129