FR2863765A1 - Sequential access memory for e.g. printer, has output buffer, central unit and comparator for allowing memory to effectuate reading of plane memory while preventing data read in plane memory from being applied on input/output - Google Patents

Abstract

The memory (MEM) has a comparator, an output buffer, and a central unit preventing execution of read or write command if high order address of extended address is different from that of high order address allocated to the memory. The buffer, the unit and the comparator are arranged to allow the memory to effectuate reading of a plane memory (MA) while preventing data read in the memory (MA) from being applied on serial input/output. An independent claim is also included for a method of manufacturing a plane memory addressable with an extended address.

Description

1 2863765

  The present invention relates to serial memories on a silicon chip, and more particularly to the production of an extended memory plane by juxtaposition of a plurality of serial memories. .

  Among the memories integrated on a silicon chip, there are "parallel" type memories having parallel inputs and outputs, and "series" type memories, having a serial input / output. Serial memories, or serial memories, generally comprise only one data input / output allowing them to receive bit-by-bit read or write commands comprising an operation code, a reading or writing address. , and possibly a piece of data to write.

  For various technological reasons, the integrated silicon chip memories comprise an integrated memory plane of relatively limited size, in terms of memory space, generally less than the memory space required by certain applications.

  For example, computer peripherals such as printers require high-capacity memories to store large volumes of data. As a result, it is customary to group several silicon chips together to form extended memory planes formed by the juxtaposition of the integrated memory planes present in each of the memories. Such a grouping generally consists of a stack of silicon chips in the same housing or a stack of packages each comprising a silicon chip.

  An important objective in the realization of an extended memory array is to not drastically increase the number of interconnecting wires between, on the one hand, the various silicon chips forming the extended memory array and, on the other hand, on the other hand, the organ that exploits the memory plane, generally a microprocessor, a microcontroller, a DSP processor, etc.

  Another important goal is to ensure that an extended memory array formed by a given number of memories, is compatible with an extended memory array of the same size made with a lower number of memories. Indeed, with the rapid evolution of integration technologies on silicon, the size of the integrated silicon chip on-chip memory plans continues to increase, so that the number of individual memories necessary for the realization of a memory array extended size determined decreases. For example, a memory array of 2 MB (Megabytes) formed by four memories 512 KO (Kilobytes) each, can be achieved later with only two memories of 1024 KO each.

  Such compatibility means that the replacement of an extended memory array by another, comprising a smaller number of memories, must be possible with a minimum of software and hardware modifications, ideally that the replacement does not require any modification of the program. computer that uses the extended memory map. This implies that the overall "behavior" of the memory plane, that is to say its response to read or write commands accompanied by addresses of determined size, must not change.

  However, to date, the above objectives are not achieved and may even appear contradictory. To fix ideas, Figures 1 and 2A, 2B illustrate two conventional methods for performing an extended memory array, respectively with parallel-type memories and serial memories.

  In FIG. 1, four identical memories PMEM1, PMEM2 PMEM3, PMEM4 of parallel type are grouped together to obtain an extended memory plane. The memories each comprise an N-bit addressable integrated memory array (not shown). Each memory has N address entries AIo-AIN_1 in parallel, connected to the N least significant address son of an address bus ADB. The address bus comprises N + 2 address wires, necessary for addressing the extended memory array whose size is here four times that of the memory planes integrated in the silicon chips. The selection of each memory within the extended memory array is made by means of a selection input CS ("Chip Select") provided on each silicon chip. For this purpose, the two most significant wires of the address bus ADB are applied to an address decoder ADEC which supplies four selection wires CS1, CS2, CS3, CS4, each selection wire being connected to the input CS of a memory.

  This example shows that the realization of an extended memory array by means of parallel-input integrated circuits results in a reduction of the interconnection wires in order to be able to individually select the memories within the extended memory plane. In addition, the replacement of the extended memory array with a memory array of the same size, which would be realized with two integrated circuits having dual size integrated memory planes, would require a modification of the interconnection wires and the address decoder. In return, the extended memory plane has a software unitary character since it is possible to scan the addresses without worrying about what is the memory corresponding to the current address applied to the bus, the selection of memories being made automatically by the address decoder and the CS selection inputs. The extended memory plane would therefore be compatible at the software level with a same size memory array that would be 4 286 3765 made with two integrated circuits having individual memory cards of double size.

  FIG. 2A relates more specifically to the technical field of the invention and represents an extended memory array realized with four identical serial memories SMEM1, SMEM2, SMEM3, SMEM4, whose structure is shown schematically in FIG. 2B.

  Note that the use of serial memories is advantageous or almost mandatory in applications where control circuits are connected to a large number of elements. Thus, in some computer peripherals, there are microprocessor control circuits having hundreds of input / output ports despite a drastic reduction in interconnections through the widespread use of serial memories. In such applications, the use of serial memories is therefore almost indispensable because the number of ports to provide in the microprocessors would become unacceptable if parallel-type memories were used.

  Each SMEM memory comprises a serial I0 input / output, an IOCT input / output circuit, a CPU CPU, an N-bit ADEC address counter, and an N-bit addressable integrated memory array MA (Fig. 2B).

  The IOCT circuit is connected to the serial input / output IO and converts data received in serial form into parallel data, and vice versa. Each serial IO input / output is connected to a common DTW data wire (Fig. 2A) to all memories, which carries both commands, addresses, and data in serial form. Each memory also includes two IP1 identification entries, IPO whose potential is adjusted so as to assign each memory an identifier. For example, the two inputs IP1, IPO of the memory SMEM1 are brought to a supply voltage Vcc to form an identifier "11", the inputs IP1, IPO of the memory SMEM2 are carried respectively to the voltage Vcc and 2863765 the ground (GND) to form the identifier "10", the inputs IP1, IPO of the memory SMEM3 are grounded and the voltage Vcc to form the identifier "0,1" and the inputs IP1, IPO memory SMEM4 are grounded to form the identifier "00".

  The selection of each memory within the extended memory plane is. here made in software by sending to the memories distinctive commands of the type [OPCODE, I1, I0, AD] comprising an operation code OPCODE, two identification bits Il, IO and an AD address of N bits. The central unit of each memory executes the OPCODE operation codes present in the received commands if the identification bits Il, IO correspond to the identifier of the memory. In the case, for example, of a read command, the address counter ACNT stores the N address bits AN_1-Ao present in the command and applies them to the memory plane MA, while the central unit applies a signal of reading on the memory plane.

  In summary, the conventional method that has just been described consists in providing serial memories capable of "self-identifying" on receipt of a distinctive command. This method is advantageous as regards the number of electrical interconnections, since the juxtaposition of the memories does not lead to a reduction in the interconnection wires, the IP1, IPO identification inputs of the memories being locally polarized, using voltages (Vcc, GND) available in the vicinity of the silicon chips.

  However, the extended memory array obtained does not have a software unitary character, particularly as regards the execution of a continuous read command. Thus, a continuous reading of the extended memory plane first requires the sending to the first memory SMEM1 of a continuous read command of its integrated memory plane, of the type: [CODE (continuous_read), 1,1, AD0] comprising the operation code of the command, the identifier 1,1 of the memory SMEM1, and the address ADO where the continuous reading must be initialized in the integrated memory plane. Similar commands having appropriate identification bits must then be sent to the other memories, ie a total of four commands to read the entire memory array.

  In addition, the replacement of the four memories by two double-sized memories or even a single memory of quadruple size, requires a substantial modification of the program using the extended memory plane, because the commands to be sent are then no longer the same, both by their structure only by their number. Thus the continuous reading of a memory plane of the same size formed by two memories instead of four requires the sending of two continuous reading commands instead of four. The commands do not have the same structure and must include N + 1 address bits instead of N address bits.

  Yet another disadvantage of this method is that it is applicable only if the communication protocol of the serial bus provides for an identification field in the commands. However, some serial buses, including SPI buses of widespread use in industry, have communication protocols that do not provide for the insertion of an identifier in the commands.

  In conclusion, the realization of an extended memory array with serial memories without adding interconnection wires, leads to a complexification, a "specialization" of the communication protocol, which hinders the realization of a unitary memory plane to the plane. of the software, and therefore makes it impossible to obtain perfect compatibility between two extended memory planes comprising memories in different numbers.

  Thus, a general object of the present invention is to provide a method and a serial memory structure which make it possible to produce an extended memory array having a unitary character, that is to say behaving, seen from the outside. , as a single memory comprising a large memory plane.

  Another objective of the invention is that an extended memory plane has such a unitary character even when it is formed by the juxtaposition of serial memories having no integrated memory planes of the same size.

  Another object of the invention is to provide a method and a serial memory structure that allow the realization of an extended memory plane having a unitary character vis-à-vis a continuous read command of the extended memory array.

  Yet another object of the invention is to provide an extended memory array having a unitary character as regards the execution of particular commands for reading special registers which are generally provided in the serial memories, for example registers of state or identification records.

  To achieve these objectives, a general idea of the present invention is to apply to serial memories forming an extended memory plane, non-distinctive commands comprising an extended address covering the entire memory plane, and to assign to each memory a address of high weight within the extended memory plane so that each memory can itself determine if the command is intended for him or not.

  Another idea of the invention, relating more specifically to the execution of a continuous read command of the memory plane, is to provide, in each memory, an extended address counter for storing the entire extended address. present in the orders received. Thus, each memory is able to receive commands whose address field exceeds the size of its own integrated memory array, and is able to increment its address counter to a wider range than addressing. of its own memory array, so that multiple memories can work together to simulate the operation of a single memory.

  Yet another idea of the invention, relating more specifically to the realization of an extended unitary memory plane read and write, is to provide, in each memory, an availability / occupation contact and to interconnect the contacts availability / occupying all memories forming the extended memory plane so that each memory can know if one of the other memories is occupied by a write operation of its memory plane. Thus, when a memory performs a write operation of its memory plane, it carries the determined potential contact availability / occupation and prevents other memories to respond to a read command. The set of memories thus behaves like a single memory, because a single memory can not be simultaneously available for reading and writing.

  Yet another idea of the invention, relating more specifically to reading special registers in an extended memory plane, is to designate a master memory and the other slave memories, and to ensure that only a master memory can execute a command. reading a special register.

  More particularly, at least one of the above-mentioned objectives is achieved by the provision of a method for producing an extended memory array comprising a plurality of integrated serial memories on silicon chips, each memory comprising a serial input / output and an integrated memory array addressable in N bits, N being different for each integrated memory, the extended memory array being addressable by means of an extended address comprising N least significant bits and K most significant bits, the inputs / outputs series of memories being interconnected, the method comprising the steps of providing, in each memory, an availability / occupancy contact, providing, in each memory, means for forcing the availability / occupancy contact at a given electrical potential, during an operation erasing or programming of the integrated memory plane, interconnecting the contacts of disp enable / occupy the memories, and prevent the execution of a read or write command in each memory when the electrical potential of the availability / occupation contact has the determined potential.

  According to one embodiment, the method comprises the steps of providing, in each memory, means for storing a high-order address allocated to the memory within the extended memory plane, allocating each memory a high-order address, applying to the memories of the read or write commands comprising an extended address, and to prevent the execution of a read or write command in each memory when the K most significant address bits of the extended address are different from the the most important address assigned to the memory.

  According to one embodiment, the step of preventing execution of a read command in a memory includes a step of preventing read data in the memory integrated memory plane from being provided on the input / output. out of memory.

  According to one embodiment, each memory comprises an output buffer circuit for providing on the serial input / output of the memory data read in the integrated memory plane, and the step of preventing data read in the integrated memory plane. to be provided on the input / output of the memory includes a step of providing a blocking signal to the output buffer circuit of the memory.

  According to an embodiment aimed at producing an extended memory array that can respond to a continuous read command of the memory plane, the method comprises the steps of providing, in each memory, an extended address counter of N + K bits. for storing an extended address, applying to the memories an extended read command having an extended read start address, and continuously incrementing or decrementing the extended address counter of each memory, including when the K address address bits are different from the high-order address assigned to the memory until the execution of the continuous read command is stopped.

  According to one embodiment, during execution of a continuous read command the integrated memory plane of each memory is read continuously even when the K most significant address bits are different from the most significant address assigned to Memory.

  According to one embodiment, during the execution of a continuous read command the integrated memory plane of each memory is read only when the K most significant address bits are identical to the most significant address assigned to Memory.

  According to one embodiment, the method comprises a step of providing, in each memory, means for storing information on the number K of high-order bits that can comprise at most the extended address, K being a variable between 0 and Kmax, Kmax being a non-zero integer delimiting the maximum size of the extended address.

  According to an embodiment aiming at the realization of an extended memory plane of variable size addressable by means of an extended address which can go from N bits to N + Kmax bits, without modifying the architecture of the memories 2863765 composing the extended memory plane , the method comprises the steps of providing, in each memory, an extended address counter comprising N + Kmax counting cells of one bit each, providing, in each memory, means for storing Kmax reference bits, and allocating to each memory at least K reference bits forming a high-order address, K being between 0 and Kmax.

  According to one embodiment, the method comprises a step of deactivating count cells of the extended address counter as a function of the information on the number K so that the counter comprises only N + K active counting cells.

  According to one embodiment, the method comprises a step of comparing only K reference bits with K most significant address bits present in the counter, without taking into account the other address bits present in the counter.

  According to one embodiment, the information on the number K is provided to the memories in the form of a coded binary number giving an indication of the size of the extended memory array.

  According to one embodiment, the method comprises a step consisting in providing, in each memory, specific contacts, and a step of configuring the most significant address assigned to the memory by applying specific electrical potentials to the specific contacts.

  The present invention also relates to a memory on a silicon chip, comprising a serial input / output and an N-bit addressable integrated memory array, an availability / occupation contact, means for forcing the availability / occupation contact at a determined electrical potential. during an erasure or programming operation of the integrated memory plane, and release the electrical potential of the availability / occupation contact outside the erasure or programming operations of the integrated memory plane, and means for preventing the executing a command for reading or writing the integrated memory plane when the electric potential of the availability / occupation contact has the determined potential, including when the memory is not performing an erase operation or programming of the integrated memory plane.

  According to one embodiment, the memory comprises means for storing a high-order address assigned to the memory within an addressable extended memory array by means of an extended address comprising N least significant bits and K most significant bits. , means for storing an extended address present in a command applied to the serial input / output of the memory, means for comparing the K most significant address bits with the most significant address assigned to the memory , and means for preventing execution of a read or write command of the integrated memory array when the K most significant address bits present in the read command are different from the high-order address assigned to Memory.

  According to one embodiment, the memory comprises an output buffer circuit for supplying, on the serial input / output of the memory, data read in the integrated memory plane, and a comparator for providing a signal for blocking the output buffer if the K most significant address bits are different from the most significant address assigned to the memory.

  According to one embodiment, the memory includes a time shift circuit for delaying the application of the blocking signal to the output buffer circuit if, at the moment when the blocking signal passes to an active value, the buffer circuit of output is supplying on the serial input / output the bits of data read in the integrated memory array before the blocking signal passes to the active value.

  According to one embodiment, the memory comprises an extended address counter of N + K bits, for storing an extended address received on the serial input / output of the memory, and a central unit for executing a read command. continuous operation of the extended memory array by incrementing or continuously decreasing the extended address counter including when the K most significant address bits are different from the most significant address assigned to the memory, until the end of the execution of the continuous read command.

  According to one embodiment, the central unit is arranged to read continuously the integrated memory plane during the execution of a continuous read command, even when the K most significant address bits are different from the address of heavy weight attributed to memory.

  According to one embodiment, during the execution of a continuous read command, the central unit is arranged to read the integrated memory plane only when the K most significant address bits are identical to the most significant address. attributed to memory.

  According to one embodiment, the memory comprises means for storing information on the number K of high-order bits that comprise the extended address, K being a variable between 0 and Kmax, Kmax being a non-zero integer delimiting the size maximum of the extended address, an extended address counter comprising N + Kmax counting cells of one bit each, and means for storing Kmax reference bits among which K reference bits represent an address of high weight attributed to the plane integrated memory within the extended memory plane.

  According to one embodiment, the memory comprises a configuration register for memorizing Kmax flags corresponding by their number and their rank to Kmax high-order bits that can contain at most the extended address, each flag having a logical value 14 2863765 determined if the most significant bit of corresponding rank is present in the extended address, the number of flags having the determined logical value defining the number K of most significant bits present in the extended address.

  According to one embodiment, the memory comprises a configuration register for storing a coded bit number giving an indication of the size of the extended memory array, and a decoding circuit providing, from the coded binary number, Kmax flags corresponding by their number. and their rank to the most significant bits that can be maximally extended address, each flag having a logic value determined if the most significant bit of corresponding rank is present in an extended address, the number of flags having the logical value determined defining the number K of most significant bits present in the extended address.

  According to one embodiment, the memory comprises means for deactivating count cells of the extended address counter as a function of the information on the number K, so that the counter comprises only N + K active counting cells.

  According to one embodiment, the means for comparing the K most-significant address bits with the K reference bits comprise a comparator comprising Kmax inputs and means for inhibiting inputs of the comparator according to the information on the number K , so that the comparator comprises only K active inputs.

  According to one embodiment, the memory comprises specific contacts allowing a hardware configuration of the high-order address assigned to the memory, by applying specific electrical potentials to the specific contacts.

  The present invention also relates to an extended memory plane comprising a combination of at least two memories according to the invention, in which the 2863765 serial inputs / outputs of each memory are interconnected and the availability / occupation contacts of each memory are interconnected.

  These and other objects, features and advantages of the present invention will be set out in more detail in the following description of a memory according to the invention, given in a non-limiting manner in relation to the attached figures among which: FIG. 1 previously described represents an extended memory plane comprising parallel-type memories, - Figures 2A, 2B previously described respectively represent an extended memory array comprising conventional memory series and the structure of these series memories, - Figure 3 represents an extended memory array comprising serial memories according to the invention, and schematically represents the structure of one of these series memories, - Figure 4 represents in the form of blocks an embodiment of a serial memory according to the invention, - Figure 5A represents a first embodiment of an extended address counter represented in block form in FIG. Fig. 5B shows a first exemplary embodiment of a comparator shown as a block in Fig. 4; Fig. 6A shows a second exemplary embodiment of the extended address counter shown as a block in Fig. 4B. FIG. 6B shows a second exemplary embodiment of the comparator shown in block form in FIG. 4, FIGS. 7A to 7J are timing diagrams showing counting signals and data signals and illustrating the operation of a plan. extended memory 16 2863765 according to the invention in response to a continuous read command.

  FIG. 3 represents an extended memory array comprising four memory memories MEM1, MEM2, MEM3, MEM4 according to the invention, integrated on silicon chips. Each memory conventionally comprises an IOP (In / Out Pad) input / output contact, an IOCT input / output circuit ensuring the conversion of the data received in serial form into parallel data, and vice versa, an addressable integrated memory array MA. under N bits, and a cabled or microprocessor CPU CPU. It will be assumed here and in what follows, for the sake of simplicity of the disclosure, that the integrated memory planes of each memory are identical and that the number N of address bits necessary for the reading or writing of a datum in each of the integrated memory planes is identical for each memory.

  Memories MEM1 to MEM4 have their respective IOP contacts connected to a common DTW data wire. This data wire belongs to a serial data bus which may include control wires such as clock wires, power wires, ground wires ... which are not shown here.

  According to the invention, the read or write commands sent to the memories via the DTW wire comprise an OPCODE operation code, an EAD address, and possibly DT data (for the data writing commands), ie: [OPCODE , EAD] (read) or [OPCODE, EAD, DT] (write) This command structure differs from a classical command in that the EAD address included therein is an extended address including an N + K number of address bits which is greater than the number N of 17 2863765 address bits required for the addressing of the integrated memory array of each memory, N + K being at least equal to the number of address bits required for addressing extended memory plan as a whole.

  The extended address EAD thus comprises N low order address bits AN_1-Ao forming a low dot address ADL intended to select a memory area in one of the integrated memory planes, generally a binary word, and K bits of most significant address AN + K-1, AN + K-2, ... AN forming a high-order address ADH making it possible to designate one of the memories.

  In the example shown, K is equal to 2 because the extended memory plane comprises four serial memories. The commands thus comprise addresses of N + 2 bits.

  The ADL address comprises low order address bits AN_1-Ao and the ADH address comprises 2 most significant address bits AN + 1, AN.

  According to the invention, each memory comprises an extended address counter EACNT of N + K bits, here N + 2 bits, a comparator COMP having twice K inputs (2 * K), here 4 inputs, and a storage means a RADH reference high-order address assigned to the memory, which represents the address of the memory within the extended memory plane, more precisely the address of the integrated memory plane of the memory within the extended memory array.

  This storage means is for example an indexing register IDXREG comprising K reference bits RK-1, RK-2, ... Ro, here two bits R1, RO, representing the RADH address. For example, the IDXREG register of the memory MEM1 comprises the reference bits "00", the register IDXREG of the memory MEM2 comprises the reference bits "01", the register IDXREG of the memory MEM3 comprises the reference bits "10" and the IDXREG register of the memory MEM4 comprises the reference bits "11" 18 2863765 When a command comprising an extended address is sent on the data wire DTW, each memory receives the command and applies the operation code OPCODE to its central unit CPU, and stores the extended address EAD in its extended address counter EACNT. The address ADL formed by the first N bits AN_1-Ao of the address EAD stored by the counter, is applied to the memory plane MA while the address ADH, formed by the K most significant address bits of the address EAD, here the bits AN + 1, AN, is applied on K first inputs of the comparator COMP, here two inputs. The latter receives on K other inputs, here two inputs, the reference bits RK_1-Ro, here the bits R1, RO.

  The output of the comparator provides an ADMATCH signal which is for example at 1 when the most significant bits of the extended address received are identical to the most significant address assigned to the memory, that is to say identical to the bits. reference. The ADMATCH signal is used to prevent memories that are not affected by the extended address from executing the received command, whether it is a read command or a write command (when the plans integrated memory are writable).

  This non-execution of a command is obtained by blocking the execution of the operation code by the central unit UC, at least as regards the write commands.

  However, the non-execution of a command can also be obtained, as regards the read commands, by leaving the central unit of each memory to execute the read operation and by preventing the read data from being applied to the IOP serial input / output contact. This method is, according to the invention, the preferred solution for ensuring a continuous reading of the extended memory array, since it allows the CPU of each memory to continuously read its integrated memory array, and to provide the data read. when the ADMATCH signal goes to 1.

  According to another aspect of the invention, each memory comprises an availability / occupation contact RBP (Ready / Busy Pad) and a circuit RBCT RBP contact management. The RBP contacts of the memories are interconnected and are carried by default to a high potential, here a supply voltage Vcc, via a high-value resistor RPU high value. Resistance RPU is here external to the memories, but can also be internal to each memory, that is to say, be integrated on the silicon chips.

  The RBCT circuit receives an Internal Write In Progress (IWIP) signal sent by the central unit, and supplies the central unit with an EWIP (External Write In Progress) signal. The IWIP signal is set by the central unit during an operation of writing the integrated memory plane (deletion and / or programming). When the IWIP signal goes to 1, the RBCT circuit forces the RBP contact to a low potential, for example the ground potential. Furthermore, the circuit RBCT sets the signal EWIP when it detects the low potential, here the ground potential, on the contact RBP ,, including when the signal IWIP is at 0. The fact that the signal EWIP is at 1 while the IWIP signal is 0 means that the ground potential on the RBP contact is imposed by another memory. The signal EWIP thus enables the central unit to know that a memory of the extended memory array is performing a write operation in the memory plane that is specific to it. The central unit then refuses to execute a read or write command that may possibly be received on the IOP input / output contact, as long as the current writing is not completed.

  Thus, when a memory executes a write operation, the other memories are informed by the change to 0 of their contact RBP, which causes the passage 2863765 to 1 of the signal EWIP. The CPUs of these memories then refuse to execute read or write commands. This aspect of the invention makes it possible to confer on the memory plane a unitary character in writing, since the latter then behaves from the outside as a single memory. Indeed, a single memory can not simultaneously perform an operation of writing and reading of its memory plane. Similarly, a single memory can not simultaneously execute two write commands in two different areas of its memory plane.

  A detailed embodiment of a serial memory embodying the various aspects of the invention mentioned above, as well as others which will be described later, will now be described with reference to FIG.

  General aspects of the memory The memory MEM represented in FIG. 4 comprises the elements described above, namely: the IOP contact forming the serial input / output of the memory, the availability / occupation contact RBP, the circuit IOCT input / output circuit, - the RBCT contact management circuit RBP, - the central processing unit UC, - the extended address counter EACNT, - the addressable MA memory board under N bits, - the IDXREG indexing register and the comparator COMP.

  The memory also comprises: an internal data bus 5 of parallel type, a GNDP ground contact, a clock contact CKP receiving a clock signal CKO, a clock circuit CKGEN, a circuit of FIG. synchronization SYNCCT, and - two special registers, here a status register STREG (Statutes Register) and an identification register IDREG.

  The input / output circuit includes an INBUF input buffer having an input and a serial output, an INSREG shift register having a serial input and a parallel output, an OUTBUF output buffer having an input and a serial output , and an OUTSREG shift register having a parallel input and a serial output. The INBUF buffer has its input connected to the IOP contact and its serial output connected to the serial input of the INSREG register, the output of which is connected to the data bus 5. The OUTSREG register has its input connected to the data bus 5. Its output . is connected to the input of the buffer OUTBUF whose output is connected to the contact IOP.

  The memory array MA conventionally comprises an array of memory cells FGTMTX, for example a matrix of floating gate transistors, an XYDEC line and column decoder, a programming circuit LATCHCT comprising high voltage locks whose inputs are connected to the bus , and a SENSECT read circuit comprising read amplifiers whose outputs are connected to the bus 5.

  The special STREG and IDREG registers, which are in themselves conventional, are accessible for reading and writing via the bus of 5. The IDREG register comprises, for example, a unique identifier ID of the silicon chip. The state register STREG comprises, for example, bits P0, P1,... Pi for write protection of fractions (parts) of the memory plane, a WEN bit for general write protection (Write Enable), and a bit WP representative of the current value of the EWIP signal, and generally any data useful for the management of a memory known to those skilled in the art.

  The central unit controls the various elements of the memory, the control links between the central unit and these various elements being represented schematically by a dotted line. The central unit controls in particular the various read and / or write registers, read and write control the memory plane MA and its 22 2863765 constituent elements, controls the extended address counter EACNT for the loading of the extended address and / or for incrementing or decrementing the counter, when executing continuous read commands, controls the loading of shift registers, etc.

  The clock generator CKGEN provides a clock signal CK1 which is a sub-multiple of the signal CKO. The signal CKO is a bit clock signal while the signal CK1 is a word clock signal, whose frequency is equal to the frequency of the clock signal CKO divided by the number of bits that comprise the binary words present in the memory map. The clock signal CK1 speeds the operations relating to binary words, in particular of reading or writing of the memory plane, of incrementation or decrementation of the address counter EACNT, of loading a binary word in the register OUTSREG or reading a binary word in the register INSREG, etc. The clock signal CKO cadence operations related to the transmission or reception of bits in serial form, including the shift of bits in the shift registers OUTSREG , INSREG and the timing of buffers OUTBUF, INBUF.

  Aspects of the invention relating to the execution of commands comprising an extended address Execution of commands comprising an extended address The operation code OPCODE and the extended addresses EAD received in serial form on the IOP contact are transformed by the register INSREG in parallel data applied on the bus 5, and are respectively applied to an input of the central unit and an input of the extended address counter EACNT. When an EAD address has been registered in the EACNT address counter, it provides the first N address bits AN_1-Ao (address ADL) to the XYDEC decoder, and supplies the high-order address bits 23 2863765. AN + 2, AN + 1, AN (ADH address) at first inputs of the comparator COMP.

  The indexing register IDXREG here comprises three reference bits R2, R1, RO which form the RADH reference high-order address assigned to the memory within the extended memory plane. This extended memory array is thus addressable at most under N + 3 bits (K = 3), and its size can not be greater here than 8 times the size of the integrated memory plane MA. An extended address thus comprises here, at the most, 3 most significant address bits AN + 2, AN + 1, AN- The bits R2, R1, RO are applied to second inputs of the comparator COMP whose output provides the signal ADMATCH described above.

  The ADMATCH signal is applied to the CPU to block the execution of write commands. The signal ADMATCH is also applied to an input of a gate 10 of NO OR two-input type, whose output provides a signal SHZ (Set High Z). The signal SHZ is applied to a control input of the output buffer OUTBUF via the synchronization circuit SYNCCT. The OUTBUF output buffer is a tri-state buffer that can have an output state of 0 (ground), 1 (Vcc), or high impedance (HZ). When the SHZ signal is 1, the OUTBUF buffer sets its high impedance output. The synchronization circuit SYNCCT is generally transparent for the signal SHZ, except in a particular case described below.

  Thus, when the most significant bits present in an extended address received in a command do not match with the reference bits, the ADMATCH signal goes to 0 and the SHZ signal goes to 1, which switches the output of the OUTBUF buffer into the high impedance state. The data applied to the serial input of the buffer is therefore no longer transmitted on the IOP input / output contact, which makes it possible not to execute a read command. Of course, the CPU is, in turn, configured to perform the read command, in accordance with the preferred method of the invention for not executing a read command, whereby the data is read but blocked in exit. The SYNCCT circuit becomes non-transparent with respect to the signal SHZ when a LOAD signal for loading a binary word is applied to the OUTSREG shift register by the central unit. From this moment, the SYNCCT circuit counts a number of clock cycles CKO corresponding to the number of bits present in a binary word, ie a clock cycle CK1, and becomes transparent again when the transmission cycle of the binary word is completed. Thus, if the signal SHZ goes to 1 while a binary word is being sent bit by bit on the IOP output contact, the blocking (high impedance setting) of the output buffer occurs only after that the entire word has been sent.

  The aspects of the invention relating to the reading protection of the extended memory array during a write operation will now be described.

  Protection of the Extended Memory Plane during Writing The RBCT circuit comprises a switch transistor T1, here of NMOS type, an OR type gate and an inverting gate 21. The drain and source terminals of the transistor T 1 are respectively connected to the RBP contact. and ground, while the transistor gate is driven by the IWIP signal provided by the CPU. The gate 21 is connected as input to the RBP contact. The gate 20 receives on one input the signal IWIP, on another input the output of the gate 21, and its output provides the signal EWIP.

  As indicated above, the IWIP signal is set when the central unit performs an erase and / or programming operation in the memory plane.

  The RBP contact, which is biased to the voltage Vcc by the RPU resistor described above, is then forced to 0 2863765 (ground) by the transistor T 1. On the other hand, if the RBP contact is forced to 0 by another memory (the RBP contacts being interconnected), the EWIP signal goes to 1 even if the IWIP signal is 0. Thus, when IWIP = O and EWIP = 1, The CPU knows that another memory is being written and refuses to execute a read or write command for the reasons explained above.

  Aspects of the invention will now be described to provide a serial memory that is configurable and can be incorporated into an extended memory array of variable size.

  Aspects relating to obtaining a configurable memory The memory comprises a CNFREG configuration register and a CNFDEC configuration decoder. The CNFREG register includes information on the size of the extended memory plane in which the memory is incorporated. This information is here the number K which is coded in binary by means of two bits K1, K0, and can vary between K = 0 and K = Kmax = 3. The size of the extended memory array is thus equal to 2K times the size of the integrated memory array MA, ie a number of memory points (binary words) equal to 2K * 2N or 2N + K The output of the CNFREG register is applied to the configuration decoder CNFDEC which provides, from K, three flags F2, F1, FO indicating the number of high-order address bits that includes the extended address of the extended memory array.

  Note that the flags F2, F1, FO can also be directly registered in the CNFREG register, the storage of the K parameter in binary form being provided here to reduce the size of the CNFREG register.

  The relationship between the number K and the flags F2, F1, FO is described in Table 1 below. The decimal value of K is described by the first column of the table. The binary value of K (bits K1, K0) is described by the second column. The size of the extended memory array is described by the third column of the table. The fourth, fifth and sixth columns respectively describe the values of the flags F2, F1, FO for each value of K. The seventh column mentions the most significant address bits (address bits beyond the first N bits) that includes the extended address, for each value of K. The last column describes the maximum value MSBmax of the most significant address in the extended memory plane, for each value of K. It appears in table 1 that a flag F2 , F1, FO is at 1 when the corresponding high-order bit is used in the extended address.

  Finally, K is a programmable variable that can vary from 0 to Kmax, with here Kmax = 3, and the configuration register makes it possible to incorporate the memory into an extended memory array comprising 2 (K = 1), 4 (K = 2) or 8 (K = 3) memories having an N-bit addressable integrated memory array, or to incorporate it into a composite extended memory array (composed of memories of different sizes) addressable under N + K bits.

  It also appears in Table 1 that the FO flag is at 0 only when K is equal to 0. In other words, the fact that the FO flag is 0 means that the memory is not integrated in a memory array extended, and that there is no high-order address. The memory then operates in "conventional" mode, that is to say by executing all the commands without its operation being dependent on the comparison of the most significant address bits and the reference bits R2, R1, RO

Table 1

  K (decimal) K1 KO 2K * 2N F2 Fl FO MSB MSBmax 0 00 2N 0 0 0 - - 1 01 2 * 2N 0 0 1 YEAR 1 2 10 4 * 2N 0 1 1 YEAR + 1 YEAR 11 3 11 82 '' 1 1 1 AN + 2 AN + 1 AN 111 27 2863765 In order to inhibit the comparison mechanism of the most significant addresses and the reference bits when F0 = 0, the FO flag is applied to the input of an inverting gate 11 whose output provides an ADMATCH signal. The signal ADMATCH 'is applied to the second input of the gate 10. Thus, when FO = O, ADMATCH' is at 1 is the signal SHZ is forced to 0, so that the buffer OUTBUF can not be put in the high impedance state.

  On the other hand, in order to adapt the operation of the memory to the number K of high-order bits that comprises the extended addressing, the extended address counter and / or the comparator have a variable configuration which is a function of K. FIGS. 5A and 5B respectively represent a first embodiment EACNT1 of the extended address counter and a first embodiment COMP1 of the comparator. According to this first embodiment of these elements, the address counter comprises a variable number of active counting cells, which is a function of K, whereas the comparator comprises a number of comparison entries which is fixed and equal to Kmax. .

  More particularly, the address counter EACNT1 comprises a basic counting block BCNT comprising N counting cells of 1 bit each (not shown) and three additional counting cells C1, C2, C3 of 1 bit each, arranged at the same time. outside of the base count block. The various counting cells are clocked by the clock signal CK1.

  The basic counting block BCNT receives as input the address bits AN_1Ao, ie the address ADL, and provides address bits AN_l '-Ao'. The address bits AN_1 '-Ao' are equal to the address bits received at the input in the case of a read or write command with a fixed address, or form an incremented or decremented address at the rhythm of the signal of clock CK1 in the case of an order 28 2863765 of continuous reading. The count block BCNT provides a sum carry-over bit C (Carry) when it reaches the overflow value (all address bits at 1) and when it returns to 0.

  The counting cells C1, C2, C3 each comprise an input In to receive a high-order address bit, respectively AN, AN + 1, AN + 2, together forming the address ADH, and an output providing bits of address AN ', AN + 1', AN-F21, respectively. Each counting cell C1, C2, C3 comprises a CIN input to receive the C bit of the previous rank and a COUT output to supply the C bit of the next rank. The input CIN of the cell C1 receives the bit C supplied by the block BCNT via an AND gate whose other input receives the flag F0. The input CIN of the cell C2 receives the bit C supplied by the cell C1 via an AND gate whose other input receives the F1 flag. The input CIN of the cell C3 receives the bit C supplied by the cell C2 via an AND gate whose other input receives the flag F2. When the flags F0, F1, F2 are at 1 (K = Kmax = 3) the three cells are active and connected in cascade to the BCNT block. The address bits AN ', AN + 1', AN + 2 'are then equal to the address bits received at the input in the case of a command to read or write at fixed address, or form a most significant address. incremented or decremented at the rate of the clock signal CK1 in the case of a continuous read command. When the flag F2 is at 0 and the flags F1, FO at 1 (K = 2), the cell C3 is disconnected from the rest of the counter by the corresponding AND gate. Its output remains at 0 during a continuous read cycle and is not involved in determining the ADMATCH signal provided by the comparator. When the flags F2, F1 are at 0 and the flag FO at 1 (K = 1), the cells C3, C2 are disconnected from the remainder of the address counter and their outputs remain at 0 during a continuous read cycle 29 2863765 and do not interfere in the determination of the ADMATCH signal provided by the comparator. Finally, when the flags FO to F2 are all 0, the three cells are disconnected and the address counter includes only the base counter BCNT, which is equivalent to an address counter of a conventional memory. The memory operates in this case in "classical" mode: the signal ADMATCH 'is at 1 and forces at 0 the signal SHZ, as described above.

  The comparator COMP1 shown in FIG. 5B comprises doors 30, 31, 32 of the EXCLUSIVE OR type and a gate 33 of the NON OR type. Gate 30 receives as input the reference bit RO and the most significant address bit AN '. The gate 31 receives as input the reference bit R1 and the most significant address bit AN + 1 '. The gate 32 receives as input the reference bit R2 and the high-order address bit AN + 21E. The gate 33 has three inputs respectively connected to the outputs of the gates 30, 31, 32, and supplies the signal ADMATCH.

  Figs. 6A and 6B respectively show a second embodiment EACNT2 of the extended address counter and a second embodiment COMP2 of the comparator. According to this second embodiment, the address counter EACNT2 comprises an invariable number N + Kmax of active counting cells. The counter EACNT2 is the equivalent of the counter EACNT1 in which the AND gates for filtering the sum transfer bits C are deleted and replaced by direct connections.

  The comparator COMP2 has the same doors as the comparator COMP1 described above, designated by the same references. It further comprises ET type doors 34, 35, 36. The gate 34 receives as input the output of the gate 30 and the flag F0. Its output is applied to the first input of the gate 33. The gate 35 receives as input the output of the gate 31 and the F1 flag. Its output is applied to the second input of the gate 33. The gate 36 receives as input the output of the gate 32 2863765 and the flag F2. Its output is applied to the third input of the gate 33. Thus, the inputs of the comparator are inhibited by the flags F0, F1, F2 when they are at 0. More particularly, the inputs of the comparator corresponding to the inputs of the gate 30 are inhibited when the flag FO is at 0. The inputs of the comparator corresponding to the inputs of the doors 30, 31 are inhibited when the flags F0, F1 are at 0. Finally, all the inputs of the comparator are inhibited when all the flags F0, F1 , F2 are at 0, 1 ADMATCH signal is then forced to 1. This embodiment of the comparator makes it possible to delete the gates 10, 11, the signal ADMATCH can be directly applied to the SYNCCT circuit.

  Finally, the serial memory according to the invention has a programmable configuration enabling it to function as a conventional serial memory, or to be integrated in an extended memory array whose size is 2 times, 4 times or 8 times the size of the memory. his own memory plan.

  The programming of the configuration register CNFREG is preferably done by software, by means of a specific command that the central unit executes. This programming can be provided when all the memories are interconnected, because the value of K is the same for all the memories. However, programming of the IDXREG indexing register must be done before the interconnection of the memories, since each memory must receive an individual high-order address and the execution of an individual IDXREG register write command can not be performed. be considered until a * most significant address is registered. The IDXREG register can for example be programmed during the manufacture of silicon chips, which are then classified in batches, each batch corresponding to a high-order address. This solution, however, goes against the desired flexibility.

  According to the invention, a more advantageous solution consists in providing electrical contacts, here three contacts IDXPO, IDXP1, IDXP2 connected to inputs of the register IDXREG respectively corresponding to the reference bits RO, R1, R2. The contacts IDXPO, IDXP1, IDXP2 are connected to the ground by a low resistance RPD of strong value, individual or collective. When the silicon chip is arranged in a housing, each contact IDXPO, IDXP1, IDXP2 is connected to the voltage Vcc to program to 1 of the corresponding reference bit, or is left disconnected to program to 0 the corresponding reference bit. If none of the three contacts IDXPO, IDXP1, IDXP2 are connected to the voltage Vcc, all the reference bits are at 0 and the memory operates in "classical" mode. Various improvements of this static programming principle by wiring may be provided by those skilled in the art. In particular, there can be provided a control circuit for disconnecting the resistance RPD contacts IDXPO, IDXP1, IDXP2 when the IDXREG register is programmed, in order to prevent a leakage current is continuously circulating in the resistor RPD.

  Table 2 below describes the various high-order addresses that can be loaded in the register IDXREG as a function of the value of K (K1 KO) loaded in the register CNFREG.

Table 2

CNFREG IDXREG

  (Ki KO) (R2 R1 RO) 00 000 01 000 or 001 from 000 to 011 11 from 000 to 111 An aspect of the invention relating to the reading of one of the special registers, the purpose of the invention will now be described. The invention being here to ensure that, when a read command of such a register is applied to a set of memories, a single memory processes the command and provides on the serial bus the contents of the special register, so to avoid collisions of answers.

  Aspects relating to the execution of special register read commands The memory includes a master memory decoder MSTDEC which provides a MASTER signal (Fig. 6). When the MASTER signal is at 1, the memory is considered as the master memory within the extended memory array while the other memories are considered as slaves. Since only one memory can be master within the same extended memory plane, the MASTER signal must be 1 for a single memory. According to the invention, one solution among others is to confer the status of master memory to the one which receives in the register IDXREG a most significant address which is the strongest high-order address of the extended memory plane. For this purpose, the decoder MSTDEC receives as input the reference bits RO, R1, R2 and the bits K1, K0 forming the number K. Table 3 below describes the logic function of producing the MASTER signal executed by the decoder MSTDEC . It appears that for each value of K, the signal MASTER is at 1 when the most significant address R2 R1 RO corresponds to the highest possible value in the extended memory plane. When K = 0, the MASTER signal is always at 1 since the memory operates in the "classical" mode.

  According to the invention, the central unit UC is configured to execute a read command of one of the special registers STREG, IDREG only if the signal MASTER is at 1. The register is then transferred to the IOP output of the memory via the internal data bus 5 and the IOCT circuit. Thus, from the outside, the extended memory array has a unitary character with respect to the reading of the special registers since it is always the master memory that responds to the read commands. In other words, everything happens as if the extended memory plane had only one copy of each of the special registers, those of the slave memories never being read and remaining inaccessible from the outside.

Table 3

  K (decimal) CNFREG IDXREG MASTER (Ki KO) (R2 R1 RO) 0 00 000 1 1 01 001 1 1 01 000 0 2 10 011 1 2 10 from 000 to 010 0 3 11 111 1 3 11 from 000 to 110 0 Special registers of the slave memories, although they are not accessible in reading, must nevertheless be able to be programmed because they can act on the operation of these memories. Thus, according to the invention, the write protection bits PO at pi are assigned to the write protection of fractions of the extended memory array rather than the protection of fractions of the integrated memory plane of the memory in which they are stored. These bits therefore relate to each of the memories, in particular those which are part, if necessary, of the fraction of the extended memory array to be protected in writing. Also, the WEN bit is used as a collective bit assigned to the general write protection of the extended memory plane, and not to the write protection of a specific memory.

  Thus, and unlike the read commands, special register write commands are executed by all memories, masters or slaves. The special registers thus contain strictly the same value in each of the memories of the expanded memory array and form the equivalent of a single collective register.

  The execution of a continuous play command will now be described in more detail. Such a command is in itself of a conventional structure but has an extended address EADO start reading, an address of N + K bits: [CODE (continuous reading), EAD0] When such a continuous read command is received the respective CPUs of the memories continuously incrementally or continuously decrement their extended address counters, and each provides the requested data when the high bits of the extended address counter become equal to the reference bits present in the address register. indexing. Since the respective extended address counters of the various memories comprise at each instant the same extended address value, the memories are automatically relayed to provide on the serial bus the contents of their respective integrated memory planes, which corresponds, given the external, to a single memory having a large integrated memory plan that would perform a continuous read operation of its memory plane.

  To fix the ideas, FIGS. 7A to 7J illustrate the execution of a continuous read command of the extended memory plane represented in FIG. 3, formed by the memories MEM1 to MEM4. FIGS. 7A, 7C, 7E, 7G represent count values CNTVAL1, CNTVAL2, CNTVAL3, CNTVAL4 formed by the first N bits of the extended address counter of the memories MEM1, MEM2, MEM3, MEM4, respectively, or the ADL addresses. . FIGS. 7A, 7C, 7E, 7G also represent the values of the signals ADMATCH1, ADMATCH2, ADMATCH3, ADMATCH4 at the output of the respective comparators of the memories MEM1, 2863765 MEM2, MEM3, MEM4. FIGS. 7B, 7D, 7F, 7H represent the data DTREAD1, DTREAD2, DTREAD3, DTREAD4 read in the integrated memory banks MEM1, MEM2, MEM3, MEM4, respectively. FIG. 7I represents the most significant count value formed by the two most significant bits AN + 1, AN (because here K = 2) present in the extended address counter of each memory, namely the address ADH. Figure 7J shows the DTOUT data that is provided by the integrated memory array. It is assumed here that the continuous read starts at the zero address of the extended memory array, and that the memory MEM1 is the one with the lowest high-order address, ie AN + 1 AN = 00.

  During continuous reading, the low-count values CNTVAL1, CNTVAL2, CNTVAL3, CNTVAL4 perform several count cycles, each time returning to zero (Fig. 7A, 7C, 7E, 7G) while the count value of weight increases one unit each cycle. At each cycle, the central units of the memories read all of their respective memory planes, but these data are output only when the signal ADMATCH is 1. Thus, the data provided during the first counting cycle are those which are read by the memory MEM1, and extend from the first binary word DT10 to the last bit word DTlx present in the memory MEM1. The data supplied during the second counting cycle are those read by the memory MEM2 and extend from the first binary word DT20 to the last binary word DT2x present in the memory MEM2. Likewise, the data supplied during the third counting cycle are those read by the memory MEM3 and extend from the first binary word DT30 to the last binary word DT3x present in the memory MEM3. During the fourth and last counting cycle, the data provided are those read by the memory MEM4, and extend from the first binary word DT40 to the last binary word DT4x present in the memory MEM4. Stopping the read process can however occur at any time, and is usually triggered by ceasing to apply the CKO clock signal to the memories.

  It will be clear to one skilled in the art that a memory according to the invention is capable of various variants and embodiments.

  Thus, although it has been proposed in the foregoing that the non-execution of a reading command by a memory is obtained by performing a reading of the integrated memory plane and then blocking the data at the output of the memory, a Another method may also consist in not reading the memory plane. A complex decoder covering all the address bits of the counter must then be provided to anticipate the moment when data will have to be provided, in order to initialize the reading of the memory array in good time during the execution of a command. in which the extended address counter is continuously incremented or decremented.

  Also, it will be apparent to those skilled in the art that various combinations of the means of the invention may be provided, some means may not be implemented.

  Those skilled in the art will note in particular that the provision of an extended address counter is only justified if it is desired that the memories can execute a continuous read command covering the entire extended memory plane, or on a part of the extended memory array covering at least two separate memories. If it is not planned to program the central units to execute such a command, the high-order addresses can be directly applied to the comparator or be stored by a static register which does not provide the counting function.

  Those skilled in the art will also note that the implementation of the availability / occupation contact RBP and the EWIP signal is justified only if the integrated memory plane of each memory is accessible both for reading and writing ( for example a flash memory plane or EEPROM). Also, the prediction of the configurable address counter and / or the configurable comparator is only justified if it is desired to provide a configurable memory, intended to be incorporated in an extended memory plane whose size is not predetermined.

  Similarly, the prediction of the master memory signal is justified only if it is desired to provide an extended memory array capable of responding to a command for reading special registers.

  Finally, although it has been described for the sake of simplicity the realization of an extended memory plane having memories having integrated memory planes of the same size, it will be clear to those skilled in the art that the invention also applies to the realization of a composite extended memory plane. In this case, N and K are different in each memory but the sum of N and K remains constant and equal to the number of bits that comprise the extended address of the composite extended memory array.

Claims (27)

  A method for producing an extended memory array comprising a plurality of silicon-based integrated memory memories (MEM1-MEM4), each memory comprising a serial input / output and an N-bit addressable integrated memory array (MA), N being able to be different for each integrated memory, the extended memory array being addressable by means of an extended address (EAD) comprising N least significant bits (ADL) and K most significant bits (ADH), the serial inputs / outputs of the memories being interconnected, characterized in that it comprises the steps of: - providing, in each memory, an availability / occupancy contact (RBP), - providing, in each memory, means (RBCT, UC) for forcing the availability / occupancy contact (RBP) at a determined electrical potential during an erasure or programming operation of the integrated memory plane (MA), - interconnecting the availability contacts ity / occupation of the memories, and - prevent the execution of a read or write command in each memory when the electrical potential of the contact (RBP) availability / occupation has the determined potential (GND).   2. Method according to claim 1, comprising the steps of: - providing, in each memory, means (IDXREG) for storing a high-order address (RADH) allocated to the memory within the extended memory array, each memory a high-order address (RADH), - apply to the read / write commands memory including an extended address (EAD), and 28 - prevent the execution of a read or write command in each memory when the K most significant address bits (ADH) of the extended address are different from the high-order address (RADH) assigned to the memory.   The method of claim 2, wherein the step of preventing execution of a read command in a memory includes a step of preventing read data in the integrated memory (MA) of the memory of be provided on the input / output of the memory.   The method of claim 3, wherein each memory includes an output buffer (OUTBUF) for providing on the serial input / output of the memory data read from the integrated memory (MA) plane, and wherein a step of preventing data read in the integrated memory array from being provided on the input / output of the memory includes a step of providing a blocking signal (ADMATCH, SHZ) to the output buffer circuit (OUTBUF) of the memory.   5. Method according to one of claims 1 to 4,   for performing an extended memory array that can respond to a continuous read command of the memory array, comprising the steps of: - providing, in each memory, an extended address counter (EACNT) of N + K bits, for storing an extended address, applying to the memories an extended read command having an extended read start address, and continuously incrementing or decrementing the extended address counter (EACNT) of each memory, including when the K bits of High-order address (ADH) are different from the high-order address (RADH) assigned to 2863765 memory, until the execution of the continuous read command is stopped.   The method of claim 5, wherein, during the execution of a continuous read command, the integrated memory array (MA) of each memory is read continuously even when the K most significant address bits (ADH ) are different from the high-order address (RADH) assigned to the memory.   The method of claim 5, wherein, during execution of a continuous read command, the integrated memory (MA) plane of each memory is read only when the K most significant address bits (ADH) ) are identical to the high-order address (RADH) assigned to the memory.   8. Method according to one of claims 1 to 7, comprising a step of providing, in each memory, means (CNFREG) for storing information (K1, K0) on the number K of high-order bits that can include at most the extended address, K being a variable between 0 and Kmax, Kmax being a non-zero integer delimiting the maximum size of the extended address.   9. The method as claimed in claim 8, for producing an extended memory array of variable size addressable by means of an extended address that can range from N bits to N + Kmax bits, without modifying the architecture of the memories composing the memory array. extended, comprising the steps of: - providing, in each memory, an extended address counter (EACNT) comprising N + Kmax counting cells 35 of one bit each, - providing, in each memory, means for memorizing Kmax reference bits, and 41 2863765 - assign to each memory at least K reference bits (R2-RO) forming a high-order address (RADH), K being between 0 and Kmax.   The method of claim 9, including a step of disabling Extended Address Counter counting cells (EACNT) based on the information (K1, K0) on the number K so that the counter includes only N + K active counting cells.   11. Method according to one of claims 9 and 10, comprising a step of comparing only K reference bits (R2-RO) with K most significant address bits (ADH) present in the counter, without taking into account other address bits present in the counter.   12. Method according to one of claims 8 to 11, wherein the information (K1, KO) on the number K is provided to the memories in the form of a coded binary number giving an indication of the size of the extended memory array .   13. Method according to one of claims 1 to 12,   comprising a step of providing, in each memory, specific contacts (IDXPO-IDXP2), and a step of configuring the high-order address (RADH) assigned to the memory by applying determined electrical potentials to the specific contacts.   14. Memory (MEM) on a silicon chip comprising a serial input / output and an N-bit addressable integrated memory array (MA), characterized in that it comprises: an availability / occupation contact (RBP); means (RBCT, UC) for forcing the availability / occupancy contact (RBP) at a given electrical potential during an erasure or programming operation of the integrated memory array (MA), and releasing the contact electrical potential (RBP) availability / occupation outside the erase operations or programming the integrated memory plane, and means (UC) to prevent the execution of a read command or write the integrated memory array when the potential availability / occupancy contact (RBP) has the determined potential (GND), even when the memory is not performing an erase or programming operation of the integrated memory array .   The memory of claim 14, comprising: - means (IDXREG) for storing a high-order address (RADH) allocated to the memory within an addressable extended memory array by means of an extended address (EAD) comprising N least significant bits (ADL) and K most significant bits (ADH), - storage means (EACNT) of an extended address present in a command applied to the serial input / output of the memory, - means (COMP) to compare the K most significant address (ADH) bits with the highest order (RADH) address assigned to the memory, and - means (COMP, ADMATCH, SHZ, OUTBUF) to prevent the execution of an integrated memory map (MA) reading or writing command when the K most significant address bits (ADH) present in the read command are different from the assigned high-order address (RADH) in memory.   Memory according to claim 15, comprising: - an output buffer circuit (OUTBUF) for providing on the serial input / output of the memory data read in the integrated memory plane (MA), and 2863765 - a comparator ( COMP) to provide a blocking signal (ADMATCH, SHZ) of the output buffer (OUTBUF) if the K most significant address (ADH) bits are different from the high order address (RADH) assigned to the memory .   Memory according to claim 16, comprising a time shift circuit (SYNCCT) for delaying the application of the blocking signal (ADMATCH, SHZ) to the output buffer circuit (OUTBUF) if, at the moment blocking changes to an active value, the output buffer is supplying on the serial input / output the bits of data read in the integrated memory (MA) plane before the blocking signal passes to the value active.   Memory according to one of claims 15 to 17, comprising: - an extended address counter (EACNT) of N + K bits, for storing an extended address (EAD) received on the serial input / output of the memory, and - a central unit (CPU) for executing a continuous read command of the extended memory array by continuously incrementing or decrementing the extended address counter (EACNT) even when the K most significant address bits (ADH). are different from the high-order address (RADH) assigned to the memory until the execution of the continuous read command is stopped.   Memory according to claim 18, wherein the central unit is arranged to continuously read the integrated memory (MA) plane during the execution of a continuous read command, including when the K most significant address bits. (ADH) are different from the high-order address (RADH) assigned to the memory.   44 2863765 The memory of claim 18, wherein, during the execution of a continuous read command, the CPU is arranged to read the integrated memory (MA) plane only when the K most significant address bits. (ADH) are identical to the high-order address (RADH) assigned to the memory.   21. Memory according to one of claims 15 to 20, comprising: - means (CNFREG) for storing information (K1, KO) on the number K of high-order bits that includes the extended address, K being a variable between 0 and Kmax, Kmax being a non-zero integer delimiting the maximum size of the extended address, - an extended address counter (EACNT) comprising N + Kmax counting cells of one bit each, and - means for storing Kmax reference bits among which K reference bits (R2-RO) represent a high-order address (RADH) allocated to the integrated memory plane (MA) within the extended memory plane.   22. Memory according to claim 21, comprising a configuration register (CNFREG) for memorizing Kmax flags (F2-FO) corresponding by their number and their rank to Kmax bits of high weight that can contain at most the extended address, each flag having a logical value determined if the most significant bit of corresponding rank is present in the extended address, the number of flags (F2-FO) having the determined logical value defining the number K of most significant bits present in the address extended.   The memory of claim 22, comprising a configuration register (CNFREG) for storing a coded bit number giving an indication of the size of the extended memory array, and a decoding circuit providing, from the encoded binary number, Kmax 2863765 flags. (F2-FO) corresponding in number and rank to the most significant bits that can hold the extended address at the maximum, each flag having a logical value determined if the most significant bit of corresponding rank is present in an extended address, the number of flags (F2-FO) having the determined logic value defining the number K of most significant bits present in the extended address.   24. The memory according to one of claims 21 to 23, comprising means for deactivating count cells of the extended address counter (EACNT) as a function of the information (K1, K0) on the number K, so that the counter only includes N + K active counting cells.   Memory according to one of Claims 21 to 23, in which the means for comparing the K most significant address bits (ADH) with the K reference bits (R2-RO) comprise a comparator (COMP) comprising Kmax. inputs and means for inhibiting inputs of the comparator (COMP) as a function of the information (K1, KO) on the number K, so that the comparator (COMP) comprises only K active inputs.   Memory according to one of Claims 15 to 25, comprising specific contacts (IDXPO-IDXP2) allowing a hardware configuration of the high-order address (RADH) allocated to the memory, by applying specific electrical potentials to the contacts. specific.   An extended memory array comprising a combination of at least two memories according to one of claims 14 to 26, wherein the serial inputs / outputs of each memory are interconnected and the availability / occupation contacts of each memory are interconnected. .