FR2857156B1 - METHOD FOR MANUFACTURING ELECTRONIC COMPONENTS OF REDUCED THICKNESS - Google Patents
METHOD FOR MANUFACTURING ELECTRONIC COMPONENTS OF REDUCED THICKNESSInfo
- Publication number
- FR2857156B1 FR2857156B1 FR0308107A FR0308107A FR2857156B1 FR 2857156 B1 FR2857156 B1 FR 2857156B1 FR 0308107 A FR0308107 A FR 0308107A FR 0308107 A FR0308107 A FR 0308107A FR 2857156 B1 FR2857156 B1 FR 2857156B1
- Authority
- FR
- France
- Prior art keywords
- electronic components
- reduced thickness
- manufacturing electronic
- manufacturing
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/10—Mounting in enclosures
- H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
- H03H9/1085—Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a non-uniform sealing mass covering the non-active sides of the BAW device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3164—Partial encapsulation or coating the coating being a foil
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H9/00—Networks comprising electromechanical or electro-acoustic devices; Electromechanical resonators
- H03H9/02—Details
- H03H9/05—Holders; Supports
- H03H9/10—Mounting in enclosures
- H03H9/1064—Mounting in enclosures for surface acoustic wave [SAW] devices
- H03H9/1078—Mounting in enclosures for surface acoustic wave [SAW] devices the enclosure being defined by a foil covering the non-active sides of the SAW device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0612—Layout
- H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01057—Lanthanum [La]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Acoustics & Sound (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Geometry (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
- Wire Bonding (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0308107A FR2857156B1 (en) | 2003-07-03 | 2003-07-03 | METHOD FOR MANUFACTURING ELECTRONIC COMPONENTS OF REDUCED THICKNESS |
PCT/FR2004/001642 WO2005013353A2 (en) | 2003-07-03 | 2004-06-28 | Method for producing reduced-thickness electronic components |
TW093119849A TW200511523A (en) | 2003-07-03 | 2004-06-30 | Process for fabricating narrow thickness electronic components |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0308107A FR2857156B1 (en) | 2003-07-03 | 2003-07-03 | METHOD FOR MANUFACTURING ELECTRONIC COMPONENTS OF REDUCED THICKNESS |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2857156A1 FR2857156A1 (en) | 2005-01-07 |
FR2857156B1 true FR2857156B1 (en) | 2005-09-02 |
Family
ID=33522721
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0308107A Expired - Fee Related FR2857156B1 (en) | 2003-07-03 | 2003-07-03 | METHOD FOR MANUFACTURING ELECTRONIC COMPONENTS OF REDUCED THICKNESS |
Country Status (3)
Country | Link |
---|---|
FR (1) | FR2857156B1 (en) |
TW (1) | TW200511523A (en) |
WO (1) | WO2005013353A2 (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108022886A (en) * | 2017-11-30 | 2018-05-11 | 深圳华远微电科技有限公司 | A kind of encapsulating structure of chip upside-down mounting type wave filter |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2799883B1 (en) * | 1999-10-15 | 2003-05-30 | Thomson Csf | METHOD OF ENCAPSULATING ELECTRONIC COMPONENTS |
JP2001339011A (en) * | 2000-03-24 | 2001-12-07 | Shinko Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
DE10136743B4 (en) * | 2001-07-27 | 2013-02-14 | Epcos Ag | Method for the hermetic encapsulation of a component |
-
2003
- 2003-07-03 FR FR0308107A patent/FR2857156B1/en not_active Expired - Fee Related
-
2004
- 2004-06-28 WO PCT/FR2004/001642 patent/WO2005013353A2/en active Application Filing
- 2004-06-30 TW TW093119849A patent/TW200511523A/en unknown
Also Published As
Publication number | Publication date |
---|---|
WO2005013353A3 (en) | 2005-07-28 |
FR2857156A1 (en) | 2005-01-07 |
WO2005013353A2 (en) | 2005-02-10 |
TW200511523A (en) | 2005-03-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
FR2851373B1 (en) | METHOD FOR MANUFACTURING AN INTEGRATED ELECTRONIC CIRCUIT INCORPORATING CAVITIES | |
FI20031341A0 (en) | Method for manufacturing an electronic module | |
FR2825773B1 (en) | MULTILAYER PIPE AND METHOD OF MANUFACTURE | |
DE60227481D1 (en) | Manufacturing process for complementary transistors | |
FR2836486B1 (en) | PROCESS FOR PRODUCING A METALLIC ELEMENT | |
GB2402941B (en) | Method for manufacturing substrate | |
FR2883206B1 (en) | METHOD FOR MANUFACTURING JOINT FITTING AND JOINT FITTING | |
FR2885745B1 (en) | RECOVERY BOX AND METHOD OF MANUFACTURE | |
DE60123570D1 (en) | Production process for an electronic medium | |
FR2864059B1 (en) | INTEGRATED MICROSOUPAPE AND METHOD FOR MANUFACTURING SUCH MICROSOUPAPE | |
FR2856552B1 (en) | METHOD FOR MANUFACTURING PARTS FOR PASSIVE ELECTRONIC COMPONENTS AND PARTS OBTAINED | |
FR2858618B1 (en) | PROCESS AND REACTOR FOR MANUFACTURING HYDROXYMETHYLFURFURAL | |
FR2853473B1 (en) | ELECTRONIC COMPONENT COMPRISING A RESONATOR AND METHOD OF MANUFACTURING | |
FR2826964B1 (en) | PROCESS FOR THE MANUFACTURE OF (METH) ACRYLATES SILANES | |
FR2832852B1 (en) | METHOD FOR MANUFACTURING AN ELECTRONIC COMPONENT INCORPORATING AN INDUCTIVE MICRO-COMPONENT | |
FR2883939B1 (en) | ROD AND METHOD FOR MANUFACTURING SUCH ROD | |
FR2863773B1 (en) | PROCESS FOR THE PRODUCTION OF AMINCI SILICON ELECTRONIC CHIPS | |
FR2833411B1 (en) | METHOD FOR MANUFACTURING AN ELECTRONIC COMPONENT INCORPORATING AN INDUCTIVE MICRO-COMPONENT | |
FR2879420B1 (en) | BEDDING SOMMIER STRUCTURE AND METHOD FOR MANUFACTURING SUCH STRUCTURE | |
FR2857156B1 (en) | METHOD FOR MANUFACTURING ELECTRONIC COMPONENTS OF REDUCED THICKNESS | |
FR2860730B1 (en) | PROCESS FOR MANUFACTURING POROUS ELEMENT AND APPLICATIONS | |
FR2875927B1 (en) | METHOD FOR PROTECTING AN ELECTRONIC CHIP, SELF-CHANGED ELECTRONIC CHIP AND METHOD OF MANUFACTURING THE CHIP | |
FR2832853B1 (en) | METHOD FOR MANUFACTURING AN ELECTRONIC COMPONENT INCORPORATING AN INDUCTIVE MICRO-COMPONENT | |
FR2827270B1 (en) | PROCESS FOR MANUFACTURING MICROSCOPIC PARTS | |
ITMI20021985A1 (en) | METHOD FOR THE MANUFACTURE OF ELECTRONIC SEMICONDUCTOR DEVICES |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 13 |
|
CD | Change of name or company name |
Owner name: EPCOS AG, DE Effective date: 20160223 |
|
CJ | Change in legal form |
Effective date: 20160223 |
|
TP | Transmission of property |
Owner name: EPCOS AG, DE Effective date: 20160223 |
|
PLFP | Fee payment |
Year of fee payment: 14 |
|
PLFP | Fee payment |
Year of fee payment: 15 |
|
TP | Transmission of property |
Owner name: SNAPTRACK, INC., US Effective date: 20180202 |
|
PLFP | Fee payment |
Year of fee payment: 16 |
|
ST | Notification of lapse |
Effective date: 20200306 |