FR2850222A1 - Optical transmission system, has modulation-multiplexing unit producing optical signal at two voltage levels, and demodulation-demultiplexing unit restoring electric signals from signal produced at two voltage levels - Google Patents

Abstract

The system has distant equipment (4) including a modulating-multiplexing and demodulation- demultiplexing unit (7, 8). The unit (7) is linked with an optical transmitter (9) that converts electric signals into an optical signal. The modulation-multiplexing unit produces the optical signal at two voltage levels, and a demodulation-demultiplexing unit (8) restores the electric signals from the signal having two voltage levels.

Description

The present invention relates to a system for

  optical transmission, in particular for the offset by optical fibers of electrical signals of x-DSL type.

  The invention relates to the field of x-DSL type broadband access systems, for example ADSL ("Asynchronous Digital Subscriber Line" in English terminology). It typically finds its application in serving areas remote from a network access node, also called a central office.

  In the current context of the increase in transmission speed, and the explosion of Internet services, many broadband access systems have been introduced to subscribers. These broadband access systems use existing cabling, that is, cabling on twisted copper pair. However, for areas remote from the exchange, the throughput performance is greatly degraded due to the weakening of the copper pair.

  In order to allow the service of said remote areas in high-speed services, systems for offsetting electrical signals by means of one or more optical fibers are proposed. One of these systems is described in the article by Masaru Fuse, Toshihiko Yasue, Mariko 25 Nakaso, Hiroaki Yamamoto, Kuniaki Utsumi, and Susumu Morikura entitled "Proposal of Multi-channel xDSL Access System for Multidwellings using Optical SCM Technology "and published in" Proceedings of ECOC'02, paper 9.2.4 "1. The system described in this article uses a known modulation-multiplexing technique, usually called "Optical SCM" (Optical Sub-Carrier Multiplexing in English).

  The invention will now be presented with reference to FIG. 1 which schematically represents a system similar to that which is described in the above-mentioned article.

  Such a system comprises a center equipment 1 5 located near or inside a central and connected by copper pairs 21 to 2n to an access equipment 3 which can be, for example, a DSLAM ("Digital Subscriber Line Access Multiplexerl "in Anglo-Saxon terminology). It also includes remote equipment 4 located near users U1 to Un. The center equipment 1 is connected to the remote equipment 4 by a fiber optic cable 5.

  The elementary functions of the center 1 and remote 4 equipment are symmetrical. Thus, these devices 15 firstly comprise means 6 for separating the two directions of transmission. These means 6 can be, for example, diplexing filters or directional couplers. They also include modulation-multiplexing means 7 as well as demultiplexing-demodulation means 8. The modulation and multiplexing functions, as well as those of demultiplexing and demodulation, have been voluntarily combined here because, in practice, they are very often strongly nested. This equipment also includes optical transmitters 9 and optical receivers 10. Each optical transmitter 9 thus makes it possible to convert the frequency modulated and multiplexed signal, coming from a modulation - multiplexing means, into an optical signal which it transmits on the optical fiber cable 5. Each optical receiver 30 10 makes it possible to restore the multiplexed electrical signal from the received optical signal. One can use an optical fiber per direction of transmission or a single fiber for the two directions of transmission by implementing, for example, optical wavelength multiplexing.

  An important drawback of the "Optical SCM" technique is that it involves the use of an expensive optical transmitter 9 to allow optimal linearity to be obtained between the power of the optical signal and the signal voltage. electrical, in order to limit the level of intermodulation products between the sub-carriers and thus avoid problems of distortion of the signal conveyed. This can lead, in practice, to impose the use of a DFB 10 type laser ("Distributed Feed Back", in English) more expensive than a FP type laser ("Fabry-Pérot") or VCSEL type ("Vertical Cavity Surface Emitting Laser" in English).

  Another drawback resides in the fact that, in order to avoid the phenomenon of clipping, or "clipping" in English, as well as the phenomenon of distortion of the underlying intermodulation, phenomena both well known to those skilled in the art, the effective optical modulation index must not exceed a low value close to 25%. However, such an index value is not favorable in terms of signal to noise ratio at the output of the optical receiver and, consequently, it results in a high optical power required for reception.

  Another drawback concerns the modulation-multiplexing and demultiplexing-demodulation functions which require, for their implementation, numerous circuits such as for example local oscillators, mixers and selective filters which are generally expensive, bulky or large consumers energy.

  Also, the technical problem to be solved by the object 30 of the present invention is to propose an optical transmission system, in particular for the offset by optical fiber of electrical signals of x-DSL type, comprising center equipment connected to equipment. remote by means of at least one fiber optic cable, said center equipment and said remote equipment each comprising a multiplexing modulation means connected to an optical transmitter equipment to convert said electrical signals into an optical signal intended to be conveyed on the fiber optic cable, and a demultiplexing-demodulation means 5 connected to an optical receiver for restoring the electrical signals from said optical signal conveyed on said fiber optic cable, which would overcome constraints on the linearity between the power of the optical signal and the voltage of the electrical signals, to allow the use of a less expensive optical transmitter, and which would furthermore have an effective optical modulation index well above 25%, which would be favorable for obtaining the optical power required for low reception.

  The solution to the technical problem is obtained, according to the present invention, by the fact that said modulation - multiplexing means is arranged to produce a signal at two voltage levels and that said demultiplexing - demodulation means is arranged to reproduce said electrical signals from said signal at two voltage levels generated by said modulation - multiplexing means.

  Thus, the signal produced by the modulation means 25 -multiplexing being a binary type signal since it has two voltage levels, the clipping phenomena as well as the intermodulation distortion phenomena no longer appear. Consequently, the system makes it possible to overcome the constraints on the linearity and can therefore use a less expensive optical transmitter than those used up to now. In addition, for such a signal, the clipping phenomenon being avoided, there is no longer any constraint on the effective optical modulation index which can therefore reach a value close to 100%.

  On the other hand, thanks to the invention, the multiplexing modulation functions on the one hand, and demultiplexing - demodulation functions on the other hand use inexpensive circuits, not bulky, and consuming little energy.

  Other features and advantages of the invention will appear on reading the following description, given by way of illustrative but nonlimiting example, with reference to the appended figures which represent: FIG. 1, already described, a functional diagram 10 d 'an optical transmission system for the offset by optical fibers of electrical signals of x-DSL type, - Figure 2a, a functional diagram of a modulation-multiplexing means used in a system conforming to that of Figure 1, - FIG. 2b, a timing diagram of the signals relating to the modulation-multiplexing means shown diagrammatically in FIG. 2a, FIG. 3, a diagram of an embodiment of a means for generating voltage ramp signals 20 used in the modulation means - multiplexing of FIG. 2a, FIG. 4, a diagram of an embodiment of a means of generating synchronization elements used in the modulation means - multiplexing of FIG ure 25 2a, - Figure 5a, a block diagram of a demultiplexing-demodulation means used in a system conforming to that of Figure 1, - Figure 5b, a timing diagram of the signals relating to the demultiplexing - demodulation means schematically in FIG. 5a, FIG. 6, a diagram of an embodiment of a synchronization recovery means used in the demultiplexing - demodulation means of FIG. 5a. FIG. 1 which has already been described to illustrate the prior art, also applies to an optical transmission system, for the offset by optical fibers of electrical signals of x-DSL type according to the invention. Indeed, the system comprises the same elements as the system already described. The difference with the systems of the prior art essentially lies in the processing of the signals by the multiplexing modulation 7 and demultiplexing - demodulation 8 means. The modulation - multiplexing 7 means in particular no longer processes the signals according to the SCM technique, but it is arranged to convert them into a signal with two voltage levels. The demultiplexing - demodulation means is, in turn, arranged to restore each of the electrical signals SI to 15 Sn of type x-DSL from the signal at two voltage levels generated by the multiplexing modulation means.

  A functional diagram of a multiplexing modulation means 7 intended to produce a signal with two voltage levels is shown in FIG. 2a and will be described, for a better understanding, with reference to the timing diagram of FIG. 2b.

  The signal at two voltage levels which is produced consists of periodic frames each comprising a synchronization cell CELO followed by cells CEL1 to CELn respectively corresponding to each of the signals S1 to Sn to be multiplexed and each comprising a single voltage level transition whose time position is a function of the voltage of said electrical signal S1 - Sn 30 corresponding to the instant of said transition.

  An oscillator it produces a clock signal CLK which controls a shift register 12. This shift register operates in a loop so as to periodically produce on its outputs control signals Co to Cn 35 corresponding to cells CELO to CELn. The control signal CO is directed to a means for generating synchronization elements 13 while the control signals C1 to Cn control means for generating voltage ramps 14, to 14n intended to produce ramp signals Ri to Rn. These ramp signals are compared, by means of comparators 151 to 15n, to the electrical input signals Si to Sn of the multiplexing modulation means 7 so as to produce the signals TI to Tn each rising transition of which is produced when the instantaneous voltages of ramp Ri - Rn and corresponding signal Si Sn are equal.

  Thus, each rising transition of the signals T1 to Tn has a time position in its cell CEL1 to CELn which is proportional to the instantaneous voltage of the corresponding input signal Si to Sn, at the instant of said transition. For correct operation, the amplitude of the ramp signals must of course be greater than the maximum peak-to-peak amplitude of the input signals SI to Sn.

  The signals Tl to Tn are then time-multiplexed by means of a first "YES" logic gate 16a which receives the signals from the comparators 15 of rank of a first parity, for example of odd rank, and of a second gate "YES" logic 16b which receives the 25 signals from the comparators 15 of rank of the other parity, that is to say of even rank in the example. The "OR" gate 16a, respectively 16b, is followed by a monostable flip-flop 17a, respectively 17b, which delivers a signal Ta, respectively Tb, comprising a short pulse 30 for each rising transition of the signals TI - Tn of odd rank, respectively even . The signals Ta and Tb are directed to the set and reset inputs of a flip-flop 18 which delivers on its output a time multiplex signal TM with two voltage levels capable of modulating an optical transmitter in light intensity.

  It should be noted that the monostable flip-flops 17a and 17b are not functionally essential for the production of the signal TM. In fact, their presence is advantageous because they reduce the risk of malfunction of the flip-flop 18 caused by an overlapping of the pulses on its set and reset inputs.

  Indeed, the ramp signals Ri to Rn are represented in FIG. 2b in an ideal manner for reasons of simplicity, but, in practice, it is quite obvious that the 10 rising edges of these signals do not have a rise time no. For this reason, the falling edges of the signals Tl to Tn can encroach on the immediately next cell, which constitutes a risk of overlapping between two consecutive pulses Tl to Tn. In addition, since it is difficult, in practice, to produce a well-linear ramp in the areas close to its ends, it is possible to use a ramp whose duration is greater than the duration of a cell, but this further increases the risk overlap between two consecutive pulses Tl to Tn 20.

  It is interesting to note that the signals T1 to Tn correspond to a type of modulation well known under the name PWM ("Pulse Width Modulation" in English).

  PWM modulation is a synchronous modulation with irregular sampling. In fact, the voltage samples of the modulating signal are not taken regularly, but at times which depend on the value of these samples. For this reason, it is necessary to use an average sampling repetition frequency higher than the minimum frequency allowed by sampling theory. This minimum frequency is equal to twice the highest frequency contained in the signals Si to Sn to be multiplexed.

  It should be noted that in the case of the present invention, the maximum amplitude of the variations in sampling instant is equal to the duration of a cell. For this reason, when the number of cells per frame is high, it can be considered that the sampling is almost regular which allows the use of a ramp repetition frequency close to the minimum frequency authorized by the theory of l 'sampling.

  For example, by way of illustration, in the case of a downlink ADSL signal, for which it is recalled that the highest frequency is of the order of 1.1 MHz, a ramp repetition frequency of l order of 3 MHz is sufficient with a frame comprising 16 cells, one of which is reserved for synchronization and the other 15 for the multiplexing of 15 signals. The CLK clock frequency is then 3X16 = 48 MHz and the average frequency of the TM signal is 48/2 = 24 MHz. Note that in order to maintain good precision of the moments of transition of the TM signal, the high cutoff frequency of the optical transmission channel must be of the order of ten times the average frequency of the TM signal, ie 240 MHz.

  An embodiment of one of the ramp generation means 14 is shown in FIG. 3. It comprises a first transistor 19 for supplying a capacitor 20 25 with constant current. To this end, this transistor 19 includes in its emitter circuit a resistor 21 connected to a potential -V and its base is connected to a reference potential Vref. Thus, the constant current is determined by the resistor 21 and the difference between 30 Vref and -V. The ramp generation means also comprises a second transistor 22 for resetting the voltage ramp across the capacitor 20 and an adaptation means 23 intended to make the logic levels compatible, for example TTL (from the English "Transistor 35 Transistor Logic ") or ECL (from the English" Emitter-Coupled Logic "), of the corresponding control signal Cl coming from the shift register 12 with the high and low voltages required on the base of the transistor 22. This adaptation means 23 can be, for example, a simple bridge of 5 resistors. The transistors shown in Figure 3 are bipolar transistors, but it is of course possible to use field effect transistors.

  An embodiment of the means for generating synchronization elements 13, used in the modulation-multiplexing means of FIG. 2a, is shown in FIG. 4. It comprises a monostable flip-flop 24 receiving the control signal CO and delivering a signal SY which comprises a short pulse for each rising transition of the signal CO. This signal SY is directed to three delay means, 25a, 25b and 25c, which provide a delay of Y2, y4, and% 4, respectively, of the duration of the synchronization cell CELO. The signal SYa from the delay means 25a is directed to an input of the logic "OR" gate 16a and the signals from the delay means 25b and 25c are applied to the inputs of another logic "OR" gate 26 which delivers a signal SYb directed to an input of the logic gate "OR" 16b.

  A synchronization element thus produced is represented in FIG. 2b by the part of the TM signal 25 located inside the CELO cell. It has of course the characteristic of not being able to be imitated by a particular position of the transitions located in cells CELI to CELn. It is centered in the CELO synchronization cell and is made up of three transitions 30 spaced apart from each other by a quarter of its duration.

  It should be noted that the circuits used in the multiplexing modulation means and which have just been described, have the advantage of being inexpensive, not bulky and consuming little energy.

  A functional diagram of a demultiplexing demodulation means 8 intended to restore, from the signal TM produced by the multiplexing modulation means 7, the electrical signals Si to Sn, is shown in FIG. 5 5a and will be described, for better understanding, referring to the timing diagram in Figure 5b.

  The signal at two voltage levels TM from the optical receiver 10 is applied to the input of a comparison means 27 with symmetrical outputs. This comparator 27 10 thus produces the signal TM and the inverted signal TMinv. The demultiplexing - demodulation means 8 comprises as many "AND" logic gates 28, 28nq as there are signals Si to Sn to be restored. The signal TM, coming from the comparator 27 is applied to an input of each AND gate 28 of rank 15 of a first parity, for example of odd rank, while the inverted signal Tminv is applied to an input of each gate 28 of rank on the other parity, that is to say of even rank in the example. The AND gates 28, to 28n also receive selection signals SELi to SELn 20 produced by a shift register 29 which, like the shift register 12 of FIG. 2a, operates in a loop. This shift register 29 is controlled by an oscillator 30 whose frequency is controlled by a voltage from a synchronization recovery means 31 receiving on the one hand the signals TM and TMinv and on the other hand a signal for selecting SELO synchronization generated by the shift register 29.

  The timing diagram of FIG. 5b clearly shows that the signals Pl to Pn obtained at the output of the AND gates 28i to 30 28, respectively identical to the signals Tl to Tn of FIG. 2b, correspond to a PWM type modulation of the signals Si to Sn. According to a known property of PWM modulation, the signals Pi to Pn include in their frequency spectrum the corresponding signals Si to Sn which can be isolated by simple low-pass filtering obtained by means of low-pass amplifiers 32, at 32n.

  The synchronization recovery means 31, of the demultiplexing - demodulation means 8, intended to detect the presence of the synchronization elements produced by the generation means 13 of synchronization elements, of FIG. 4, is represented in FIG. 6 It comprises a monostable flip-flop 33a, respectively 33b, producing a short pulse for each rising transition of the signal at two voltage levels TM, respectively of the inverted signal TMinv, a delay means 34a, respectively 34b, of a value of Y4. , respectively Y2, of the duration of the CELO cell and a three-input "AND" logic gate 35 which thus delivers a short pulse when the presence of a synchronization element is detected. The RSY signal formed by these short pulses is applied to an input of a phase comparator 36 which forms with the oscillator 30 and the shift register 29 a phase locked loop 20 whose operation is well known to those skilled in the art. art.

  This phase comparator 36 also receives a signal SELOa which is obtained by delaying the synchronization selection signal SELO via a delay means 37. The phase comparator 36 is for example of the type producing on its output an error voltage zero when the pulses arriving on its inputs are centered between them. This configuration is represented on the timing diagram of FIG. 5b by the signals RSY and SELOa.

  Of course, the direction of the signals of the timing diagrams of FIGS. 2b and 5b is only an illustrative example because it is quite possible to conceive an embodiment of the modulation-multiplexing means 7 and the demultiplexing-demodulation means 8 with inverted signals.

  The circuits used in the multiplexing modulation means 7 and in the demultiplexing demodulation means 8 which have just been described have the advantage of being simple elements, inexpensive, not bulky and consuming little energy.

Claims (11)

  1. Optical transmission system, in particular for the offset by optical fibers of electrical signals (S1-Sn) of x-DSL type, comprising center equipment (1) connected to remote equipment (4) by means of at least one fiber optic cable (5), said center equipment (1) and said remote equipment (4) each comprising modulation-multiplexing means (7) connected to an optical transmitter (9) for converting said electrical signals ( Si - Sn) into an optical signal intended to be conveyed on the fiber optic cable (5), and a demultiplexing-demodulation means (8) connected to an optical receiver (10) to restore the electrical signals (S1-Sn ) from said optical signal carried on said optical fiber cable, characterized in that the multiplexing modulation means (7) is arranged to produce a signal at two voltage levels (TM) and in that the demultiplexer - demodulator ( 8) is arranged to restore each one of the electrical signals (S1 - Sn) from said signal at two voltage levels (TM) 25 generated by said multiplexing modulation means.   2. System according to claim 1, characterized in that the signal at two voltage levels (TM) consists of periodic frames each comprising a synchronization cell (CEL0) followed by cells (CELI - CELn) corresponding respectively to each of said electrical signals (S1 - Sn) and each comprising a single voltage level transition 35 whose time position is a function of the voltage of said electrical signal (S1-Sn) corresponding to the instant of said transition.   3. System according to claim 2, characterized in that the synchronization cell (CELO) comprises a synchronization element centered in said synchronization cell and composed of three transitions spaced apart from each other by a quarter of its duration.   4. System according to one of claims 1 to 3,   characterized in that the multiplexing modulation means (7) comprises: means (13) for generating synchronization elements, - means (14, - 14,) for generating voltage ramp signals (RI - Rn ), - means (151 - 15,) for comparing the voltage ramp signals (RI Rn) with the electrical signals (S1 - Sn), intended to generate signals (Tl - Tn) each having an upward transition when the instantaneous voltage of a corresponding ramp signal (Ri - Rn) is equal to that of the corresponding signal (S1-Sn), - two "OR" logic gates (16a, 16b) each receiving the signals from the comparison means (151 - 15,) of ranks of first and second parity respectively.   - a bistable flip-flop (18) delivering said signal at two voltage levels (TM) from signals from said "OR" logic gates (16a, 16b).   5. System according to claim 4, characterized in that the modulation - multiplexing means (7) further comprises an oscillator (11) delivering a clock signal intended to drive a shift register (12) operating in a loop for produce on the one hand a control signal (CO) of the means (13) 5 for generating synchronization elements, and on the other hand control signals (Cl - Cn) of the means (14, - 14,) of generation of ramp signals (RI - Rn).   6. System according to one of the preceding claims, characterized in that the means (13) for generating synchronization elements comprises a monostable rocker (24) receiving the control signal (CO), three delay means (25a, 25b and 25c) which provide respectively a delay of VA, 'and 3 / of the duration of the synchronization cell (CELO) and a logic "OR" gate (26) connected to two of the delay means (25b, 25c) .   7. System according to one of the preceding claims, characterized in that each of the logic gates "or" (16a, 16b), of the multiplexing modulation means, is connected to a monostable rocker (17a, 17b) delivering a signal (Ta , Tb) to an input of the flip-flop (18), said signal (Ta, Tb) comprising a short pulse for each rising transition of the signals (Tl - Tn) of first and second parity ranks respectively.   8. System according to one of the preceding claims, characterized in that each means (14, - 14j) for generating ramp signals comprises: a first transistor (19) for supplying a capacitor (20) with constant current, said first transistor comprising in its emitter circuit a resistor (21), - a second transistor (22) for resetting the voltage ramp across said capacitor (20), and - an adaptation means (23).   9. System according to one of the preceding claims, characterized in that the demodulation demultiplexing means (8) comprises: - a comparator (27) receiving said signal at two voltage levels (TM) coming from the optical receiver (10), - "AND" logic gates (281 - 28n) of 15 rows of first parity each receiving the signal with two voltage levels (TM) coming from said comparator (27) and selection signals (SEL1 - SELn) from rows of said first parity, - "AND" logic gates (281 - 28n) of 20 rows of second parity each receiving a signal with two inverted voltage levels (TMinv) coming from said comparator (27) and selection signals (SEL1 - SELn) of rows of said second parity, and - low-pass amplifiers (321 to 32n) delivering the electrical signals (S1 to Sn).   10. System according to claim 9, characterized in that the demultiplexing-demodulation means (8) further comprises a shift register (29) controlled by an oscillator (30) and operating in a loop to produce on the one hand, the selection signals (SEL 1 - SELn) and on the other hand, a synchronization selection signal (SEL0) intended to be supplied to a frame synchronization recovery means (31) producing a frequency control voltage of operation of said oscillator (30).   11. System according to claim 9 or 10, characterized in that the synchronization recovery means (31) comprises two monostable flip-flops (33a and 33b) producing a short pulse for each rising transition of the signal at two voltage levels (TM ), respectively of the inverted signal (Tminv), two delay means (34a and 34b) having the value Y4 and% / 2 of the duration of the synchronization cell (CELO), a logic gate "'AND" (35) followed by a phase comparator (36) which also receives a signal (SELOa) obtained by delaying the synchronization selection signal (SELO) via other delay means (37).