FR2845177B1 - Protocole de priorite d'acces pour systeme informatique - Google Patents

Protocole de priorite d'acces pour systeme informatique

Info

Publication number
FR2845177B1
FR2845177B1 FR0310909A FR0310909A FR2845177B1 FR 2845177 B1 FR2845177 B1 FR 2845177B1 FR 0310909 A FR0310909 A FR 0310909A FR 0310909 A FR0310909 A FR 0310909A FR 2845177 B1 FR2845177 B1 FR 2845177B1
Authority
FR
France
Prior art keywords
computer systems
access priority
priority protocol
protocol
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0310909A
Other languages
English (en)
Other versions
FR2845177A1 (fr
Inventor
Paul L Rogers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Development Co LP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Development Co LP filed Critical Hewlett Packard Development Co LP
Publication of FR2845177A1 publication Critical patent/FR2845177A1/fr
Application granted granted Critical
Publication of FR2845177B1 publication Critical patent/FR2845177B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/372—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a time-dependent priority, e.g. individually loaded time counters or time slot
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0811—Multiuser, multiprocessor or multiprocessing cache systems with multilevel cache hierarchies
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
FR0310909A 2002-09-23 2003-09-17 Protocole de priorite d'acces pour systeme informatique Expired - Fee Related FR2845177B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/261,460 US20040059879A1 (en) 2002-09-23 2002-09-23 Access priority protocol for computer system

Publications (2)

Publication Number Publication Date
FR2845177A1 FR2845177A1 (fr) 2004-04-02
FR2845177B1 true FR2845177B1 (fr) 2006-04-21

Family

ID=31993536

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0310909A Expired - Fee Related FR2845177B1 (fr) 2002-09-23 2003-09-17 Protocole de priorite d'acces pour systeme informatique

Country Status (2)

Country Link
US (1) US20040059879A1 (fr)
FR (1) FR2845177B1 (fr)

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DE10302287A1 (de) * 2003-01-22 2004-08-12 Micronas Gmbh Speichervorrichtung für eine Multibus-Architektur
US7062582B1 (en) * 2003-03-14 2006-06-13 Marvell International Ltd. Method and apparatus for bus arbitration dynamic priority based on waiting period
US20050138281A1 (en) * 2003-12-18 2005-06-23 Garney John I. Request processing order in a cache
US7624396B1 (en) * 2004-02-26 2009-11-24 Sun Microsystems, Inc. Retrieving events from a queue
KR101172844B1 (ko) * 2004-06-04 2012-08-10 코닌클리케 필립스 일렉트로닉스 엔.브이. 제 1 당사자를 제 2 당사자에게 인증하는 인증방법
US20060020760A1 (en) * 2004-07-22 2006-01-26 International Business Machines Corporation Method, system, and program for storing sensor data in autonomic systems
DE102005013001A1 (de) * 2005-03-21 2006-09-28 Siemens Ag Verfahren zur agentenbasierten Zuordnung von Komponenten zu Aufträgen im Rahmen eines Logistikprozesses
JP2008102599A (ja) * 2006-10-17 2008-05-01 Renesas Technology Corp プロセッサ
JP4984846B2 (ja) * 2006-11-22 2012-07-25 富士通株式会社 業務フロー管理プログラム、業務フロー管理装置、および業務フロー管理方法
DE602007010015D1 (de) * 2007-12-11 2010-12-02 Ericsson Telefon Ab L M Verfahren und Vorrichtung für die Erzeugung von Prioritäten in einem Multiprozessor-Gerät
CN102282546B (zh) * 2008-11-10 2016-04-06 新思科技有限公司 资源控制
CN102428450A (zh) 2009-03-11 2012-04-25 新诺普系统公司 用于资源控制的系统和方法
US8667197B2 (en) * 2010-09-08 2014-03-04 Intel Corporation Providing a fine-grained arbitration system
US8904115B2 (en) * 2010-09-28 2014-12-02 Texas Instruments Incorporated Cache with multiple access pipelines
US9559889B1 (en) * 2012-10-31 2017-01-31 Amazon Technologies, Inc. Cache population optimization for storage gateways
KR102396309B1 (ko) * 2015-11-06 2022-05-10 삼성전자주식회사 데이터 요청을 제어하기 위한 장치 및 방법
WO2017180032A1 (fr) * 2016-04-12 2017-10-19 Telefonaktiebolaget Lm Ericsson (Publ) Planification de processus dans un système de traitement doté d'au moins un processeur et de ressources matérielles partagées
CN108270693A (zh) * 2017-12-29 2018-07-10 珠海国芯云科技有限公司 网站访问的自适应优化疏导方法及装置
US10831668B2 (en) * 2018-08-30 2020-11-10 International Business Machines Corporation Detection and prevention of deadlock in a storage controller for cache access via a plurality of demote mechanisms
US10613981B2 (en) * 2018-08-30 2020-04-07 International Business Machines Corporation Detection and prevention of deadlock in a storage controller for cache access
US11237985B2 (en) * 2019-10-29 2022-02-01 Arm Limited Controlling allocation of entries in a partitioned cache
WO2022161619A1 (fr) * 2021-01-29 2022-08-04 Huawei Technologies Co., Ltd. Dispositif de commande, agencement de calcul et procédé pour augmenter les résultats de lecture dans une mémoire cache à files d'attente multiples

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US5440752A (en) * 1991-07-08 1995-08-08 Seiko Epson Corporation Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU
US5790813A (en) * 1996-01-05 1998-08-04 Unisys Corporation Pre-arbitration system allowing look-around and bypass for significant operations
US5862355A (en) * 1996-09-12 1999-01-19 Telxon Corporation Method and apparatus for overriding bus prioritization scheme
US5948081A (en) * 1997-12-22 1999-09-07 Compaq Computer Corporation System for flushing queued memory write request corresponding to a queued read request and all prior write requests with counter indicating requests to be flushed
US6622224B1 (en) * 1997-12-29 2003-09-16 Micron Technology, Inc. Internal buffered bus for a drum
US6286083B1 (en) * 1998-07-08 2001-09-04 Compaq Computer Corporation Computer system with adaptive memory arbitration scheme
US6505229B1 (en) * 1998-09-25 2003-01-07 Intelect Communications, Inc. Method for allowing multiple processing threads and tasks to execute on one or more processor units for embedded real-time processor systems
US6215703B1 (en) * 1998-12-04 2001-04-10 Intel Corporation In order queue inactivity timer to improve DRAM arbiter operation
US6425060B1 (en) * 1999-01-05 2002-07-23 International Business Machines Corporation Circuit arrangement and method with state-based transaction scheduling
US6330646B1 (en) * 1999-01-08 2001-12-11 Intel Corporation Arbitration mechanism for a computer system having a unified memory architecture
US6438629B1 (en) * 1999-02-02 2002-08-20 Maxtor Corporation Storage device buffer access control in accordance with a monitored latency parameter
US6330647B1 (en) * 1999-08-31 2001-12-11 Micron Technology, Inc. Memory bandwidth allocation based on access count priority scheme
US6499090B1 (en) * 1999-12-28 2002-12-24 Intel Corporation Prioritized bus request scheduling mechanism for processing devices
US6636949B2 (en) * 2000-06-10 2003-10-21 Hewlett-Packard Development Company, L.P. System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing
EP1182550A3 (fr) * 2000-08-21 2006-08-30 Texas Instruments France Arbitrage de priorité orienté tâches
US6745293B2 (en) * 2000-08-21 2004-06-01 Texas Instruments Incorporated Level 2 smartcache architecture supporting simultaneous multiprocessor accesses
US20020087614A1 (en) * 2000-08-31 2002-07-04 Andrej Kocev Programmable tuning for flow control and support for CPU hot plug
KR100803114B1 (ko) * 2000-11-30 2008-02-14 엘지전자 주식회사 메모리 중재 방법 및 시스템
US6728790B2 (en) * 2001-10-15 2004-04-27 Advanced Micro Devices, Inc. Tagging and arbitration mechanism in an input/output node of a computer system

Also Published As

Publication number Publication date
US20040059879A1 (en) 2004-03-25
FR2845177A1 (fr) 2004-04-02

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Legal Events

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ST Notification of lapse

Effective date: 20140530