FR2828971A1 - TWO-PHASE SIGNAL DECODING CIRCUIT - Google Patents

Abstract

A circuit (200) and associated method for decoding a biphase signal (DALIINO) is provided. According to the invention, the circuit (200) essentially comprises: a precharging register (210), for precharging a pair of states of the biphase signal, one state of the pair of states being precharged on each pulse of a signal periodic precharge (PREC), and- a verification circuit (220), for comparing the two states of the pair of states and providing an active error signal (ER) if the two states are equal. Application to electronic ballast control circuits for lamps.

Description

MMS message header.

  TWO-PHASE SIGNAL DECODING CIRCUIT

  The invention relates to a circuit for decoding two-phase signals and can be used in a circuit for transmitting or receiving such signals. The invention is particularly advantageous for the reception of signals according to the DALI communication protocol (from the English Digital Addressable Lighting Interface), used in particular for the control of electronic ballasts. The invention can more generally be used for the reception of

all types of two-phase signals.

  Ballasts are electronic circuits used to control fluorescent lamps, mercury lamps or more generally any type of discharge lamps. The ballasts can be controlled by digital signals, for example according to the DALI communication protocol, defined in particular in an IEC standard of January 10, 2000. 'According to the DALI communication protocol, a digital signal received takes the form of a frame comprising a start bit, a 16-bit binary word and two end bits, ie a 19-bit frame. The 16-bit word includes, for example, an 8-bit address and an 8-bit instruction. In return, a transmitted digital signal is in the form of an 11-bit frame comprising a start bit, an 8-bit datum and two

end bits.

  According to the DALI communication protocol, each bit of a frame, received or transmitted by the control circuit, is coded in the form of a two-phase signal, that is to say in the form of a signal taking 2 states. successive. A logic "1" is coded in the form of a signal (FIG. 1, ref. 110A, 11Ob) which is equal to "O" during a 1st phase, and which is equal to "1" during a 2nd phase. In the same way, a logical "O" is coded in the form of a signal (figure 1, ref. 120a, 120b) which is equal to "1" during a 1st phase and which is equal to "0" during a 2nd phase. A start bit (130a, 130b) is coded in the form of a signal equal to "O" during a 1st phase and equal to "1" during a 2nd phase. Finally, an end bit (140a, 140b) is coded as a signal

equal to "1" during the 2 phases.

  Thus, all the bits of a frame are coded as follows: a logical "1" is coded by the pair of states "01", a logical "0" is coded by the pair "10", a bit of start is coded by pair "01" and an end bit is coded by pair "11". A frame of nineteen bits (respectively onse bits) is thus coded in the form of a binary number of thirty eight states

(respectively twenty-two states).

  The frames thus coded are transmitted at the speed of 1200 bits per second, or 2400 states per second since each bit is coded in the form of two states. The transmission time of a digit of a frame is

  thus equal to T = 1/2400 or T = 416.37 ps.

  An object of the invention is to provide a circuit for decoding such two-phase signals, capable of receiving such signals and of extracting information therefrom.

2s relevant.

  Another object of the invention is to provide a circuit for decoding such signals, capable of checking the

good reception of such signals.

  With these objectives in view, the invention relates to a decoding circuit for decoding a biphase signal, characterized in that it comprises: - a preload register, for preloading a pair of states of the biphase signal to be decoded, a state of the pair of states being preloaded on each pulse of a periodic preload signal, and - a verification circuit, to compare the two states of the pair of states and provide a signal

  error active if the two digits are equal.

  The decoding circuit of the invention thus makes it possible to receive and verify the reception of the pairs of states of the two-phase signals: the circuit of the invention indicates, after the reception of each pair of states, whether the states have been correctly received or not. If the two states of the same pair are identical, this in fact means that at least one of the states is wrong: this observation is simply deduced from the manner of coding a biphase signal, as we have seen previously. As the biphase signal is received, the verification circuit will thus check, pair by pair, all the pairs of states contained in the frame

of a biphase signal.

  According to a preferred embodiment, the verification circuit also provides a decoded signal representative of a pair of states stored in the

preload register.

  The verification circuit thus provides, after verification, not all the states of the biphase signal, but only the relevant information contained in the.

two-phase signal.

  The decoding circuit according to the invention is advantageously supplemented by a storage circuit, for storing the decoded signal, on each pulse of a validation signal with a period equal to twice the period of the precharge signal. The storage circuit can for example be of the register type or

memory.

  At each pulse of the validation signal, the storage circuit thus stores, bit by bit, all the bits of the word contained in the frame of the

  biphase signal, as we will see better later.

  3s It will be noted that the decoding circuit according to the invention makes it possible to limit the size of the memorization circuit to the tail le of the word contained in the frame of the.

  two-phase signal (for example 16 bits or twice 8 bits).

  The decoding circuit is further advantageously supplemented by a delay circuit producing an end signal after a predefined time, to indicate the end of the two-phase signal. The delay circuit is initialized at the start of the two-phase signal, for example during reception

the start bit of a frame.

  The end signal will for example be taken into account to cancel a possible active error signal when receiving an end bit (coded by a pair of states

identical "11").

  According to one embodiment, the preload register is a shift register, comprising a serial input on which the biphase signal to be decoded is applied, and a parallel output connected to a parallel data input of the verification circuit. The precharge register comprises at least two bits, necessary to store at least one pair of states which will be checked by the verification circuit. The preload register can also include a number

bit higher, for example 4.

  According to one embodiment, the verification circuit comprises a first gate comprising two 2s inputs connected to two successive lines of the parallel data output of the preload register. The function of the first gate is to check whether the states of a pair of states contained in the preload register are different (correct reception) or

identical (bad reception).

  If the preload register comprises at least four bits, the verification circuit is advantageously completed by: - a second gate comprising two inputs connected to two other successive lines of the parallel data output of the preload register, and s - a third gate comprising two inputs connected respectively to the output of the first

  door and at the exit of the second door.

  This variant makes it possible to detect and store the two end bits indicating the end of a frame of the signal to be decoded. Furthermore, if the decoding circuit comprises a delay circuit, the verification circuit is advantageously completed by a fourth gate comprising an input connected to a sort of the third gate, an input to which the end signal is applied, and a output on which the error signal is produced. Thus, when the end signal is active, the error signal is inactive, thus indicating that the last two states received were received correctly, regardless of the value of these states. This variant of the verification cTrcuit thus makes it possible not to signal an error when the end bits, coded by two identical states and equal to "1", are received in the register of

preload.

  The decoding circuit is further improved by the addition of a filter, for filtering the biphase signal to be decoded, the filter comprising an input to which the biphase signal to be decoded is applied and an output connected to the serial input of the register of preload. The filter eliminates possible disturbances

  brief which could appear on the signal to decode.

  According to one embodiment, the filter includes: - a sample register, for storing samples of a digit of a pair of digits of the biphase signal to be decoded, - a set of logic gates to calculate an average value of the samples contained in the sample register and provide said average value to the

preload register.

  The invention also relates to a method for decoding a biphase signal, which can, for example but not only, be implemented using a circuit.

  decoding as described above.

  The method according to the invention notably comprises: a step of precharging a pair of states of the biphase signal, a state of the pair of states being preloaded at each pulse of a periodic precharging signal (PREC), - a step of comparing the two states of the preloaded state pair, and - a step of supplying an error signal (ER) which is active if the two states are equal or inactive

s 1no.

  The method is for example supplemented by a step of supplying a decoded signal representative of the

preloaded state pair.

  Advantageously, a step is added of memorizing the decoded signal, with each pulse of a periodic validation signal, of period equal to two

  times the period of the precharge signal.

  A time measurement step, initialized at the start of the biphase signal, can also be added, to produce an end signal after a predefined time,

  2s indicating the end of the two-phase signal.

  The method can finally comprise a step of filtering the two-phase signal, carried out before the precharging step. The subject of the invention is also a circuit for transmitting and receiving biphase signals coded according to a DALI communication protocol, characterized in that it comprises a decoding circuit as described above. The invention finally relates to a control circuit of an electronic ballast receiving piloting signals in the form of biphase signals coded according to a DALI communication protocol, characterized in that it

  includes a decoding cTrcuit as described above.

  The invention and the advantages which ensue from it will become more clearly apparent on reading the

  description which follows of exemplary embodiments of a

  two-phase signal decoding circuit, according to

  the invention. The description should be read with reference to

  attached drawings in which: - Figure 1, already described, presents two-phase signal diagrams, - Figure 2 is a block diagram of a decoding circuit according to the invention, and - Figures 3 and 4 are diagrams electronics of an embodiment of the circuit of Figure 2, - Figures 5A to 5E are timing diagrams of signals at different points of the circuit of Figure 2, - Figure 6 shows a possible improvement of the circuit of Figure 2, and - Figures 7A to 7D are timing diagrams of

  signals at different points in the circuit of figure 6.

  The decoding circuit 200 of FIG. 2 essentially comprises a precharge register 210 and a

verification circuit 220.

  Register 210 includes a serial data input E, a clock input CP and a parallel data output S. A DALIIN signal is applied to input E of register 210. The DALIIN signal is a two-phase signal, containing digital data in the form of nineteen bit frames coded by binary numbers of thirty eight states. A precharge signal PREC, periodic, is applied to the CP input. The PREC signal has a period equal to T = 416.67 ps second, i.e. the transmission time

of a frame state.

  In the example, the register 210 is a 4-bit shift register as shown in FIG. 3. The register 210 thus comprises four flip-flops 300 to 303 of type D connected in series, each comprising a data input D, a CP clock input and Q data output. The input D of the flip-flop 300 is connected to the input E of the register 210, the inputs D of the flip-flops 301 to 303 are respectively connected to the outputs Q of the flip-flops 300 to 302. The inputs CP of all the flip-flops 300 to 303 are connected together to the CP input

  of register 210 to receive the PREC command signal.

  Finally, the outputs Q of flip-flops 300 to 303 are connected to serial outputs S0 to S3 forming the output

S parallel to register 210.

  The operation of register 210 is conventional: at each active edge of the signal PREC, a digit of the signal DALIIN is entered in least significant bit in register 210, and the four bits contained in register 210 are supplied on its output S. The verification circuit 220 includes a data input E, parallel, connected to the output S of the register 210, a serial data output OUT and a

information output I.

  It will be recalled that, according to the DALI protocol, a logical "1" is coded by the pair of states 01 "and that an" O "is coded by the pair" 10 ". The data is transmitted to the circuit 200 in the form 19-bit frames comprising a start bit (equal to "1" and coded "01"), a 16-bit word, and two end bits. All bits of the word

  16 bits are coded by the pair "01" or the pair "10".

  The circuit 220 makes it possible to check whether the states (more precisely the pairs of states) of the coded frame are correctly required or not. For this, the circuit 220 compares two states previously received and stored in the register 210 in 3s. If the two states are different, then the circuit 220 provides an inactive ER signal (in a first logic state, for example "1") on its output I. On the contrary, if the two states are identical, then the circuit 220 supplies an active ER signal (in a second logic state, in the example "0"). In parallel, the circuit 220 supplies, on its data output OUT, a data bit representative of the two compared states. In the example described, the data bit supplied on the output OUT is the bit stored in flip-flop 302 of register 210. After the reception of a pair of states, an inactive ER signal indicates that the two digits are different and therefore that the corresponding bit of the frame has been correctly requested. On the contrary, an active ER signal after the reception of a pair of states indicates that the two states of the pair of received states are identical and therefore that the corresponding bit of the frame has not been correctly received. Thus, the value of the signal ER is preferably taken into account after the reception of a pair of states and not after the reception of the first state

of a pair of states.

  The ER signal is also used: it can be used for example to stop operation

  of circuit 200 and / or reset it.

  An exemplary embodiment of the circuit 220 is detailed in FIG. 4. It comprises two logic gates of the OU-Exclusive type 410, 420 and a logic gate of the ET 430 type, each gate comprising two

data input and output.

  The two inputs of gate 410 are connected to inputs E0, E1 of circuit 220, and the two inputs of gate 420 are connected to inputs E2, E3 of circuit 220, the inputs E0 to E3 forming the parallel input E of circuit 220. The respective outputs of doors 410, 420 are connected to the inputs of door 3s 430. Finally, the input E2 is connected to the output OUT of circuit 220 and the output of door 430 is connected to

the output I of circuit 220.

  The overall operation of the decoding circuit 200 according to the invention will now be detailed in the context of a digital example, in relation to the

timing diagrams of Figures 5A to 5E.

  In the example, the frame requested (FIG. 5A) comprises a start bit (coded by the pair "0l"), a 16-bit word comprising logical "l" (coded "0l") in most significant bits strong and logical "0" (coded "l0") in least significant bits, and two end bits (coded "ll"). Figure 5B shows the shape of the PREC signal. Finally, FIGS. 5C, 5D show the content of the register 210, and the evolution of the signal OUT at the output of the

circuit 220.

  We will also assume that initially all

  the flip-flops of circuit 200 are initialized at "l".

  At time T0, the circuit of FIG. 2 is activated and the reception of the DALIIN signal begins. Between T0 and TO + 2T, the start bit is required: the DALIIN signal is equal to "0" during time T. then it is equal to "l"

between T0 + T and TO + 2T.

  At time A0, between T0 and T0 + T, the signal PREC is active and the signal DALIIN, equal to 0, is

  memorized in the 1st flip-flop 300 of register 210.

  At the instant Al = A0 + T, the signal PREC is again active, and the signal DALIIN, now equal to l, is memorized in the 1st flip-flop 300, the "0" previously memorized being shifted in flip-flop 301: the first

  pair of states is thus stored in register 210.

  Furthermore, the input El of circuit 220 is at "0" and the input E0 is at "l": circuit 220 provides an inactive ER signal on its output, indicating correct reception of the first pair of digits "0l ", relative 3s to the start of frame bit. Finally, in parallel, the circuit

  220 produces a logical "l" on its OUT output.

  At the instant A) = A0 + 2T, the signal PREC is again active, and the signal DALIIN, now equal to 0, is stored in the 1st flip-flop 300, the previous content of flip-flop 300, respectively of flip-flop 301 , being S shifted in flip-flop 301, respectively flip-flop

  302. The OUT signal is equal to "0".

  At the instant A3 = A0 + 3T, the signal PREC is again active, and the signal DALIIN, now equal to 1, is memorized in the 1st flip-flop 300, the "0" previously memorized being shifted in flip-flop 301: the second pair of states is stored in register 210, which

  thus contains the number "0101" (ref. 510, figure 5C).

  Furthermore, the input E1 of circuit 220 is at "0" and its input E0 is at "1": circuit 220 provides an inactive ER signal on its output, indicating correct reception of the number "01" relating to a bit equal to "1". In parallel,

  the OUT signal goes to "1" (ref. 520, figure 5C).

  At the instant A4 = A0 + 4T, the signal PREC is again active, and the signal DALIIN, again equal to 0, is memorized in the 1st flip-flop 300, the previous content of flip-flops 300 to 302 being shifted in the flip-flops 301 to

  303. The OUT signal is equal to "1".

  At the instant A5 = A0 + 5T, the signal PREC is again active, and the signal DALIIN, now equal to 1, is memorized in the 1st flip-flop 300, the "0" previously memorized being shifted in flip-flop 301: the third pair of states is stored and register 210 thus contains the number "0101" (ref. 530, FIG. 5C). Furthermore, the inputs E1, E0 of the circuit 220 are respectively at 0 and at 1: the circuit 220 provides an inactive ER signal on its output, indicating correct reception of the number "01" relating to a bit equal to "1". In

  parallel, the OUT signal goes to 1 (ref. 540, figure 5C).

  At time A6, the active PREC signal causes the preload of a new bit in register 210 (in

example a "0").

  At time A7, the active PREC signal also causes the preload of a new bit in the register 210 (in the example a "1"). Circuit 220 provides an inactive ER signal, indicating good reception, and the content of flip-flop 302 (in this case a "1") is produced on the output OUT: the 2nd bit (a "1") of the word

  16 bits contained in the received frame are thus transmitted.

  The set is repeated until complete reception

  of all the bits of the received frame.

  Improvements can be made easily

  on the decoding circuit 200 of FIG. 2.

  A first improvement consists in adding a storage circuit 230 (shown in dotted lines in FIG. 2), to store the bits of the 16-bit word contained in the requested frames, as and when

  said bits are supplied by circuit 220.

  In one example, the storage circuit 230 (FIG. 2) comprises a serial data input E connected to the data output OUT of circuit 220 and a clock input CP to which is applied a

VAL signal for validation.

  The signal VAL is a periodic signal, of period equal to twice the period of the signal PREC, here 2T = 833.33 ps. An example of signal VAL is shown in FIG. 5E. In this example, an active edge of the signal VAL is produced on receipt of the second state of each pair of states. Recall that the second state of a pair of states corresponds to the value of the coded bit: for example the pair "10", whose second state is equal

at "0", encodes the bit "0".

  In the example, the circuit 230 is produced by a shift register of 16 bits, clocked by the signal

  VAL. Such a register is similar to register 210.

  3s Thus, at each active edge of the signal VAL, the circuit 230 stores a bit of the 16-bit word contained in the frame requested. Depending on the applications envisaged, the 16-bit word stored in the register 230 may subsequently be stored in two 8-bit registers or in a memory, or may be used by any other circuit. It should be noted that circuit 230 is not essential for the operation of circuit 200, in particular if the words produced by circuit 220 are used.

directly by another element.

  In practice, the circuit 230 could be an input register of an element (calculation circuit, control circuit, etc.) using, moreover, the 16-bit word requ). Note, however, that if memorization of the required bits is necessary, then the decoding circuit 200 according to the invention makes it possible to limit the size of the memorization circuit 230 to 16 bits (or twice 8 bits), while a circuit conventional reception process uses a 32-bit register capable of

  memorize all the states of the received biphase signal.

  Another improvement to the circuit in FIG. 2 consists in adding a delay circuit 240 (shown in dotted lines in FIG. 2) comprising a clock input 2s to which the signal VAL is applied, and an output connected to an input FIN of circuit 220. Circuit 240 is activated when circuit 220 decodes the frame start bit (which corresponds to the 1st activation of the ER signal). Circuit 240 produces a

  end signal after a preset time, equal to 32T.

  The circuit 240 thus has the function of measuring the time necessary for the reception of the 16-bit word contained in a frame (the 16-bit word being coded by 16 pairs of states, ie a reception duration of 32T), then 3 s to signal to circuit 220, by means of the signal FIN (in the active example at 1), that all the bits of the

frame have been requested.

  The circuit 240 is produced according to known diagrams. In one example, the cTrcuit 240 is produced in the form of a four-bit counter, which counts pulses of the signal VAL, of period 2T, and which produces

  the signal FIN when it reaches a predefined value.

  More generally, circuit 240 can be produced by any delay circuit, capable of transmitting a signal FIN at

  after a predetermined time equal to 32T.

  If a delay circuit 240 is added, the circuit 220 must be completed accordingly to take into account the signal FIN. In the example of FIG. 4, the circuit 220 is completed by the addition of an OR gate 440 (shown in dotted lines in FIG. 4), comprising two inputs connected respectively to the FIN input of the circuit 220 and to the output of gate 410, gate 440 also comprising an output connected to output I of circuit 220. Thus, if the FIN signal is active, gate 440 provides a logical "l", whatever the values applied to the inputs EO to E3 of circuit 220. The decoding circuit 200 can also be improved by adding a filter 250 (shown in dotted lines in FIG. 2) comprising an input to which the coded signal DALIINO is applied, an input CP clock on which is applied a sampling signal ECH, of period T. and a data output S connected to the data input of the register

preload 210.

  The filter 250 calculates an average value of the DALIINO signal during a period T (between O + n * T and O + (n + l) * T for example, n being an integer), and supplies this average value to the register 210. Such a 3s filter thus makes it possible to overcome disturbances

  parasites possibly present on the DALIINO signal.

  An example of a filter that can be used in the invention is shown in FIG. 6. It includes three D flip-flops 610, 620, 630, three AND gates 640, 650, 660 with two inputs and one output, and one OR gate with three

S inputs and one output.

  Flip-flops 610, 620, 630 are connected in series: input D of flip-flop 610 is connected to input E of filter 250 to receive the DALIINO signal, inputs D of flip-flops 620, 630 are connected to outputs Q of flip-flops 610, 620. The CP clock inputs of all flip-flops 610, 620, 630 are connected together to the CP input of filter 250 to receive the

ECH signal.

  One input of door 640 is connected to the Q output of flip-flop 610 and the other input of door 640 is connected to the Q output of flip-flop 620. An input of door 650 is connected to output Q of the flip-flop 610 and the other input of gate 650 is connected to output Q of flip-flop 630. One input of gate 660 is connected to output Q of flip-flop 620 and the other input of gate 660 is connected to the output Q of the flip-flop 630. Finally, the inputs of door 670 are connected respectively to the output of door 640, to the output of door 650 and to the output 2s of door 660, the output of door 670 being

  connected to the output S of the filter 250.

  The operation of the filter 250 is explained below in an example. Figure 7A shows the DALIINO signal between TO + n * T and TO + (n + 2) * T, n being an integer. In the example, the DALIINO signal is equal to "O" between TO + n * T and TO + (n + l) * T, then it is equal to "1" between TO + (n + l) * T and TO + ( n + 2) * T. Small disturbances 711, 712, 713 punctually modify the value of

DALIINO.

  The signal ECH (FIG. 7B) is periodic, of period T. In the example, it comprises three pulses 721, 722, 723 per period. The signal PREC (FIG. 7C), used by the register 210, is also of period T. it comprises a single pulse 725 per period, which appears after the pulse 723. The signals ECH, PREC, as well as the signal VAL, are by example provided by a control circuit, not described here. These signals are for example produced from a global clock signal of a component using the circuit of the invention, and which has a frequency multiple of the frequency of the signals

  ECH, PREC, VAL, for example a frequency equal to 16 / T.

  During the three pulses 721, 722, 723 on the ECH signal, three values of the DALIINO signal are stored in flip-flops 610, 620, 630. The gates 640, 650, 660, 670 calculate at any time an average value of the values contained in flip-flops 610, 620, 630 and said average value is supplied on the output S of filter 250. During the next PREC 725 pulse, the average value supplied by filter 250 is memorized

in register 210.

  In the example, during pulses 721, 722 on the signal ECH, the signal DALIINO is equal to "O" and two "O" are memorized in the flip-flops of the filter 250, then during pulse 723, a "1 "is stored in said

  flip-flops, due to the presence of disturbance 712.

  2s Doors 640, 650, 660, 670 calculate an average value from the content of flip-flops 610, 620, 630, a logical "O" is thus provided on the output of filter 250, and it is memorized in register 210 during of pulse 725 on the PREC signal. The effects of

  perturLation 712 have been deleted.

  Changes can also be made

  on the decoding circuit 200 of FIG. 2.

  The output of register 210 can be modified. In fact, in the example above, the output S2 of the register 210 is connected to the input of the register 230, in order to store a bit of the signal DALIIN in the register 230 at each pulse VAL. It would also be possible to connect one of the other outputs (SO, S1 or S3) of register 210 to the input of register 230. If necessary, we will simply make sure to modify the signal VAL accordingly, so that the states relevant in the DALIIN signal and corresponding to the bits of the 16-bit word encoded in the DALIIN signal are supplied by the circuit

220 at the appropriate time.

  The size of register 210 can also be changed. Indeed, the register 210 used in the examples described above is a four-bit register. Its essential role is to store two by two the states of the received DALIIN signal, so that these pairs of states are tested by the cTrcuit 220. The advantage of using a register 210 of four bits and of being able to memorize completely the four states encoding the end bits. It would however be possible to choose a register 210 comprising only 2 bits, or on the contrary a register of size greater than four. If necessary, circuit 220 should be modified accordingly. For example, if a two bit register 210 is chosen, the gates 420, 430 of circuit 220 become useless and can be deleted. In this case, the output of door 410 is connected directly to the output

I of cTrcuit 220.

  The control signals PREC, VAL, ECH (supplied by a control circuit not shown) can also be modified, they must however all be three periodic, the signals PREC, ECH of period T and the signal VAL of period 2T. These signals can be obtained from a clock signal external to the circuit and from a set of logic gates and / or delay circuits. In the examples above, these signals are all impulse signals. It is however possible to replace all or part of these signals by square signals for example, the rising (or falling) edges of such signals being in

  this case taken into account for the circuit control.

/

Claims (12)

  1. Decoding circuit (200) for decoding a biphase signal (DALIIN0), characterized in that it comprises: - a preload register (210), for preloading a pair of states of the biphase signal, a state of the pair of states being preloaded with each pulse of a periodic precharge signal (PREC), and - a verification circuit (220), for comparing, the two states of the pair of states and providing a signal   (ER) error active if the two states are equal.   2. Circuit according to claim 1, characterized in that the verification circuit (220) also provides a decoded signal (OUT) representative of the pair of states   stored in the preload register (210).   3. Circuit according to claim 2, characterized in that it also comprises a storage circuit (230), for storing the decoded signal (OUT), on each pulse of a validation signal (VAL) periodic, of period equal to two times the signal period of preload (PREC).   4. Circuit according to one of claims 1 to 3,   characterized in that it also comprises a delay circuit (240) producing an end signal (END) after a predefined time, to indicate the end of the two-phase signal (DALIIN0), the delay circuit (240) being initialized at start of the two-phase signal (DALIIN0).   5. Circuit according to one of claims   above, characterized in that it also comprises a filter (250), for filtering the biphase signal (DALIIN0), the filter (250) comprising an input to which the biphase signal (DALIINO) is applied and an output connected to the serial entry of the register of preload (210).   6. Method for decoding a biphase signal (DALIINO), characterized in that it comprises: - a step of precharging a pair of states of the biphase signal, a state of the pair of states being preloaded at each pulse of a periodic precharge signal (PREC), - a step of comparing the two states of the preloaded state pair, and - a step of providing an error signal (ER) which is active if the two states are equal or inactive if not.   7. Method according to claim 6, characterized in that it also comprises a step of supplying a decoded signal (OUT) representative of the pair of states preloaded.   8. Method according to claim 7, characterized in that it also comprises a step of memorizing the decoded signal (OUT), on each pulse of a periodic validation signal (VAL), of period equal to twice.   the period of the precharge signal (PREC).   9. Method according to one of claims 6 to 8,   characterized in that it also includes a time measurement step, initialized at the start of the biphase signal (DALIINO), to produce an end signal (END) after a predefined time, indicating the end of the biphase signal (DALIINO).   3s 10. Method according to one of claims 6 to 9,   characterized in that it also comprises a step of / filtering the biphase signal (DALIINO), carried out before the preload step.   11. Circuit for transmitting and receiving biphase signals coded according to a DALI communication protocol, characterized in that it comprises a decoding cTrcuit   according to one of claims 1 to 5.   12. Control circuit of an electronic ballast receiving control signals in the form of biphase signals coded according to a DALI communication protocol, characterized in that it comprises a decoding circuit