FR2824647B1 - Systeme d'adressage de memoire pour bus d'interconnexions de composants peripheriques - Google Patents
Systeme d'adressage de memoire pour bus d'interconnexions de composants peripheriquesInfo
- Publication number
- FR2824647B1 FR2824647B1 FR0203396A FR0203396A FR2824647B1 FR 2824647 B1 FR2824647 B1 FR 2824647B1 FR 0203396 A FR0203396 A FR 0203396A FR 0203396 A FR0203396 A FR 0203396A FR 2824647 B1 FR2824647 B1 FR 2824647B1
- Authority
- FR
- France
- Prior art keywords
- bus
- peripheral component
- memory addressing
- addressing system
- component interconnections
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000002093 peripheral effect Effects 0.000 title 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0107037A GB2373598B (en) | 2001-03-20 | 2001-03-20 | Peripheral component interconnect bus memory address decoding |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2824647A1 FR2824647A1 (fr) | 2002-11-15 |
FR2824647B1 true FR2824647B1 (fr) | 2005-07-08 |
Family
ID=9911224
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0203396A Expired - Fee Related FR2824647B1 (fr) | 2001-03-20 | 2002-03-19 | Systeme d'adressage de memoire pour bus d'interconnexions de composants peripheriques |
Country Status (5)
Country | Link |
---|---|
US (1) | US20020138709A1 (fr) |
AU (1) | AU784334B2 (fr) |
CA (1) | CA2371509A1 (fr) |
FR (1) | FR2824647B1 (fr) |
GB (1) | GB2373598B (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6931457B2 (en) * | 2002-07-24 | 2005-08-16 | Intel Corporation | Method, system, and program for controlling multiple storage devices |
GB2444745B (en) * | 2006-12-13 | 2011-08-24 | Advanced Risc Mach Ltd | Data transfer between a master and slave |
US9317446B2 (en) * | 2014-09-23 | 2016-04-19 | Cisco Technology, Inc. | Multi-level paging and address translation in a network environment |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0291741A (ja) * | 1988-09-29 | 1990-03-30 | Toshiba Corp | アドレスバスの切換制御方式 |
US5363500A (en) * | 1990-01-25 | 1994-11-08 | Seiko Epson Corporation | System for improving access time to video display data using shadow memory sized differently from a display memory |
US5668973A (en) * | 1995-04-14 | 1997-09-16 | Ascom Hasler Mailing Systems Ag | Protection system for critical memory information |
GB2329984B (en) * | 1997-10-01 | 2002-07-17 | Thomson Training & Simulation | A Multi-Processor Computer System |
US6317657B1 (en) * | 1998-08-18 | 2001-11-13 | International Business Machines Corporation | Method to battery back up SDRAM data on power failure |
JP3206570B2 (ja) * | 1998-11-12 | 2001-09-10 | 日本電気株式会社 | Pci機能拡張制御装置、及びpci機能拡張制御方法 |
-
2001
- 2001-03-20 GB GB0107037A patent/GB2373598B/en not_active Expired - Fee Related
-
2002
- 2002-02-12 CA CA002371509A patent/CA2371509A1/fr not_active Abandoned
- 2002-03-19 FR FR0203396A patent/FR2824647B1/fr not_active Expired - Fee Related
- 2002-03-20 AU AU27535/02A patent/AU784334B2/en not_active Ceased
- 2002-03-20 US US10/101,527 patent/US20020138709A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
US20020138709A1 (en) | 2002-09-26 |
GB0107037D0 (en) | 2001-05-09 |
FR2824647A1 (fr) | 2002-11-15 |
CA2371509A1 (fr) | 2002-09-20 |
GB2373598B (en) | 2004-12-29 |
GB2373598A (en) | 2002-09-25 |
AU784334B2 (en) | 2006-03-16 |
AU2753502A (en) | 2002-09-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20091130 |