FR2791217A1 - Mobile telephone power management circuit includes fast and slow clock circuits, enabling reduction of power consumption in standby mode - Google Patents

Abstract

The circuit offers a standby mode, in which the telephone still maintains synchronization with the mobile network. The mobile telephone (1) has an aerial (2) communicating with the network (3). In order to reduce the consumption of current by the mobile telephone circuit in its standby mode, first (11) and second (12) circuits are used providing rapid and slow clock pulses respectively. The slow clock signal is regularly sampled by the rapid clock signal before cutting the supply of the first circuit (11) when the telephone is to be changed into its standby mode. The telephone receives information from the network indicating a difference between a known date and a previous date. Processing with the slow and rapid clock signals, and this date information, enables the telephone to remain in synchronism with the network.

Description

Standby method in a mobile phone The present invention has for

  subject a standby process in a mobile phone. One of the objects of the invention is to put a mobile telephone in a standby state while ensuring lower energy consumption. This reduction in energy consumption allows an increase in the autonomy of a mobile phone power source. The invention could equally well apply to any portable device, such as for example a portable computer. A portable device is a device with an independent power source. Thus the portable device can move without limit of space while remaining

  powered by the power source.

  Currently, standby methods are implemented comprising a first circuit providing a fast clock signal and a second circuit providing a slow clock signal. Standby can also be ensured by leaving only a minimum of possible functions supplied in cases where there is no slow clock signal. The fast clock signal is of frequency greater than a frequency of the slow clock signal. With these methods, a microprocessor of a mobile telephone is clocked, during an active state, by the first circuit. An active state is a state in which a mobile telephone can communicate with a mobile telephone network with which it is linked by radio. When a mobile phone does not exchange information with a network then it can be put in a standby state. In this standby state, a fast clock signal is exchanged which cadences the microprocessor with a slow clock signal. To achieve this, a clock input from the microprocessor of the first circuit is switched to the second circuit. Thus, the microprocessor is clocked by a

slow clock signal.

  Such a method presents problems. In fact, during a standby state, only a transceiver device of the mobile telephone is deactivated, the other circuits such as the microprocessor or the clock circuits remain supplied by a power source. Thus, energy consumption during a standby state of the mobile telephone remains high. One of the elements that consumes the most energy is the first circuit providing the fast clock signal. A current value of

  consumption of this first circuit is around 2 mA.

  In the state of the art, the first circuit must remain activated during a standby state. Indeed, a mobile telephone must remain permanently synchronized with a mobile telephone network to which it is connected. More precisely, the fast clock circuit is slaved to a reference supplied by the network. By keeping the first circuit activated, when going from a standby state to an active state, a mobile telephone is always synchronized with a network since the first circuit providing the fast clock signal is always active. In return, this results in consumption

  significant energy during a standby time of a mobile phone.

  In addition, another problem relating to the microprocessor employed exists.

  Indeed, with such an embodiment, a microprocessor must be able to operate with these two frequency values. Thus, when this standby method is used, the mobile telephone must be provided with a so-called static microprocessor. A static microprocessor is provided to work with a fast clock signal but it can also work with a clock signal

  slow whose frequency value is a few tens of kHz.

  The object of the present invention is to remedy these problems by proposing a standby method in which the supply of the first circuit supplying the fast clock signal is deactivated in particular. You can also cut the processor power. The method of the invention therefore remains applicable even with a dynamic processor, that is to say not static. In this method, a duration of a standby state is then controlled by a device clocked by the second circuit supplying the slow clock signal. This second circuit is advantageous because a current consumption of this second circuit is of the order of 1 pA. On the other hand, this advantage is associated with a drawback due to a significant drift of the clock frequency in temperature, of the order of 1 ppm, as well as to a low precision on a frequency value of this second

circuit of the order of 30 ppm.

  With the invention, to remedy this problem, the second circuit is calibrated by the first circuit when the mobile telephone is active. Thus a frequency, and therefore a duration of a period, of the second circuit is perfectly known. In addition, this calibration is carried out regularly, for example before each standby state, in order to

  get rid of drifts in particular in temperature of this second circuit.

  In this case, characteristics of the slow clock signal are perfectly known. Given the high periodicity of the calibrations, the temperature drift can be neglected. A reference signal is thus obtained, during a standby state, making it possible to keep synchronization with a

  mobile telephone network to which a mobile telephone is connected.

  In the invention, a number of periods to be counted is determined from the slow clock signal thus calibrated. This number of period includes an integer part and a decimal part. The entire game is counted at a rate set by the slow clock signal. The decimal part is counted at a rate set by the fast clock signal. A counting duration of the whole part can correspond to a duration of the state of

mobile phone standby.

  The method of the invention can be applied to any type of telephone

  mobile whether or not it includes a static microprocessor.

  The subject of the invention is therefore a standby method in a mobile telephone, characterized in that - a mobile telephone is connected to an mobile telephone network by an antenna - the mobile telephone is provided with a radio transmission-reception device connected to the antenna, a first circuit providing a fast clock signal, a second circuit providing a slow clock signal, a microprocessor connected by a bus to a data memory, and a potential source supplying these various elements, - information is received on the antenna of the mobile telephone from the network indicating a delta difference between a known date To and a later date T1, - there are a number N of periods of the clock signal fast contained in a period of the slow clock signal, - we divide a value of the delta duration by the number N and we obtain a number M, M being constituted by an integer part E and a decimal part D, - we count m periods with the fast clock circuit, with m <no is equal to D x N, between the date To and a first edge of the slow clock signal after the date To, - it is stored in the data memory of the telephone mobile a value r of a remainder of a subtraction between m and n, - we place the mobile phone in a standby state, - we count E periods with the slow clock circuit, - we count r periods with the circuit fast clock,

  - the mobile phone is put in a state of standby.

  The invention will be better understood on reading the description which follows

  and examining the accompanying figures. These are presented for information only and in no way limit the invention. The figures show: - Figure 1: a representation of the different means of a mobile telephone used by the method of the invention; - Figure 2: a temporal evolution, in the form of chronograms, of signals used in the method of the invention - Figure 3: a representation, in the form of an algorithm, of a

  possible sequence of the various stages of the process of the invention.

  Figure 1 shows a mobile phone 1 usable to implement the method of the invention. The mobile telephone 1 has an antenna 2. This mobile telephone 1 is radio-linked with a

  mobile telephone network 3 via antenna 2.

  Regularly, the network 3 sends information 4 to the antenna 2 of the mobile telephone 1. This information 4 relates to a delta difference between a known date TO and a later date T1. A date TO is, for example, a date on which the mobile telephone 1 must listen to know whether it is the subject of an incoming call. A T1 date is a later appointment to repeat such listening. To process the information 4, the mobile telephone 1 notably includes a radio device 5 connected to the antenna 2, a microprocessor 6, a program 7 in a program memory 8, a data memory 9 as well as a communications bus 10 which connects these elements together. The term “microprocessor” means all of the means for processing baseband signals, that is to say means other than those used to process radioelectric signals. This includes the processor itself, such as one or more DSPs and their associated logic circuits. The device 5 is responsible for translating the information 4 into data understandable by the program 7, in particular for demodulating and quantifying it. These data are placed in the data memory 9 by the microprocessor 6 via the bus 10. The data memory 9 thus includes information relating to the value of the delta difference between the date TO and the date T1. Mobile phone 1 is further provided with a first circuit 11 providing a fast clock signal and a second circuit 12 providing a slow clock signal. It is also provided with a potential source 13 constituting a potential source supplying the various elements of the mobile phone 1. In the mobile phone 1 there is also a circuit 14 for counting and a circuit 15 for putting the mobile phone on standby 1 subsequently named ASIC 15. The circuit 15 is an ASIC (Application Specialized Integrated Circuit in English or integrated circuit with specialized application in French) capable of performing certain operations, but not all, normally performed by the microprocessor 6. The circuit 15 is in particular responsible for waking up the microprocessor 6 at the end of the standby period. In practice, circuit 14 is incorporated into circuit 15 and

therefore form a single ASIC.

  The counting circuit 14 comprises, in addition to a connection to the bus, an input 16 and an input 17. The input 16 is connected to the first circuit 11 and the input 17 is connected to the second circuit 12. This counting circuit 14 is responsible for counting a number N of periods of the fast clock signal contained in a period of the slow clock signal. In a variant, the counting device 14 counts a number of periods of the fast clock signal contained in several successive periods of the slow clock signal. In this variant, the program 7 determines a number N by dividing a number of periods of the fast clock signal by a number of

periods of the slow clock signal.

  The value of N obtained is stored in the data memory 9. Program 7 uses the value of N and the value of the delta deviation for

  determining a number of equivalent periods of the slow clock signal.

  According to a unit in which the delta difference is expressed two realizations are possible. A first preferred embodiment consists in the network 3 sending information 4 whose information relating to the delta difference is expressed in time units, seconds for example. Thus, the program 7 multiplies a value of N by a duration of a period of the fast clock signal. Then program 7 divides the value of the delta difference by the result of this multiplication. A number M is thus obtained. In a second embodiment, the information sent is expressed in number of periods of the fast clock signal. To obtain the value of M, the program 7 directly divides the delta difference by the value of N. The number M consists of an integer part E defining a number of periods of the slow clock signal. This number M also includes a decimal part D defining a fraction of a period of the slow clock signal. This value D cannot be counted from the slow clock signal since it is less than the duration of a period of the slow clock signal. Rounding the number M by default or by excess would amount to making an error which may be equal to one period of the slow clock signal, which is intolerable. Indeed, during a return to an active state of the mobile telephone 1 a requested synchronization between the network 3 and the

  mobile phone 1 must be produced with an accuracy of less than 1 p.s.

  This means that a difference between a wake-up call from mobile phone 1 and the scheduled date T1 must not exceed 1 lis. Otherwise the mobile phone 1 will not be able to communicate with the network 3 since it will have missed the date T1 of appointment. Thus this decimal part D is counted but in number of periods of the fast clock signal. To do this, the program 7 converts the value of the number D into a value n of periods of the fast clock signal by multiplying D by N. This value of n is stored in the data memory 9 by the microprocessor 6. In practice the FIG. 2 schematically shows a duration corresponding to the result M. This duration corresponds to the duration of the slow counting E and to a duration of

fast counting n, o n = m + r.

  When the TO date has passed, the mobile telephone 1 can be put in a standby state. Initially, the circuit 15 counts m periods of the fast clock signal between the date TO and that T2 of a first edge of the slow clock signal after the date TO. This value of m therefore corresponds to a phase shift between the fast clock signal on the date TO and the slow clock signal, the unit of this phase shift being in number of periods of the fast clock signal. A value of m thus obtained is subtracted from the value of n to give a remainder r. The rest r is stored in a memory (not shown) of the circuit 15. From the moment when this first edge of the slow clock signal occurs, E period is counted with the slow clock circuit. We also put the mobile phone in a standby state

  during a period T2-T4 during which the E periods are counted.

  From this first edge, the ASIC 15 stops a supply, by the potential source 13, of the various elements of the mobile telephone 1 including in particular that of the first circuit 11. Once the E periods have been counted, the ASIC circuit 15 supplies power to again the first circuit 11, and there are r periods with the fast clock circuit. At the end of the counting of E periods, the mobile telephone 1 is put into an active state. Later, on the date T1 which corresponds to the date on which the network 3 had given an appointment, the mobile telephone 1 can again exchange information such as 4 with the network 3. In addition a calibration of the second circuit 12 is at

  again made with the first circuit 11.

  In a preferred example, the first circuit 11 providing the fast clock signal is connected to the microprocessor 6. The ASIC 15 is responsible for counting the E periods of the slow clock signal. Consequently we connect the

  second circuit 12 supplying the slow clock signal to the ASIC 15.

  The mobile telephone 1 comprises a switch device 18 with a

  power input 19, a control input 20 and an output 21.

  The input 19 is connected to the potential source 13. The output 21 is connected to the device 5, to the microprocessor 6, to the clock circuit 11, to the device

  count 14, to program memory 8 and to data memory 9.

  The second circuit 12 and the ASIC 15 are connected directly to the potential source 13. The ASIC 15 also comprises a control output 22. This control output 22 of the ASIC 15 is connected to the control input 20 of the switch device 18. During the period of counting the E periods of the slow clock signal, the ASIC 15 sends information to the switch device such that the switch device 18 behaves like an open circuit between the power input 19 and the output 21. Thus, all the elements connected to the output 21 are no longer supplied. Energy consumption depends, in a standby state, mainly on the clock circuit

12 and ASIC 15.

  FIG. 2 shows a time evolution, in the form of chronograms 23 to 27, of the method of the invention. On the chronogram 23, dates corresponding to the main events appear

  producing before, during and after a standby state of the mobile phone 1.

  The standby occurs after, or at the time of the T2 date, that is to say for example on a T3 date. The awakening occurs before the date T1, at a date T5. The duration from the date T5 to the date T1 must be sufficient for the microprocessor 6 and the circuits which it controls to be available for the active state at the date T1. On the time axis of chronogram 24 we do

  a slow clock signal appears, for example with a half duty cycle.

  In a preferred variant, the signal of circuit 12 is produced continuously. This is not a problem because circuit 12 consumes little. One could however consider cutting it during the active state. On the time axis of the timing diagram 25, there are represented steps for counting the E periods of the slow clock signal. On the time axis of the chronogram 26 a representation of the fast clock signal appears during an active state and during a standby state (between T3 and T4). Finally, on the time axis of the chronogram 27, the different counting periods are shown. At the date T on the timing diagram 23 the mobile telephone 1 receives information 4 from the network 3. The date T, on the timing diagram 26, corresponds to an instant synchronous with the fast clock signal. An event which occurs at a time synchronous with the fast clock signal is an event which occurs during an edge of this fast clock signal. Information 4 makes it possible to know a value of the delta difference between the known TO date and the later T1 date. Between the date T and the date TO the mobile telephone 1 is active. During this time interval the timing diagram 27 shows a first count N concerning a calibration of the slow clock signal, present on the timing diagram 24, and the fast clock signal. With the microprocessor 6, the number N is thus obtained. At a date TO begins the phase of counting the m periods of fast clock signal between this date TO and a first edge 28 of the slow clock signal. A start of counting, that is to say the date TO, is synchronous with the fast clock signal. An end of counting of m occurs at a date T2, during a first edge 28 of the slow clock signal, the date T2 is synchronous with the slow clock signal. Counting of the E slow clock signal periods can therefore begin. At this time of counting the various elements of the mobile telephone 1 are always supplied by the potential source 13. This allows in particular the microprocessor 6 to calculate the remainder r from the value of m and to put this value of r in the memory 9. Thus putting the mobile phone 1 into an effective standby state is shifted, for example to a date T3, relative to

  at the start of counting the E periods.

  At a date T3 later than the date T2, the ASIC 15 controls the switch device 18 in order to have an open circuit between the supply input 19 and the output 21. In a preferred example, this event on the date T3 occurs produces during a first period E periods of the slow clock signal. This event could just as easily have happened at a later date. After the T3 date, ASIC 15 counts until the arrival of a

  date T4 synchronous with the slow clock signal of chronogram 24.

  At this date T4, ASIC 15 counted E - k slow signal periods. In a preferred example k is equal to 2, but k could very well have taken any value between 0 and E. From the date T4, the ASIC 15 reactivates the circuit 11 supplying the fast clock signal. ASIC 15 continues to count until reaching the value E. This occurs at a date T5 synchronous with the slow clock signal. Thus, the k clock periods of the slow signal between the date T4 and the date T5 allow the circuit 11 to have sufficient time for the fast clock signal which it provides to be stable, this corresponds to a time of establishment. This circuit 11 has restarted synchronously with respect to the slow clock signal. Then we can consider that arrived at the date T5 the two clock signals are synchronous, or at most to a period of the fast clock signal near. From this date T5 the mobile telephone 1 is awakened but does not receive a message from the network. Indeed, the date T5 and the date T1 are not confused, therefore the mobile telephone 1 is not synchronous with the network 3. To arrive at the date T1 the microprocessor 6 counts r periods of the fast clock signal, an end of counting corresponding to date T1. The mobile phone 1 then turns on

listening on the scheduled T1 date.

  The edge 28 of the slow clock signal occurring on the date T2 is, in a preferred example, a rising edge of the slow clock signal. We could very well use as falling signal edges as reference

slow clock.

  In order to improve the calibration accuracy of the slow clock signal by the fast clock signal, the latter is replaced, in a variant, by a double clock signal of frequency higher than the fast clock signal. A double clock signal is produced from the fast clock signal. Many variants exist for obtaining the double clock signal. In one of these possible variants, a replica of the fast clock signal is used, but offset in time by half a period with respect to the fast clock signal. In this variant, we consider clock signals with a duty cycle of less than a half. That is to say that a ratio of a duration between two consecutive edges over a duration of a period of a clock signal is less than half. In this case to obtain the double clock signal, it suffices for example to add, in particular by virtue of a logic circuit performing this function, the fast clock signal and the replica of the fast clock signal. Consequently, the double clock signal makes it possible to obtain, in the same time interval, twice as many rising edges as the fast clock signal. This increases the accuracy of the calibration of the slow clock signal by the double clock signal. As a variant, the double clock signal is obtained by reversing a fast clock signal with a half duty cycle. In this variant, an even greater accuracy can be obtained, by additionally shifting each of the two signals by a quarter of a period. The precision is then multiplied by four. As synchronization with the network is carried out to a period of the fast clock signal near then, with these variants, a precision of the synchronization is improved all the more. Furthermore, with a double clock signal, there is no longer a number N of periods but a number N 'of periods of the double clock signal contained in a period of the slow clock signal. In this variant, the replica of the fast clock signal is preferably shifted by half a period with respect to the signal.

fast clock.

  In a preferred example the fast clock signal is at a frequency of 13 MHz. The slow clock signal is at a frequency of 32 kHz. A clock period equivalent to the fast clock signal is of the order of 77 ns. Accuracy of synchronization between network 3 and mobile phone 1 must be less than 1 microsecond. In the invention, we are at around 77 ns and even around 38.5 ns if we use

  the variant with the double clock signal.

  FIG. 3 shows, in the form of an algorithm, a possible sequence of the different steps of the method of the invention. In a step 29, the network 3 sends the information relating to the difference to the mobile telephone 1

  delta between the known TO date and the later T1 date.

  During a step 30 the microprocessor 6 calibrates the slow clock signal from the fast clock signal and obtains a value N which it stores

in the data memory 9.

  Once this calibration has been carried out, the program 7 controls, in a step 31, the microprocessor 6 so that the latter deduces therefrom a standby time E. This calculation makes it possible to obtain the number M with the integer part E and the rest D. One problem is that, in order to keep a synchronous set, a start of the counting of the E periods is done synchronously with respect to the fast clock signal. This synchronization is ensured in

a step 32.

  In this step 32, a phase shift m is measured between the date TO and a first rising edge of the slow clock signal after the date TO. The

  phase shift m is measured in number of periods of the fast clock signal.

  At the end of this counting, a value relative to a remainder is stored between this value m and the value of D translated into number of periods of fast clock signal. At the same instant, a step 33 begins in which the mobile telephone 1 is on standby, that is to say in which the circuit 11 supplying the fast clock signal is deactivated. Before the end of the counting of the E periods of slow clock signal, a test step 34 is implemented by the ASIC 15 in order to test whether one has arrived at a wake-up date or not. In the case of an affirmative response to this test, the method performs a step 35 in which the ASIC 15 reactivates the circuit 11 supplying the fast clock signal then, at the end of the counting of the E periods, the microprocessor 6 counts the r fast clock signal periods including one

  value was stored in the data memory 9 during step 32.

  In the case of a negative response to the test step 34, the method of the invention leaves the mobile telephone 1 in the step 33 standby and continues to count. After step 35, the mobile phone 1 is found on the date T1 provided in particular during step 29. In this case during a step 36, the mobile phone 1 is active, that is to say that it can exchange information

with the network 3.

  In a step 37, the mobile telephone I finds itself in a test step in which it is checked whether the network sends information relating to a change in a value of the delta deviation. In the case of a change, the network sends this new value, and the process is again found in step 29. In the case of a negative response to this test, the process only calibrates the signal again. slow clock from

  fast clock signal and is thus found in step 30.

  In one embodiment of the invention, it has been considered that the ASIC 15 and the microprocessor 6 measure the numbers of periods of fast clock signal or slow clock signal by means of counting, but we could very well have envisaged counting means without this

poses a particular problem.

Claims (6)

  1 - Standby method in a mobile telephone (1) characterized in that a mobile telephone (1) is connected by an antenna (2) to a mobile telephone network (3) - the mobile telephone (1) is provided with a radio transmission-reception device (5) connected to the antenna (2), a first circuit (11) providing a fast clock signal, a second circuit (12) providing a clock signal slow, a microprocessor (6) connected by a bus (10) to a data memory (9), and a potential source (13) supplying these different elements, - we receive on the antenna (2) from the mobile telephone (1) information (4) from the network (3) indicating a delta difference between a known TO date and a later date T1, - there are a number N of periods of the fast clock signal contained in a period of slow clock signal, - divide a value of the delta duration by the number N and we obtain a number M, M being constituted by an integer part E and a decimal part D, - there are m periods with the fast clock circuit, with m <no is equal to D x N, between the date TO and a first edge of the slow clock signal after the date TO, - one stores in the data memory (9) of the mobile telephone (1) a value r of a remainder of a subtraction between m and n, - one places the mobile telephone (1) in a standby state, - one counts E periods with the slow clock signal, - r periods with the fast clock signal are counted,   - the mobile phone (1) is put into an active state.   2 - Method according to claim 1 characterized in that - one connects the first circuit (11) providing the fast clock signal to the microprocessor (6), - one connects the second circuit (12) providing a slow clock signal to an ASIC circuit (15).   3 - Method according to claim 2 characterized in that - there is interposed a switch device (18) between the potential source (13) and the first circuit (11), the microprocessor (6) and the device (5) radioelectric transmit-receive, and   - the switch device (18) by the ASIC circuit (15).   4 - Method according to claim 3 characterized in that - an opening of the switch device (18) is controlled during   a duration at least equal to E periods of the slow clock signal.   - Method according to one of claims 1 to 4 characterized in that   - we count the m periods between the TO date and a first edge   amount (28) of the slow clock signal.   6 - Method according to one of claims 1 to 5 characterized in that   - a double clock signal is produced from the fast clock signal and a replica of the fast clock signal but offset in time with respect thereto, - there is a number N 'of periods of the double clock signal contained in a period of the slow clock signal instead of the number N. 7 - Method according to claim 6 characterized in that - the replica of the fast clock signal is shifted by a quarter of a period   relative to the fast clock signal.   8 - Method according to one of claims 1 to 7 characterized in that   - the fast clock signal is at a frequency of 13 MHz,   - the slow clock signal is at a frequency of 32 kHz.