FR2790152B1 - Dispositif de suppression de decalage d'horloge - Google Patents

Dispositif de suppression de decalage d'horloge

Info

Publication number
FR2790152B1
FR2790152B1 FR0001839A FR0001839A FR2790152B1 FR 2790152 B1 FR2790152 B1 FR 2790152B1 FR 0001839 A FR0001839 A FR 0001839A FR 0001839 A FR0001839 A FR 0001839A FR 2790152 B1 FR2790152 B1 FR 2790152B1
Authority
FR
France
Prior art keywords
suppression device
clock offset
offset suppression
clock
suppression
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0001839A
Other languages
English (en)
Other versions
FR2790152A1 (fr
Inventor
Adrian Fawcett
Jeremy Whaley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
SGS Thomson Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Ltd filed Critical SGS Thomson Microelectronics Ltd
Publication of FR2790152A1 publication Critical patent/FR2790152A1/fr
Application granted granted Critical
Publication of FR2790152B1 publication Critical patent/FR2790152B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S331/00—Oscillators
    • Y10S331/02—Phase locked loop having lock indicating or detecting means
FR0001839A 1999-02-18 2000-02-15 Dispositif de suppression de decalage d'horloge Expired - Fee Related FR2790152B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB9903769A GB2348327B (en) 1999-02-18 1999-02-18 Clock skew removal appartus

Publications (2)

Publication Number Publication Date
FR2790152A1 FR2790152A1 (fr) 2000-08-25
FR2790152B1 true FR2790152B1 (fr) 2001-07-27

Family

ID=10848059

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0001839A Expired - Fee Related FR2790152B1 (fr) 1999-02-18 2000-02-15 Dispositif de suppression de decalage d'horloge

Country Status (4)

Country Link
US (1) US6320436B1 (fr)
FR (1) FR2790152B1 (fr)
GB (1) GB2348327B (fr)
IT (1) IT1316642B1 (fr)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020090045A1 (en) * 2001-01-10 2002-07-11 Norm Hendrickson Digital clock recovery system
US6384649B1 (en) * 2001-02-22 2002-05-07 International Business Machines Corporation Apparatus and method for clock skew measurement
DE10128474B4 (de) * 2001-06-12 2006-05-24 Siemens Ag Verfahren und Schaltungsanordnung zur Kompensation von Laufzeitunterschieden bei der Taktsynchronisation
US7137052B2 (en) * 2001-07-19 2006-11-14 Verigy Ipco Methods and apparatus for minimizing current surges during integrated circuit testing
US6566924B2 (en) * 2001-07-25 2003-05-20 Hewlett-Packard Development Company L.P. Parallel push algorithm detecting constraints to minimize clock skew
US6753709B2 (en) * 2002-06-28 2004-06-22 Agere Systems Inc. Digital clock rate multiplier method and apparatus
US6859109B1 (en) 2003-05-27 2005-02-22 Pericom Semiconductor Corp. Double-data rate phase-locked-loop with phase aligners to reduce clock skew
US6959397B2 (en) * 2003-06-18 2005-10-25 Motorola, Inc. Programmable skew clock signal generator selecting one of a plurality of delayed reference clock signals in response to a phase accumulator output
US20050220236A1 (en) * 2004-03-31 2005-10-06 Glenn Wood Data receiver with servo controlled delayed clock
US7119583B2 (en) * 2004-03-31 2006-10-10 Micron Technology, Inc. Phase detector and method having hysteresis characteristics
US7079973B2 (en) * 2004-04-06 2006-07-18 Avago Technologies General Ip Pte. Ltd. Apparatus and method for compensating clock period elongation during scan testing in an integrated circuit (IC)
US7516379B2 (en) * 2004-04-06 2009-04-07 Avago Technologies General Ip (Singapore) Pte. Ltd. Circuit and method for comparing circuit performance between functional and AC scan testing in an integrated circuit (IC)
US7353420B2 (en) * 2005-04-07 2008-04-01 Winbond Electronics Corp. Circuit and method for generating programmable clock signals with minimum skew
US7664213B2 (en) * 2005-11-22 2010-02-16 Sun Microsystems, Inc. Clock alignment detection from single reference
US7423456B2 (en) * 2006-12-01 2008-09-09 Micron Technology, Inc. Fast response time, low power phase detector circuits, devices and systems incorporating the same, and associated methods
US7733130B2 (en) * 2008-03-06 2010-06-08 Oracle America, Inc. Skew tolerant communication between ratioed synchronous clocks
WO2010026642A1 (fr) * 2008-09-04 2010-03-11 株式会社アドバンテスト Dispositif d’essai, dispositif d'émission, dispositif de réception, procédé d’essai, procédé d'émission et procédé de réception
US9600018B1 (en) * 2014-06-09 2017-03-21 Xilinx, Inc. Clock stoppage in integrated circuits with multiple asynchronous clock domains
GB2542149B (en) 2015-09-09 2019-11-27 Imagination Tech Ltd Synchronising devices
US20180205383A1 (en) * 2017-01-19 2018-07-19 Qualcomm Incorporated Digital Clock Generation and Variation Control Circuitry
US10158364B1 (en) * 2017-08-31 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Realignment strength controller for solving loop conflict of realignment phase lock loop
US10838449B2 (en) * 2018-07-05 2020-11-17 International Business Machines Corporation Automatic detection of clock grid misalignments and automatic realignment
CN116418321B (zh) * 2023-03-28 2024-03-19 成都电科星拓科技有限公司 上电自动调整多路时钟保持输出延迟相等的方法及电路

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2071943B (en) * 1980-03-10 1984-06-27 Control Data Corp Delay lock loop
JPS5986385A (ja) * 1982-11-09 1984-05-18 Toshiba Corp サンプリングパルス生成回路
US4617679A (en) * 1983-09-20 1986-10-14 Nec Electronics U.S.A., Inc. Digital phase lock loop circuit
JPS6227813A (ja) 1985-07-29 1987-02-05 Hitachi Ltd 位相同期方式
US4755704A (en) 1987-06-30 1988-07-05 Unisys Corporation Automatic clock de-skewing apparatus
IL89120A (en) 1988-02-17 1992-08-18 Mips Computer Systems Inc Circuit synchronization system
US5118975A (en) 1990-03-05 1992-06-02 Thinking Machines Corporation Digital clock buffer circuit providing controllable delay
US5305451A (en) 1990-09-05 1994-04-19 International Business Machines Corporation Single phase clock distribution circuit for providing clock signals to multiple chip integrated circuit systems
US5218314A (en) * 1992-05-29 1993-06-08 National Semiconductor Corporation High resolution, multi-frequency digital phase-locked loop
US5790611A (en) * 1994-08-12 1998-08-04 Lsi Logic Corporation Method and apparatus for adjusting the phase of a digital signal
JP4090088B2 (ja) * 1996-09-17 2008-05-28 富士通株式会社 半導体装置システム及び半導体装置

Also Published As

Publication number Publication date
GB9903769D0 (en) 1999-04-14
ITMI20000263A1 (it) 2001-08-16
US6320436B1 (en) 2001-11-20
ITMI20000263A0 (it) 2000-02-16
GB2348327B (en) 2003-02-19
IT1316642B1 (it) 2003-04-24
FR2790152A1 (fr) 2000-08-25
GB2348327A (en) 2000-09-27

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20091030