FR2771564B1 - Dispositif pour l'initialisation a la mise sous tension d'un circuit integre digital - Google Patents

Dispositif pour l'initialisation a la mise sous tension d'un circuit integre digital

Info

Publication number
FR2771564B1
FR2771564B1 FR9714643A FR9714643A FR2771564B1 FR 2771564 B1 FR2771564 B1 FR 2771564B1 FR 9714643 A FR9714643 A FR 9714643A FR 9714643 A FR9714643 A FR 9714643A FR 2771564 B1 FR2771564 B1 FR 2771564B1
Authority
FR
France
Prior art keywords
initializing
power
integrated circuit
digital integrated
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
FR9714643A
Other languages
English (en)
Other versions
FR2771564A1 (fr
Inventor
Christian Pitot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thales Avionics SAS
Original Assignee
Thales Avionics SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thales Avionics SAS filed Critical Thales Avionics SAS
Priority to FR9714643A priority Critical patent/FR2771564B1/fr
Publication of FR2771564A1 publication Critical patent/FR2771564A1/fr
Application granted granted Critical
Publication of FR2771564B1 publication Critical patent/FR2771564B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0763—Error or fault detection not based on redundancy by bit configuration check, e.g. of formats or tags
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Storage Device Security (AREA)
FR9714643A 1997-11-21 1997-11-21 Dispositif pour l'initialisation a la mise sous tension d'un circuit integre digital Expired - Lifetime FR2771564B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR9714643A FR2771564B1 (fr) 1997-11-21 1997-11-21 Dispositif pour l'initialisation a la mise sous tension d'un circuit integre digital

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9714643A FR2771564B1 (fr) 1997-11-21 1997-11-21 Dispositif pour l'initialisation a la mise sous tension d'un circuit integre digital

Publications (2)

Publication Number Publication Date
FR2771564A1 FR2771564A1 (fr) 1999-05-28
FR2771564B1 true FR2771564B1 (fr) 2000-02-11

Family

ID=9513647

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9714643A Expired - Lifetime FR2771564B1 (fr) 1997-11-21 1997-11-21 Dispositif pour l'initialisation a la mise sous tension d'un circuit integre digital

Country Status (1)

Country Link
FR (1) FR2771564B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2992485B1 (fr) * 2012-06-21 2014-09-12 Sagem Defense Securite Circuit electrique de coupure d'une alimentation electrique a relais et fusibles

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2197507A (en) * 1986-11-03 1988-05-18 Philips Electronic Associated Data processing system
IT1246467B (it) * 1990-10-22 1994-11-19 St Microelectronics Srl Macchina a stati finiti per sistemi affidabili di computazione e regolazione
US5528756A (en) * 1995-01-30 1996-06-18 Elsag International N.V. Method and apparatus for performing supervisory functions in digital systems and obtaining diagnostics thereof

Also Published As

Publication number Publication date
FR2771564A1 (fr) 1999-05-28

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