FR2754368B1 - Procede d'optimisation d'un circuit pour l'emulation logique - Google Patents

Procede d'optimisation d'un circuit pour l'emulation logique

Info

Publication number
FR2754368B1
FR2754368B1 FR9711810A FR9711810A FR2754368B1 FR 2754368 B1 FR2754368 B1 FR 2754368B1 FR 9711810 A FR9711810 A FR 9711810A FR 9711810 A FR9711810 A FR 9711810A FR 2754368 B1 FR2754368 B1 FR 2754368B1
Authority
FR
France
Prior art keywords
optimizing
circuit
logic emulation
emulation
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9711810A
Other languages
English (en)
Other versions
FR2754368A1 (fr
Inventor
Wei Jin Dai
Junjing Yan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Quickturn Design Systems Inc
Original Assignee
Quickturn Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Quickturn Design Systems Inc filed Critical Quickturn Design Systems Inc
Publication of FR2754368A1 publication Critical patent/FR2754368A1/fr
Application granted granted Critical
Publication of FR2754368B1 publication Critical patent/FR2754368B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/331—Design verification, e.g. functional simulation or model checking using simulation with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
FR9711810A 1996-09-23 1997-09-23 Procede d'optimisation d'un circuit pour l'emulation logique Expired - Fee Related FR2754368B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/718,655 US5886904A (en) 1996-09-23 1996-09-23 Latch optimization in hardware logic emulation systems

Publications (2)

Publication Number Publication Date
FR2754368A1 FR2754368A1 (fr) 1998-04-10
FR2754368B1 true FR2754368B1 (fr) 2001-11-23

Family

ID=24886951

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9711810A Expired - Fee Related FR2754368B1 (fr) 1996-09-23 1997-09-23 Procede d'optimisation d'un circuit pour l'emulation logique

Country Status (5)

Country Link
US (1) US5886904A (fr)
JP (1) JPH10134091A (fr)
DE (1) DE19741915A1 (fr)
FR (1) FR2754368B1 (fr)
GB (1) GB2319099B (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6301553B1 (en) * 1996-05-31 2001-10-09 Luc M. Burgun Method and apparatus for removing timing hazards in a circuit design
US6141636A (en) * 1997-03-31 2000-10-31 Quickturn Design Systems, Inc. Logic analysis subsystem in a time-sliced emulator
US6081656A (en) * 1997-06-27 2000-06-27 Advanced Micro Devices, Inc. Method for deriving a double frequency microprocessor from an existing microprocessor
US6279146B1 (en) 1999-01-06 2001-08-21 Simutech Corporation Apparatus and method for verifying a multi-component electronic design
US6715093B1 (en) * 2000-04-28 2004-03-30 Hewlett-Packard Development Company, L.P. Method for triggering an asynchronous event by creating a lowest common denominator clock
US6433603B1 (en) 2000-08-14 2002-08-13 Sun Microsystems, Inc. Pulse-based high speed flop circuit
CA2329601A1 (fr) * 2000-12-22 2002-06-22 Logicvision, Inc. Methode et programme de modelisation de circuits avec verrouillage/bascule
US7260515B2 (en) * 2001-08-20 2007-08-21 Sun Microsystems, Inc. Method and apparatus for simulating transparent latches
JP2003091569A (ja) * 2001-09-17 2003-03-28 Nec Corp 半導体集積回路設計方法、半導体集積回路、電子機器
US6718530B2 (en) * 2002-07-29 2004-04-06 Sun Microsystems, Inc. Method and apparatus for analyzing inductive effects in a circuit layout
US6920625B2 (en) * 2003-04-24 2005-07-19 International Business Machines Corporation Method and apparatus for optimum transparent latch placement in a macro design
US7254793B2 (en) * 2005-02-04 2007-08-07 Synopsys, Inc. Latch modeling technique for formal verification
US7299436B2 (en) * 2005-02-10 2007-11-20 International Business Machines Corporation System and method for accurately modeling an asynchronous interface using expanded logic elements
US8595683B1 (en) 2012-04-12 2013-11-26 Cadence Design Systems, Inc. Generating user clocks for a prototyping environment
US10140413B2 (en) * 2015-04-21 2018-11-27 Synopsys, Inc. Efficient resolution of latch race conditions in emulation

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4306286A (en) * 1979-06-29 1981-12-15 International Business Machines Corporation Logic simulation machine
US4656580A (en) * 1982-06-11 1987-04-07 International Business Machines Corporation Logic simulation machine
JPH0743733B2 (ja) * 1985-12-11 1995-05-15 株式会社日立製作所 論理シミュレーション方法
US4914612A (en) * 1988-03-31 1990-04-03 International Business Machines Corporation Massively distributed simulation engine
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
ATE265712T1 (de) * 1988-10-05 2004-05-15 Quickturn Design Systems Inc Verfahren zur verwendung einer elektronisch wiederkonfigurierbaren gatterfeld-logik und dadurch hergestelltes gerät
US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5109353A (en) * 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5475830A (en) * 1992-01-31 1995-12-12 Quickturn Design Systems, Inc. Structure and method for providing a reconfigurable emulation circuit without hold time violations
US5359535A (en) * 1992-05-04 1994-10-25 Motorola, Inc. Method for optimization of digital circuit delays
US5352123A (en) * 1992-06-08 1994-10-04 Quickturn Systems, Incorporated Switching midplane and interconnection system for interconnecting large numbers of signals
US5425036A (en) * 1992-09-18 1995-06-13 Quickturn Design Systems, Inc. Method and apparatus for debugging reconfigurable emulation systems
US5452239A (en) * 1993-01-29 1995-09-19 Quickturn Design Systems, Inc. Method of removing gated clocks from the clock nets of a netlist for timing sensitive implementation of the netlist in a hardware emulation system
US5551013A (en) * 1994-06-03 1996-08-27 International Business Machines Corporation Multiprocessor for hardware emulation
US5521529A (en) * 1995-06-02 1996-05-28 Advanced Micro Devices, Inc. Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation

Also Published As

Publication number Publication date
GB9720233D0 (en) 1997-11-26
US5886904A (en) 1999-03-23
GB2319099B (en) 2001-06-27
DE19741915A1 (de) 1998-04-02
JPH10134091A (ja) 1998-05-22
FR2754368A1 (fr) 1998-04-10
GB2319099A (en) 1998-05-13

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20140530