FR2748602B1 - Circuit integre comportant des plots de connexion debouchant sur une face - Google Patents
Circuit integre comportant des plots de connexion debouchant sur une faceInfo
- Publication number
- FR2748602B1 FR2748602B1 FR9605698A FR9605698A FR2748602B1 FR 2748602 B1 FR2748602 B1 FR 2748602B1 FR 9605698 A FR9605698 A FR 9605698A FR 9605698 A FR9605698 A FR 9605698A FR 2748602 B1 FR2748602 B1 FR 2748602B1
- Authority
- FR
- France
- Prior art keywords
- ending
- integrated circuit
- plots
- connection
- connection plots
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02377—Fan-in arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01058—Cerium [Ce]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9605698A FR2748602B1 (fr) | 1996-05-07 | 1996-05-07 | Circuit integre comportant des plots de connexion debouchant sur une face |
PCT/FR1997/000790 WO1997042656A1 (fr) | 1996-05-07 | 1997-05-05 | Circuit integre comportant des plots de connexion debouchant sur une face |
US09/180,321 US6084303A (en) | 1996-05-07 | 1997-05-05 | Integrated circuit comprising connection pads emerging on one surface |
EP97923132A EP0901688A1 (fr) | 1996-05-07 | 1997-05-05 | Circuit integre comportant des plots de connexion debouchant sur une face |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9605698A FR2748602B1 (fr) | 1996-05-07 | 1996-05-07 | Circuit integre comportant des plots de connexion debouchant sur une face |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2748602A1 FR2748602A1 (fr) | 1997-11-14 |
FR2748602B1 true FR2748602B1 (fr) | 1998-08-21 |
Family
ID=9491912
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9605698A Expired - Fee Related FR2748602B1 (fr) | 1996-05-07 | 1996-05-07 | Circuit integre comportant des plots de connexion debouchant sur une face |
Country Status (4)
Country | Link |
---|---|
US (1) | US6084303A (fr) |
EP (1) | EP0901688A1 (fr) |
FR (1) | FR2748602B1 (fr) |
WO (1) | WO1997042656A1 (fr) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6246327B1 (en) * | 1998-06-09 | 2001-06-12 | Motorola, Inc. | Radio frequency identification tag circuit chip having printed interconnection pads |
WO2002017392A2 (fr) * | 2000-08-24 | 2002-02-28 | Polymer Flip Chip Corporation | Redistribution polymere de plots de connexion par billes |
EP2447985A1 (fr) | 2010-10-29 | 2012-05-02 | Gemalto SA | Procédé pour réaliser des lignes d'interconnexion ou de redirection d'au moins un composant à circuit intégré |
US10340241B2 (en) | 2015-06-11 | 2019-07-02 | International Business Machines Corporation | Chip-on-chip structure and methods of manufacture |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3421206A (en) * | 1965-10-19 | 1969-01-14 | Sylvania Electric Prod | Method of forming leads on semiconductor devices |
US4723197A (en) * | 1985-12-16 | 1988-02-02 | National Semiconductor Corporation | Bonding pad interconnection structure |
JPH0815152B2 (ja) * | 1986-01-27 | 1996-02-14 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
US5047834A (en) * | 1989-06-20 | 1991-09-10 | International Business Machines Corporation | High strength low stress encapsulation of interconnected semiconductor devices |
US5006673A (en) * | 1989-12-07 | 1991-04-09 | Motorola, Inc. | Fabrication of pad array carriers from a universal interconnect structure |
US5665991A (en) * | 1992-03-13 | 1997-09-09 | Texas Instruments Incorporated | Device having current ballasting and busing over active area using a multi-level conductor process |
US5281684A (en) * | 1992-04-30 | 1994-01-25 | Motorola, Inc. | Solder bumping of integrated circuit die |
US5483100A (en) * | 1992-06-02 | 1996-01-09 | Amkor Electronics, Inc. | Integrated circuit package with via interconnections formed in a substrate |
-
1996
- 1996-05-07 FR FR9605698A patent/FR2748602B1/fr not_active Expired - Fee Related
-
1997
- 1997-05-05 US US09/180,321 patent/US6084303A/en not_active Expired - Lifetime
- 1997-05-05 EP EP97923132A patent/EP0901688A1/fr not_active Withdrawn
- 1997-05-05 WO PCT/FR1997/000790 patent/WO1997042656A1/fr not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
EP0901688A1 (fr) | 1999-03-17 |
US6084303A (en) | 2000-07-04 |
WO1997042656A1 (fr) | 1997-11-13 |
FR2748602A1 (fr) | 1997-11-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20160129 |