FR2713365B1 - Procédé de réduction modulo à l'aide d'une table précalculée. - Google Patents

Procédé de réduction modulo à l'aide d'une table précalculée.

Info

Publication number
FR2713365B1
FR2713365B1 FR9414597A FR9414597A FR2713365B1 FR 2713365 B1 FR2713365 B1 FR 2713365B1 FR 9414597 A FR9414597 A FR 9414597A FR 9414597 A FR9414597 A FR 9414597A FR 2713365 B1 FR2713365 B1 FR 2713365B1
Authority
FR
France
Prior art keywords
reduction process
calculated table
modulo reduction
modulo
calculated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9414597A
Other languages
English (en)
Other versions
FR2713365A1 (fr
Inventor
Lee Yun Ho
Chung Ryong Jang
Myung Sung Lee Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KT Corp
Original Assignee
KT Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KT Corp filed Critical KT Corp
Publication of FR2713365A1 publication Critical patent/FR2713365A1/fr
Application granted granted Critical
Publication of FR2713365B1 publication Critical patent/FR2713365B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
FR9414597A 1993-12-06 1994-12-05 Procédé de réduction modulo à l'aide d'une table précalculée. Expired - Fee Related FR2713365B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930026632A KR950015177B1 (ko) 1993-12-06 1993-12-06 사전 계산 테이블을 이용한 모듈로 리덕션 방법

Publications (2)

Publication Number Publication Date
FR2713365A1 FR2713365A1 (fr) 1995-06-09
FR2713365B1 true FR2713365B1 (fr) 1997-05-23

Family

ID=19370037

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9414597A Expired - Fee Related FR2713365B1 (fr) 1993-12-06 1994-12-05 Procédé de réduction modulo à l'aide d'une table précalculée.

Country Status (4)

Country Link
US (1) US5572454A (fr)
JP (1) JP3432315B2 (fr)
KR (1) KR950015177B1 (fr)
FR (1) FR2713365B1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2726668B1 (fr) * 1994-11-08 1997-01-10 Sgs Thomson Microelectronics Procede de mise en oeuvre de reduction modulaire selon la methode de montgomery
US5724279A (en) * 1995-08-25 1998-03-03 Microsoft Corporation Computer-implemented method and computer for performing modular reduction
US5793659A (en) * 1996-10-15 1998-08-11 United Microelectronics Corporation Method of modular reduction and modular reduction circuit
US6424712B2 (en) * 1997-10-17 2002-07-23 Certicom Corp. Accelerated signature verification on an elliptic curve
US6369727B1 (en) * 1999-12-17 2002-04-09 Rng Research Analog-to-digital conversion method of random number generation
DE10021920C1 (de) 2000-05-05 2001-07-26 Infineon Technologies Ag Datenverarbeitungsverfahren und -Einrichtung zur Modulo-Berechnung eines Rests bei der Division
US7170997B2 (en) 2000-12-07 2007-01-30 Cryptico A/S Method of generating pseudo-random numbers in an electronic device, and a method of encrypting and decrypting electronic data
US7194088B2 (en) * 2001-06-08 2007-03-20 Corrent Corporation Method and system for a full-adder post processor for modulo arithmetic
DE10200133B4 (de) * 2002-01-04 2005-12-22 Infineon Technologies Ag Verfahren und Vorrichtung zur Berechnung von Modulo-Operationen
US20040086117A1 (en) * 2002-06-06 2004-05-06 Petersen Mette Vesterager Methods for improving unpredictability of output of pseudo-random number generators
US7849125B2 (en) 2006-07-07 2010-12-07 Via Telecom Co., Ltd Efficient computation of the modulo operation based on divisor (2n-1)
KR101326078B1 (ko) 2007-10-11 2013-11-08 삼성전자주식회사 모듈러 곱셈 방법, 모듈러 곱셈기 및 모듈러 곱셈기를구비하는 암호 연산 시스템

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3980874A (en) * 1975-05-09 1976-09-14 Burroughs Corporation Binary to modulo M translation
US4742479A (en) * 1985-03-25 1988-05-03 Motorola, Inc. Modulo arithmetic unit having arbitrary offset and modulo values
ATE55033T1 (de) * 1986-03-05 1990-08-15 Holger Sedlak Kryptographie-verfahren und kryptographieprozessor zur durchfuehrung des verfahrens.
JPH0778726B2 (ja) * 1986-08-21 1995-08-23 富士通株式会社 分割整数剰余計算機
US4891781A (en) * 1987-03-04 1990-01-02 Cylink Corporation Modulo arithmetic processor chip
EP0308963A3 (fr) * 1987-09-25 1990-04-25 Kabushiki Kaisha Toshiba Méthode et dispositif de calcul de reste
US5210710A (en) * 1990-10-17 1993-05-11 Cylink Corporation Modulo arithmetic processor chip
US5249148A (en) * 1990-11-26 1993-09-28 Motorola, Inc. Method and apparatus for performing restricted modulo arithmetic

Also Published As

Publication number Publication date
JP3432315B2 (ja) 2003-08-04
FR2713365A1 (fr) 1995-06-09
JPH07200262A (ja) 1995-08-04
KR950020088A (ko) 1995-07-24
KR950015177B1 (ko) 1995-12-23
US5572454A (en) 1996-11-05

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Legal Events

Date Code Title Description
ST Notification of lapse