FR2707039A1 - Method of producing thick electrical contact studs - Google Patents

Method of producing thick electrical contact studs Download PDF

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FR2707039A1
FR2707039A1 FR8318482A FR8318482A FR2707039A1 FR 2707039 A1 FR2707039 A1 FR 2707039A1 FR 8318482 A FR8318482 A FR 8318482A FR 8318482 A FR8318482 A FR 8318482A FR 2707039 A1 FR2707039 A1 FR 2707039A1
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indium
pellets
gold
substrate
metallizations
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Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
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    • H01L2924/01—Chemical elements
    • H01L2924/01058—Cerium [Ce]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01061—Promethium [Pm]
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    • H01L2924/01079—Gold [Au]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

On a silicone substrate (1), pallets of indium (4) of a few microns in thickness are first of all deposited on a wetting surface (2) bounded by a non-wetting surface (3), then the indium pellets are heated at 160 DEG C for a few seconds, which pellets, by melting, form globules (5), of the same volume, bonding perfectly to the wetting surface (2). This method makes it possible to obtain a mosaic of contact studs of 256x256 points at a pitch of 35 mu m for a globule height of 15 mu m.

Description

La présente invention concerne un procédé de réalisation de plots de contact électrique épais. The present invention relates to a method of producing thick electrical contact pads.

Elle s'applique dans tout le domaine de la microélectronique et particulièrement dans la fabrication des détecteurs matriciels ou des imageurs matriciels afin d'assurer les interconnexions entre deux circuits électroniques superposés. It applies throughout the field of microelectronics and particularly in the manufacture of matrix detectors or matrix imagers to ensure the interconnections between two superimposed electronic circuits.

Dans le brevet américain nO US-P 4 067 104 déposé le 24 février 1977, une méthode d'interconnexion entre des composants microélectroniques situés sur des substrats superposés est décrite. Les interconnexions électriques connectant deux circuits superposés sont des colonnes en métal, réalisées en déposant sur un circuit aux endroits prédéterminés, selon une méthode classique, plusieurs plots métalliques les uns sur les autres et en posant le deuxième circuit au-dessus.  In U.S. Patent No. 4,067,104 filed February 24, 1977, a method of interconnecting microelectronic components on superimposed substrates is described. The electrical interconnections connecting two superimposed circuits are metal columns, made by depositing on a circuit in the predetermined locations, according to a conventional method, several metal pads on each other and placing the second circuit above.

Les colonnes ont un diamètre de 1 mm et une hauteur de 1,7 min.  The columns have a diameter of 1 mm and a height of 1.7 min.

Pour certaines applications, ces dimensions représentent un encombrement gênant. En outre, la fabrication demande plusieurs dépôts de plots métalliques ; le procédé de fabrication d'un tel circuit est donc long et onéreux. For some applications, these dimensions represent a troublesome size. In addition, the manufacturing requires several deposits of metal studs; the method of manufacturing such a circuit is therefore long and expensive.

L'invention a justement pour but de remédier à ces inconvénients et notamment de permettre de réaliser des plots de contact électrique épais ayant des dimensions réduites et pouvant être fabriqués d'une manière très simplifiée. The purpose of the invention is precisely to remedy these drawbacks and in particular to make it possible to produce thick electrical contact pads having reduced dimensions and that can be manufactured in a very simplified manner.

L'invention a pour objet un procédé de réalisation de plots de contact électrique épais caractérisé en ce que l'on effectue les étapes successives suivantes
- a) on dépose sur un substrat portant un circuit électrique des métallisations d'or formant des surfaces mouillantes par rapport à l'indium, aux en droits ou les futurs contacts sont prévus, la surface restante du substrat étant recouverte d'une couche isolante ayant la propriété d'être non-mouillante par rapport à l'indium,
- b) on dépose des pastilles d'indium,d'un diamètre plus grand que celui des métallisations d'or, sur lesdites métallisations, et
- c) on soumet l'ensemble ainsi obtenu à un traitement thermique afin de transformer les pastilles d'indium en plots, ces derniers étant fixés sur les métallisations d'or par la formation du composé AuIn2 à l'interface or-indium.The subject of the invention is a method for producing thick electrical contact pads, characterized in that the following successive steps are carried out:
a) electrodeposited on a substrate bearing an electrical circuit, gold metallizations forming wetting surfaces with respect to the indium, at right angles or future contacts are provided, the remaining surface of the substrate being covered with an insulating layer; having the property of being non-wetting with respect to indium,
b) depositing indium pellets, of a diameter greater than that of the gold metallizations, on said metallizations, and
c) the assembly thus obtained is subjected to a heat treatment in order to convert the indium pellets into plots, the latter being fixed on the gold metallizations by the formation of the AuIn2 compound at the gold-indium interface.

Selon une autre caractéristique, l'épaisseur d'une pastille d'indium étant comprise entre 5 et 7 m et le diamètre de cette pastille étant d'environ 80 ssm, le diamètre du plot d d'indium est d'environ 35 ut et sa hauteur d'environ 25 > m.  According to another characteristic, the thickness of an indium pellet being between 5 and 7 m and the diameter of this pellet being about 80 ssm, the diameter of the indium pad d is about 35 μ and its height of about 25> m.

Selon une autre caractéristique, le traitement thermique consiste à chauffer l'ensemble du circuit avec les pastilles indium à 1600C pendant environ 10 secondes en présence d'un flux liquide. According to another characteristic, the heat treatment consists of heating the entire circuit with the indium pellets at 1600C for about 10 seconds in the presence of a liquid flow.

Selon une autre caractéristique, le circuit électrique sur le substrat est une configuration matricielle pour commander une matrice de composants électroniques. According to another characteristic, the electrical circuit on the substrate is a matrix configuration for controlling a matrix of electronic components.

Selon une autre caractéristique, le matériau isolant déposé sur le circuit est de la silice. According to another characteristic, the insulating material deposited on the circuit is silica.

Les caractéristiques et avantages de l'invention ressortiront mieux de la description qui va suivre, donnée en référence aux dessins annexés, sur lesquels
- la figure I représente schématiquement en coupe le plot de contact électrique avant le traitement thermique,
- la figure 2 représente schématiquement, en coupe, le plot de contact épais obtenu après le traitement thermique, et
- la figure 3 représente schématiquement une vue d'ensemble de plots de contact épais obtenus selon le procédé de l'invention
Sur la figure 1, on a représenté un substrat 1, par exemple en silicium, équipé avec des circuits électroniques suivant les processus des technologies microélectroniques. Les circuits électroniques portés par le substrat ne sont pas représentés. A l'endroit où un plot de contact est prévu, on dépose une métallisation d'or 2 formant une surface mouillante par rapport à l'indium. Son diamètre définit la surface de base du plot de contact à réaliser.The features and advantages of the invention will become more apparent from the following description given with reference to the accompanying drawings, in which:
FIG. 1 schematically represents in section the electrical contact pad before the heat treatment,
FIG. 2 schematically represents, in section, the thick contact pad obtained after the heat treatment, and
FIG. 3 schematically represents an overall view of thick contact pads obtained according to the method of the invention;
FIG. 1 shows a substrate 1, for example made of silicon, equipped with electronic circuits according to the processes of microelectronic technologies. The electronic circuits carried by the substrate are not represented. Where a contact pad is provided, is deposited a gold metallization 2 forming a wetting surface with respect to indium. Its diameter defines the base surface of the contact pad to achieve.

La surface restante du substrat est recouverte d'une couche d'un matériau isolant 3 pouvant être déposée avant ou après le dépôt des métallisations d'or 2. The remaining surface of the substrate is covered with a layer of an insulating material 3 that can be deposited before or after the deposition of the gold metallizations 2.

Ce matériau isolant est choisi tel qu'il soit non-mouillant par rapport à l'indium. Par exemple la silice SiO2 ou le nitrure de silicium Si3N4 peuvent être utilisés. L'utilisation d'autres isolants ayant cette propriété est aussi envisageable. This insulating material is chosen such that it is non-wetting with respect to indium. For example, SiO 2 silica or Si 3 N 4 silicon nitride can be used. The use of other insulators with this property is also possible.

Ensuite, des pastilles d'indium 4 sont déposées sur les métallisations d'or 2. A la place de l'indium, on peut aussi utiliser quelques uns de ses composés ayant un point de fusion assez bas comme par exemple InSn. Then, indium pellets 4 are deposited on gold metallizations 2. In place of indium, it is also possible to use some of its compounds having a low melting point, for example InSn.

Le diamètre des pastilles est choisi plus grand que celui des métallisations d'or, et donc une certaine partie des pastilles d'indium déborde sur la couche isolante 3. The diameter of the pellets is chosen larger than that of the gold metallizations, and thus a certain portion of the indium pellets overflows on the insulating layer 3.

A titre illustratif, si l'on veut réaliser une configuration matricielle de plots de contact sur un substrat, décalés de 100 wm les uns par rapport aux autres, on peut choisir le diamètre des pastilles d'indium inférieur à 90 Bm, par exemple de l'ordre de 80 pm. L'épaisseur de ces pastilles est typiquement de 5 Bm.  By way of illustration, if it is desired to make a matrix configuration of contact pads on a substrate, offset by 100 μm from each other, it is possible to choose the diameter of the indium pellets less than 90 μm, for example the order of 80 pm. The thickness of these pellets is typically 5 μm.

La réalisation des plots d'indium peut être effectué par un procédé de "lift off" en terme anglosaxon. The realization of the indium pads can be carried out by a "lift off" method in Anglosaxon terms.

Ce dernier consiste à métalliser toute la surface d'un substrat avec une couche d'indium, le substrat étant recouvert d'une résine aux endroits où le dépôt d'indium n'est pas prévu. Ensuite, on enlève la résine ainsi que l'indium se trouvant au-dessus de celle-ci au moyen d'un solvant. The latter consists in metallizing the entire surface of a substrate with an indium layer, the substrate being covered with a resin in places where indium deposition is not provided. Then, the resin and the indium above it are removed by means of a solvent.

Après le dépôt des pastilles d'indium, on soumet l'ensemble ainsi obtenu à un traitement thermique. After the deposition of the indium pellets, the assembly thus obtained is subjected to a heat treatment.

Le but de ce traitement est de faire fondre l'indium pendant une période de courte durée. Etant à l'état liquide, l'indium forme une bille 5 sur la surface mouillante, c'est-à-dire sur la métallisation d'or. Le profil ainsi obtenu est représenté sur la figure 2. The purpose of this treatment is to melt indium for a short time. Being in the liquid state, the indium forms a ball 5 on the wetting surface, that is to say on the metallization of gold. The profile thus obtained is shown in FIG.

Le point de fusion de l'indium est de 1570C; un chauffage à 1600C pendant un intervalle de temps de l'ordre de 10 secondes, avec une chaufferette quelconque, suffit pour obtenir des plots de contact 5 sous forme de billes. Pendant le chauffage, aucune précaution particulière n'est apparue nécessaire dans les essais effectués. Un chauffage à l'air est possible en présence d'un flux liquide. The melting point of indium is 1570C; heating at 1600C for a time interval of the order of 10 seconds, with any heater, is sufficient to obtain contact pads 5 in the form of beads. During heating, no special precautions appeared necessary in the tests carried out. Air heating is possible in the presence of a liquid flow.

Le diamètre et la hauteur du plot 5 d'indium en forme de bille dépendent du volume de la pastille d'indium déposée initialement. En se référant à l'exemple donné précédemment, la bille 5 a un diamètre d'environ 35 > m et une hauteur d'environ 25 lssm.  The diameter and height of the ball-shaped indium pad 5 depend on the volume of the initially deposited indium pellet. Referring to the example given above, the ball 5 has a diameter of about 35> m and a height of about 25 lssm.

Ainsi, on a réalisé un plot de contact électrique épais dont l'encombrement est nettement infé rieur à celui des plots épais selon l'art antérieur, donc une augmentation de la densité de plots dans une configuration matricielle est réalisable. L'adhérence des plots sur le substrat est assurée par la formation du composé stable AuIn2 à l'interface 6 entre l'indium et l'or. Les billes ont toutes la même forme, notamment la même hauteur puisque le volume d'indium déposé et la surface de la bille, définie par la métallisation d'or, sont parfaitement déterminés. Thus, a thick electrical contact pad has been realized whose space is much smaller than that of the thick pads according to the prior art, therefore an increase in the density of pads in a matrix configuration is feasible. The adhesion of the pads on the substrate is ensured by the formation of the AuIn2 stable compound at the interface 6 between indium and gold. The balls all have the same shape, especially the same height since the volume of indium deposited and the surface of the ball, defined by the metallization of gold, are perfectly determined.

Sur la figure 3, on a représenté une vue d'ensemble de plots de contact épais obtenus avec le procédé de l'invention. In Figure 3, there is shown an overview of thick contact pads obtained with the method of the invention.

Le procédé de réalisation de ces plots est très fiable t un rendement voisin de 1 est obtenu dans les tests, grâce à la simplicité de cette méthode collective. Ce rendement est indépendant de la surface du substrat ainsi que de la complexité de la mosaïque de plots de contact. Une mosaïque de 256x256 points au pas de 35 Bm pour une hauteur de bille de 15 Bm a été obtenue.  The method for producing these pads is very reliable and a yield close to 1 is obtained in the tests, thanks to the simplicity of this collective method. This efficiency is independent of the surface of the substrate as well as the complexity of the mosaic of contact pads. A mosaic of 256x256 points in steps of 35 Bm for a ball height of 15 Bm was obtained.

Claims (5)

REVENDICATIONS - c) on soumet l'ensemble ainsi obtenu à un traitement thermique afin de transformer les pastilles d'indium (4) en plots (5), ces derniers étant fixés sur les métallisations d'or (2) par la formation du composé AuIn2 à l'interface (6) or-indium. c) the assembly thus obtained is subjected to a heat treatment in order to transform the indium pellets (4) into plots (5), the latter being fixed on the gold metallizations (2) by the formation of the AuIn2 compound at the interface (6) gold-indium. - b) on dépose des pastilles d'indium (4), d'un diamètre plus grand que celui des métallisations d'or, sur lesdites métallisations, et b) depositing indium pellets (4), with a diameter greater than that of the gold metallizations, on said metallizations, and - a) on dépose, sur un substrat (l) portant un circuit électrique, des métallisations d'or (2), formant des surfaces mouillantes par rapport à l'indium, aux endroits où les futurs contacts sont prévus, la surface restante du substrat étant recouverte d'une couche isolante (3) ayant la propriété d'être nonmouillante par rapport à l'indium, a) depositing, on a substrate (1) carrying an electrical circuit, gold metallizations (2), forming wetting surfaces with respect to the indium, at the places where the future contacts are provided, the remaining surface of the substrate being covered with an insulating layer (3) having the property of being non-wetting with respect to indium, l. Procédé de réalisation de plots de contact électrique épais caractérisé en ce que l'on effectue successivement les étapes suivantes l. Process for producing thick electrical contact pads, characterized in that the following steps are successively carried out 2. Procédé selon la revendication 1, caractérisé en ce que l'épaisseur d'une pastille d'indium (4) étant comprise entre 5 et 7 iim et le diamètre de cette pastille d'indium (4) étant d'environ 80 Bm, le diamètre du plot (5) d'indium est d'environ 35 -m et sa hauteur d'environ 25 iim.  2. Method according to claim 1, characterized in that the thickness of an indium pellet (4) being between 5 and 7 iim and the diameter of this indium pellet (4) being about 80 Bm the diameter of the indium pad (5) is about 35 μm and its height about 25 μm. 3. Procédé selon l'une quelconque des revendications 1 et 2, caractérisé en ce que le traitement thermique consiste à chauffer l'ensemble du- circuit avec les pastilles d'indium à 1600C pendant environ 10 secondes en présence d'un flux liquide. 3. Method according to any one of claims 1 and 2, characterized in that the heat treatment consists of heating the entire circuit with the indium pellets at 1600C for about 10 seconds in the presence of a liquid flow. 4. Procédé selon l'une quelconque des revendications 1 à 3, caractérisé en ce que le circuit électrique sur le substrat est une configuration ma tricielle pour commander une matrice de composants électroniques.  4. Method according to any one of claims 1 to 3, characterized in that the electrical circuit on the substrate is a master configuration for controlling a matrix of electronic components. 5. Procédé selon l'une quelconque des revendications 1 à 4, caractérisé en ce que le matériau isolant (3), déposé sur le circuit est de la silice.  5. Method according to any one of claims 1 to 4, characterized in that the insulating material (3), deposited on the circuit is silica.
FR8318482A 1983-11-21 1983-11-21 Method of producing thick electrical contact studs Pending FR2707039A1 (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3625837A (en) * 1969-09-18 1971-12-07 Singer Co Electroplating solder-bump connectors on microcircuits
US3716907A (en) * 1970-11-20 1973-02-20 Harris Intertype Corp Method of fabrication of semiconductor device package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3625837A (en) * 1969-09-18 1971-12-07 Singer Co Electroplating solder-bump connectors on microcircuits
US3716907A (en) * 1970-11-20 1973-02-20 Harris Intertype Corp Method of fabrication of semiconductor device package

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
D.K. JADUS: "Flip Chip Terminal for Semiconductor Devices", IBM TECHNICAL DISCLOSURE BULLETIN., vol. 21, no. 3, August 1978 (1978-08-01), NEW YORK US, pages 1007 *
L.S. GOLDMANN ET AL.: "Lead-Indium for Joining a Semiconductor Chip to a Substrate", IBM TECHNICAL DISCLOSURE BULLETIN., vol. 16, no. 11, April 1974 (1974-04-01), NEW YORK US, pages 3610 - 3611 *
M. LASSUS: "Les semi-conducteurs "à protubérances": une solution économique pour les montages hybrides", ELECTRONIQUE ET MICROELECTRONIQUE INDUSTRIELLES, no. 229, 1 December 1976 (1976-12-01), PARIS FR, pages 23 - 25 *

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