FR2703543A1 - Device for aligning signals generated by an integrated electronic component - Google Patents

Abstract

The invention relates to a signal alignment device (15), intended to guarantee a substantially fixed phase with respect to an exchange clock (14) for data signals (13) generated by transmission means (17) of an electronic component (11). According to the invention, the device comprises: - transcoding means associating at least one parameter affecting the propagation times within the said electronic component with a phase-shift duration substantially proportional to the said propagation times; and - phase-shifting means making it possible to phase shift the said exchange clock (14) by a duration equal to the said phase-shifting duration, and delivering a phase-shifted exchange clock (16), the said phase-shifted exchange clock (16) being used by the said transmission means (17) in order to generate the said data signals (13).

Description

Device for aligning signals generated by an electronic component

  integrated. The field of the invention is that of data exchanges between electronic modules or components placed on the same printed circuit, these exchanges being managed by a single exchange clock supplied to all of the

  electronic components involved.

  More specifically, the invention relates to the alignment of signals generated by an electronic component In other words, the invention relates to a device intended to guarantee a phase that is substantially fixed with respect to an exchange clock to generated data signals by logical means of transmitting a

electronic component.

  The invention is particularly applicable to cases where the exchange clock

  has a very high frequency, for example equal to 155 M Hz.

  In general, the exchange of data between a first electronic component (called the sending component) and a second electronic component (called the receiving component) takes place in the following manner: logical transmission means, located in the sending component , generate data signals from data to be transmitted on the one hand and an exchange clock on the other hand; then these data signals are transmitted to the receiving component; finally, logical reception means, located in the receiver component, extract the data contained in the received data signals using the same exchange clock as that

  used by the sending component.

  Furthermore, in an integrated circuit, the phase of the generated data signals can vary from simple to triple, in particular due to the dispersions

  possible propagation times for the logical layers of electronic components

  ques For each component, these dispersions are a function of the technological parameters of this component (namely its manufacturing process) and the conditions of use of this component (namely its supply voltage and its temperature). This variation (or dispersion) of the phase of the generated data signals has no consequence for the data exchanges between components, provided that the phase with respect to the exchange clock of the generated data signals always remains less than the period of the exchange clock Indeed, if this condition is satisfied, the result of the sampling, in a component

  receiver, data signals by the exchange clock is correct.

  On the contrary, in the case of fast links (that is to say the case of data exchange between a transmitting component and a receiving component with a very high frequency exchange clock), this dispersion of the phase of

  data signals generated by the transmitting component becomes troublesome.

  In fact, in this case, the phase of the generated data signals can, depending on the instants, be less or more than the period of the exchange clock. Consequently, the data signals received by the receiving component are not guaranteed. In other words, the data extracted from these received data signals (by sampling with the exchange clock) may not be identical to the

  data sent by the sending component.

  There are several known solutions aimed at overcoming this major drawback

  fast links between circuits.

  A first known solution consists in parallelizing the data and simultaneously transmitting several data signals. In this way, the data transmission speed, and therefore the frequency of the exchange clock, can be reduced. This first known solution has several drawbacks. In fact, the parallelization of the data leads to an increase in the number of input and output pins on the transmitter and receiver components. Such an increase in the number of pins leads to choosing, for the components, a

  larger packaging and therefore more expensive.

  In addition, this parallelization of data tends to increase the complexity of the components (and in particular of the logic means included in these components), the

  surface area and the cost of these components therefore also being increased.

  A second known solution consists in calibrating as best as possible, in the receiving component, the received data signals and the exchange clock, so as to guarantee

  sampling these data signals.

  However, such a setting requires a prior measurement of the phase of the data signals with respect to the exchange clock, this prior measurement subsequently making it possible to adjust the phase to a value guaranteeing the correct sampling of the

  data signals by the exchange clock.

  Such an approach is very costly and cannot in any case be subject to

industrial development.

  A third known solution consists in implementing a phase locked loop (or PLL (for "Phase Locked Loop") in the transmitter component, in order to guarantee a fixed phase at the exchange clock.

  used by the logical transmission means of this transmitting component.

  This third known solution also has several drawbacks.

  In fact, the use of a PLL requires the use of external components (such as capacitors, resistors and delay lines), and, by

  Therefore, the use of additional pins.

  In addition, PLLs introduce jitter into the transmitted data signals

  and therefore reduce the sampling possibilities in the receiving components.

  Finally, the realization of a PLL requires the integration of analog functions difficult to implement with the technology generally used,

namely CMOS technology.

  The object of the invention is in particular to overcome these various drawbacks

state of the art.

  More specifically, an objective of the invention is to provide a device intended to guarantee a phase that is substantially fixed with respect to an exchange clock to data signals generated by logic means for transmitting a

electronic component.

  The invention also aims to provide such a device requiring no increase in the number of pins on the electronic components (whether they are input, output, or intended for

  receive external components).

  Another objective of the invention is to provide such a device which is inexpensive and which can be integrated industrially into the electronic component,

  it guarantees the phase of the output data signals.

  An additional objective of the invention is to provide such a device

  which does not require any integration of analog functions.

  These objectives, as well as others which will appear subsequently, are achieved according to the invention using a signal alignment device, intended to guarantee a substantially fixed phase, relative to an exchange clock. , to data signals generated by transmission means of an electronic component, said device comprising: transcoding means associating with at least one parameter affecting the propagation times inside said electronic component a duration of phase shift substantially proportional to said propagation times; and phase-shifting means making it possible to phase-shift said exchange clock by a duration equal to said phase-shift duration, and delivering a phase-shifted exchange clock, said phase-shifted exchange clock being used by said transmission means for

  generating said data signals.

  Thus, the exchange clock undergoes a delay (or phase shift) before being used, by the logic transmission means of the electronic component, to generate the data signals, this delay being a function of at least one parameter.

  of use of the electronic component.

  In this way, even for a very high exchange clock frequency, the phase of the data signals is substantially fixed with respect to the exchange clock In any event, even if, despite the correction made by the device according to the invention, the phase of the data signals can vary slightly between a minimum value and a maximum value, a change in value of these data signals is always located between two same exchange clock edges,

  whatever the actual value (minimum or maximum) of the phase.

  In other words, the exchange clock is delayed the more the component is fast (i.e. the propagation time inside this

component is weak).

  This makes it possible to be certain that the sampling of the data signals by the exchange clock (in the receiving component) gives identical data values whatever the technological parameters and the conditions.

  of use of the transmitter component.

  Advantageously, the said parameter or parameters affecting the propagation times

  tion inside said electronic component belong to the group includes the manufacturing process of the component the temperature of the component;

  the component supply voltage.

  In an advantageous embodiment, the device according to the invention holds

  account for variations of these three types of parameters.

  In an advantageous embodiment of the invention, the device according to the invention also comprises means for evaluating the said parameter or parameters affecting the propagation times inside the electronic component, said evaluation means delivering to said means of transcoding a speed value of said component inversely proportional to the propagation times inside

of said component.

  Such real-time evaluation means are notably described in the joint patent application entitled "Device for evaluating a coefficient affecting the propagation times within a logic integrated circuit" and

  filed in the name of the same depositors.

  Applied to an emitting component, this evaluation device delivers a binary value depending on the technological parameters and the conditions of use of this component, this value being proportional to the speed of the component (i.e. inversely proportional to the times propagation inside the component). In a preferred embodiment of the invention, said transcoding means implement a transcoding law aimed at compensating for at least one of the following types of propagation time dispersion: the propagation time dispersions affecting said clock d exchange before it arrives at said device; the propagation time dispersions induced by said phase shifting means; the propagation time dispersions induced by said means

  transmission logic of the electronic component.

  Such a transcoding law is for example determined from the results of simulations executed in maximum propagation time and then in time

minimal propagation.

  Advantageously, said transcoding means comprise either a read-only memory;

  or an integrated programmable network.

  Preferably, said phase-shifting means comprise means for generating a plurality of offset clocks, each of said clocks being offset by a distinct duration relative to said exchange clock; multiplexing means receiving at input said plurality of offset clocks and outputting said phase-shifted exchange clock, said multiplexing means being controlled by control information so as to select the offset clock exhibiting the phase shift with respect to l exchange clock closest to said phase shift duration, and said device comprises decoding means generating said control information from said multiplexing means, the value of said control information being chosen as a function of said phase shift time, the number of possible values of said control information being equal to the number

  clocks offset at the input of said multiplexing means.

  Thus, the different values of the phase shifted exchange clock are obtained by switching different clocks phase shifted between them. Furthermore, the multiplexing means are for example of the type described in the joint patent application entitled "Multiplexer N inputs / 1 output, of the type receiving at input N clock signals of the same frequency and phase shifted each

  compared to others "and filed on behalf of the same applicants.

  Such a fast clock multiplexer guarantees selection without interference

  (or glitch) of a fast clock among a plurality of offset fast clocks.

  Advantageously, said generation means comprise a plurality of elementary phase shifters wired in series and each phase shift of an elementary duration, said offset clocks being phase shifted between them by

  two of said elementary duration.

  The elementary duration is for example determined so that the most offset clock ensures, in minimum propagation time, the maximum delay

  ensuring the fixed phase of the data signals relative to the exchange clock.

  Advantageously, the device according to the invention comprises means for progressive modification of said phase shift duration, said progressive modification means generating a new modified phase shift duration equal to: the result of the addition of a predetermined progression time and the previous modified phase shift time, when said previous modified phase shift time is less than the phase shift time provided by said transcoding means, as a result of subtracting said predetermined progression time from the previous modified phase shift time, when said duration previous modified phase shift is greater than the phase shift time provided by said transcoding means; to said previous modified phase shift duration, when said previous modified phase shift duration is equal to the duration of

  phase shift provided by said transcoding means.

  In this way, the phase jumps on the phase-shifted exchange clock are limited.

  Thus, in the case where the phase shifting means comprise a multi-

  plexer of staggered fast clocks, interference-free multiplexing is facilitated.

  Preferably, said predetermined progression time is equal to

said elementary duration.

  The device according to the invention can, for example, be used for

  a frequency of said exchange clock substantially equal to 166 M Hz.

  Other characteristics and advantages of the invention will become apparent on

  reading of the following description of a preferred embodiment of

  the invention, given by way of non-limiting example, and the accompanying drawings, in which FIG. 1 presents a simplified logic diagram presenting an exchange of data between a transmitting electronic component and a receiving electronic component, the transmitting electronic component comprising a device according to the invention; Figure 2 shows examples of timing diagrams showing * the exchange clock;

  * the data signals generated by an electronic component

  that of the state of the art, on the one hand in time of

  minimal propagation and on the other hand in propagation time

maximum tion;

  * the data signals generated by an electronic component

  that comprising a device according to the invention, on the one hand in minimum propagation time and on the other hand in maximum propagation time; Figure 3 shows a simplified logic diagram of an embodiment of a device according to the invention as presented in Figure 1; Figure 4 shows examples of signal timing diagrams

shown in Figure 3.

  The invention therefore relates to a device intended to be installed in an emitting electronic component in order to guarantee a substantially fixed phase with respect to an exchange clock to data signals generated by this

transmitter electronic component.

  FIG. 1 presents a simplified logic diagram presenting an exchange of data between such a transmitting component 11 and a receiving component 12 These two components 11, 12, placed on the same printed circuit, exchange these

  data in the form of data signals 13.

  More specifically, the device according to the invention 15 receives an exchange clock 14 and delivers a phase-shifted exchange clock 16 This phase-shifted exchange clock 16 is used by logic means 17 for transmitting the

  transmitter component 11 for generating data signals 13.

  These data signals 13 are received by the receiver component 12 and logic means 18 for reception, placed in this receiver component 12, in

  extract data using the exchange clock 14.

  The duration of the phase shift applied to the exchange clock 14 in order to obtain the phase shifted exchange clock 16 is proportional to the propagation times inside the transmitter component 11, and guarantees that the data signals 13

  phase substantially fixed with respect to the exchange clock 14.

  Thus, the logic means 18 for receiving (placed in the receiver component 12) can perform a correct extraction of the data contained in the data signals 13 Indeed, such an extraction, which generally consists in sampling the data signals 13 on the edges amounts of the exchange clock 14, is only possible if the values taken by the data signals (at

  know "O t" or "1") during each amount of exchange clock amount are guaranteed.

  The device according to the invention 15 aims precisely to provide such a guarantee. The examples of chronogranimes presented in FIG. 2 make it possible to better understand one of the problems to which the device according to the invention provides

a solution.

  In this figure 2, there is shown: a timing diagram 21 representing the exchange clock two timing diagrams 22, 23 representing the data signals

  generated by a transmitter component of the state of the art (i.e.

  ie a transmitter component whose logic transmission means directly use the exchange clock to generate the data signals) in minimum propagation time and in maximum propagation time respectively; two timing diagrams 24, 25 representing the data signals generated by a transmitter component comprising a device according to the invention (that is to say a transmitter component whose logic transmission means use phase-shifted exchange clock instead of l exchange clock to generate the data signals) in minimum propagation time and in maximum propagation time respectively. On each of the timing diagrams 22 to 25 representing signals of

  data generated, there is an instant 26 of change of state.

  For the sake of simplification, it is assumed in the following description that

  the values of the data signals before and after the instant 26 of change of state

are respectively "O" and "1".

  As can be seen with the pair of chronograms referenced 22, 23, in the case of signals generated by a component of the state of the art, the instant 26 of change of state is not always located between the same two foreheads

  successive amounts of the exchange clock.

  With a minimum propagation time Tn 1 ,,, (timing diagram 22), one obtains, after sampling during the two successive edges referenced 26, 27, the

series of values "11".

  On the contrary, with a maximum propagation time Tmaxi, (timing diagram 23), one obtains, after sampling during the same two successive fronts 26, 27,

the sequence of values "01".

  It is clear from this example that the values taken by the data signals are not guaranteed during sampling. This is due to the fact that the period of the exchange clock being very short, the propagation time can be

  lower or higher than this period.

  On the other hand, as can be seen with the pair of chronograms referenced 24, 25, in the case of signals generated from an exchange clock phase shifted by a device according to the invention, the instant 26 of change of state is always

  located between the same two successive rising edges of the exchange clock.

  In this case, let the propagation time be minimal Tmi, 2 (chrono-

  gram 24) or maximum T, X 2 (chronogram 25), after sample-

  swims during the two successive fronts 26, 27, the series of values "01".

  The principle of the invention therefore consists in taking into account the value of

  propagation time For this, we delay the proportional exchange clock-

  ment to this propagation time value, so that the phase of the data signals is substantially fixed with respect to the exchange clock In any event, any variation in this phase must be small enough that, whatever whatever the value of the propagation time, the different possible instants of change of state (corresponding to the different values of the propagation time) are always located between the same two successive edges of

the exchange clock.

  Figure 3 shows a simplified logic diagram of an embodiment

  of a device according to the invention as presented in FIG. 1.

  According to this embodiment, the device comprises: means 31 for dividing (denoted DIVIDER) of the exchange clock 14 (denoted CKIN); means 32 for evaluating (denoted MESTECH) the parameters affecting the propagation times inside the electronic transmission component in which the device according to the invention is placed; transcoding means 33 (denoted TRANSCOD) making it possible to calculate a phase shift duration proportional to the propagation times; means 34 for progressive modification (denoted PROGRES 51) of the phase shift duration; decoding means 35 (denoted DECOD 5 X 32) generating control information as a function of the phase shift duration; means 36 for generating (denoted DEPHASCLOCK) a plurality of offset clocks; multiplexing means 37 (denoted MUX 532 X 1) making it possible to select one of the clocks shifted as a function of the control information generated by the decoding means 35, the shifted clock selected corresponding to the phase shifted exchange clock

16 (noted CKOUT).

  The means 31 for dividing the exchange clock 14, for example made up of synchronous counter cells, generate the different clock signals necessary for the device. In the embodiment presented, the five clocks necessary for the device, denoted CK 4 B , CK 8, CK 16, CK 16 B and CK 128, correspond to the exchange clock 14 respectively divided by 4 and inverted,

  divided by 8, divided by 16, divided by 16 and inverted, and divided by 128.

  The means 32 for evaluating the parameters affecting the propagation times inside the component are of the type described in the joint patent application entitled "Device for evaluating a coefficient affecting the propagation times within a logic integrated circuit "and filed on behalf of

same depositors.

  From the two clocks CK 8 and CK 4 B of the same phase and whose ratio of the two periods is equal to two, these evaluation means 32 deliver to the transcoding means 33 a value Cl 4: 0 l of speed of the component which East

  inversely proportional to the propagation times inside the component.

  The parameters affecting the propagation times thus taken into account are the manufacturing process of the component the temperature of the component;

  the component supply voltage.

  Thus, the faster the component (i.e. the shorter the propagation times), the greater the value Cl 4: 0 l is important In this example, the value Cl 4: 0 l is a coded mean value on 5 binary elements and generated

  at the clock frequency CK 128.

  In this embodiment, this value Cl 4: 0 l represents, before transcoding, the number of shifts (of an elementary duration) that the exchange clock 14 must undergo in order to have a fixed phase with respect to the signals of

data emitted by the component.

  Finally, these evaluation means 32 also deliver information

  MESOK indicating whether the Cl 4: 0 l value supplied is correct.

  The transcoding means 33 receive the value Cl 4: 0 l and transcode it into another value Dl 4: 0 l intended to compensate for time distortions of

spread.

  This transcoding is carried out using a transcoding law and the compensated propagation time distortions are, for example, those: of the exchange clock CKIN before it arrives at the device according to the invention ; induced by the means 37 for multiplexing offset clocks

  induced by the logical means of emission of the electronic component

  than. This transcoding law can be determined in the following way simulations are executed, in maximum propagation time then in minimum propagation time, in order to determine the number of shifts to be added to the values Cl 4: 0 l corresponding to these two cases; from these two offset numbers corresponding to the times

  minimum and maximum propagation, we deduce the law of transco-

  dage. According to a first assembly, the transcoding means 33 comprise a ROM type ROM, with the values Cl 4: 0 l possible in addresses and the

  Dl 4 values: 0 l possible at output.

  According to a second arrangement, the transcoding means 33 comprise an integrated programmable network. This network can, for example, be pre-initialized in the component, then reprogrammed when the component is actually implemented, in order to correct any additional dispersions or even refine

the compensation implemented.

  For example, the transcoding law aimed at compensating only for the dispersion of the multiplexing means 37 is Y 2 = 2 Y 1 6 if Y 1 26 Y 2 = 6 if Y 1 <6 with Y 1 the value Cl 4: 0 l provided by means 32 of evaluation

Y 2 the value Dl 4: 0 l transcoded.

  Like the value Cl 4: 0 l, the value Dl 4: 0 l transcoded is generated at the

clock frequency CK 128.

  At a frequency (namely that of the clock CK 16 in this example) faster than the frequency of generation of the transcoded value (namely the frequency of the clock CK 128 in this example), the means 34 for progressive modification generate a new modified transcoded value El 4: 0 l equal to the previous modified transcoded value: incremented by 1, if the previous modified transcoded value is less than the received transcoded value; decremented by 1, if the previous modified transcoded value is greater than the received transcoded value; as is, if the previous modified transcoded value is equal

to the transcoded value received.

  Thus, the modified transcoded value El 4: 0 l varies, at most, only by

+ 1 or -1.

  Consequently, the phase shift duration applied to the exchange clock varies, at most, only by an elementary duration. In this way, we avoid

  generate high amplitude phase jumps on the phase shifted exchange clock 16.

  The decoding means 35 receive the modified transcoded value El 4: 0 l

  and generate order information.

  In the embodiment presented, the modified transcoded value El 4: 0 l is coded on 5 binary elements and there are therefore 32 distinct states possible. At the output of the decoding means 35, there are as many control signals DECBl 31: 0 l (namely 32) as possible distinct states of the modified transcoded value El 4: 0 l and each control signal corresponds to a distinct state of the

modified transcoded value.

  The generation of the control information consists in putting in the active state only the control signal corresponding to the state of the transcoded value

modified El 4:01.

  The means for generating a plurality of offset clocks receive as input the exchange clock CKIN and deliver as output 31 clocks Al 31: 1 l shifted between them two by two with an elementary duration and an integer (including

  between 1 and 31) of elementary durations compared to the CKIN exchange clock.

  The generation means 36 comprise, for example, a plurality (31 in this example) of elementary phase shifters wired in series and each phase shift

of elementary duration.

  Thus, taking into account the non-phase-shifted exchange clock Ar OI, we

  has 32 clocks offset Al 31:01.

  The elementary duration is determined so that the most offset clock (in this example, that shifted by 32 elementary durations) ensures, in minimum propagation time, the maximum delay guaranteeing the fixed phase of the signals of

  data compared to the CKOUT exchange clock.

  The multiplexing means 37 receive as input the plurality of offset clocks Al 31: 0 l and output the phase shift exchange clock 16 (CKOUT)

  depending on the state of the control signals.

  Indeed, the offset clock applied at the output is the one whose signal

  associated command is in active state.

  Such a fast clock multiplexer without parasite (or glitch) at output is for example described in the joint patent application entitled ("Multiplexer n inputs / 1 output, of the type receiving at input N clock signals of the same frequency and phase shifted relative to each other ") and filed on behalf of

same depositors.

  In this case, the condition to be fulfilled to avoid any asynchronous problem

  nism when sampling DECBl 31: 0 l signals for controlling the multiplexer is that these signals have a propagation time with respect to the exchange clock CKIN less than the period CKIN minus the time of

  prepositioning of the flip-flops implemented in the multiplexer.

  The dividing means 31, the evaluation means 32, the progressive modification means 34 and the multiplexing means 37 can be reset

  via the reset signal RSTB.

  At 155 M Hz and with 0.6 / m technology, the embodiment

proposed works without problem.

  FIG. 4 presents an example of timing diagrams of the main signals presented in FIG. 3, namely: CK 16: the exchange clock CKIN divided by 16; CK 128: the CKIN exchange clock divided by 128; Cl 4: 0 l: the value supplied by the evaluation means 32 Dl 4: 0 l: the transcoded value; El 4: 0 l: the modified transcoded value; DECB (n-1) (respectively DECB (n), DECB (n + 1), DECB (n + 2)): the control signal (among the 32 possible) in the active state during the (nl) th (respectively (n) th (n + l) th, (n + 2) th) period of

the clock CK 16.

  FIG. 4 also presents a chronogram (denoted CLUTCH SWITCHING CKOUT) indicating the switching times of the phase shifted exchange clock. As shown in these timing diagrams, the values Cl 4: 0 l and Dl 4: 0 l are generated at the rate of the clock CK 128 while the value El 4: 0 l is generated at

clock rhythm CK 16.

  Each DECB control signal switches to the active state at the rate of

the clock CK 16.

  Finally, the phase-shifted exchange clock CKOUT switches between two

  clocks offset by an elementary duration at the rate of the clock CK 16.

Claims (8)

  1 signal alignment device (15), intended to guarantee a substantially fixed phase, relative to an exchange clock, (14) to data signals (13) generated by transmission means (17) d '' an electronic component (11),   characterized in that it comprises transcoding means (33) associating with at least one parameter affecting the propagation times inside said electronic component a phase shift duration substantially proportional to said propagation times; and phase-shifting means (36, 37) making it possible to phase-shift said exchange clock (14) by a duration equal to said phase-shift duration, and delivering a phase-shifted exchange clock (16), said phase-shifted exchange clock (16) being used by said means (17)   transmission to generate said data signals (13).   2 Device according to claim 1, characterized in that the said parameter or parameters affecting the propagation times inside said electronic component belong to the group comprising: the component manufacturing process the temperature of the component;   the component supply voltage.   3 Device according to any one of claims 1 and 2,   characterized in that it also comprises means (32) for evaluating said parameter or parameters affecting the propagation times inside the electronic component, said evaluation means (32) delivering to said transcoding means a speed value of said inversely proportional component   propagation times inside said component.   4 Device according to any one of claims 1 to 3,   characterized in that said transcoding means (33) implement a law of trance of own character. coding intended to compensate for at least one of the following types of igation time dispersion the propagation time dispersions affecting said exchange clock (14) before it arrives at said device; the propagation time dispersions induced by said phase shifting means (37); the propagation time dispersions induced by said means   (17) emission of the electronic component.   Device according to any one of Claims 1 to 4,   in that said transcoding means (33) includes a memory   6 Device according to any one of claims 1 to 4,   characterized in that said transcoding means (33) comprise a network built-in programmable.   7 Device according to any one of claims 1 to 6,   characterized in that said phase shift means comprise: means (36) for generating a plurality of offset clocks (A l 31; 0 l), each of said clocks being offset by a distinct duration with respect to said clock d 'exchange (14); multiplexing means (37) receiving as input said plurality of offset clocks (A l 31: 0 l) and outputting said phase shifted exchange clock (16), said multiplexing means (37) being controlled by information control (DECB l 31: 0 l) so as to select the offset clock having the phase shift with respect to the exchange clock (14) closest to said phase shift duration, and in that said device comprises decoding means (35) generating said control information (DECB l 31: 0 l of said multiplexing means (37), the value of said control information being chosen as a function of said phase shift duration, the number of possible values of said control information being equal to the number of clocks offset (A l 31: 0 l at the input of said means (37) multiplexing.   8 Device according to claim 7, characterized in that said generating means (36) comprise a plurality of elementary phase shifters wired in series and each phase shifting by an elementary duration, said offset clocks (A l 31: 0 l) being phase shifted they two by two of said elementary duration.   9 Device according to any one of claims 1 to 8,   characterized in that it comprises means (34) for progressive modification of said phase shift duration, said means (34) for progressive modification generating a new modified phase shift duration equal: to the result of the addition of a progression duration predetermined and of the preceding modified phase shift duration, when said preceding modified phase shift duration is less than the phase shift duration provided by said transcoding means; the result of subtracting said predetermined progression duration from the preceding modified phase shift duration, when said previous modified phase difference duration is greater than the phase difference duration provided by said transcoding means; to said previous modified phase shift duration, when said previous modified phase shift duration is equal to the duration of   phase shift provided by said transcoding means.   Device according to claims 8 and 9, characterized in that said   duration of predetermined progression is equal to said elementary duration.