FR2701189A1 - Method of fabricating a high-density multi-layer hybrid circuit and circuit obtained - Google Patents

Abstract

On a substrate (S), a conducting level (C1) is deposited by screen printing, with a set of markers (R1). Next, a first layer (D11) forming a photosensitive dielectric is deposited on the conducting level (C1) without covering the set (R1), by screen printing, and it is dried. Vias are etched in the first dielectric layer thus dried, with respect to the conducting level (C1), being aligned on the said set (R1), and it is fired. On the first dielectric layer (D11) thus fired and without covering the said set (R1), a second layer is deposited by screen printing, formed by a photosensitive dielectric identical to that of the first layer, and this is repeated until a second dielectric layer (D12) is obtained, etched and fired; and, on the second fired dielectrical layer (D12) thus obtained, another level (C2) is deposited by screen printing, formed by a conductor with another set of markers (R2), and this is repeated until complete fabrication of the circuit.

Description

Method for manufacturing a high density multilayer hybrid circuit and circuit obtained
The invention relates to the manufacture of a high density multilayer hybrid circuit.

It finds general application in microelectronics and more particularly in the manufacture of components in thick layers (THICK FILM).

Numerous methods are known for making multi-layer hybrid circuits.

The deposits by screen printing are the most widespread processes for generating the conductive lines and the electric holes (or vias) connecting together the active components and the passive components assembled on the insulating substrate of the multilayer hybrid circuit.

Des. improvements recently made to screen printing techniques have made it possible in particular to generate conductive lines less than 100 micrometers wide in an industrial environment
However, even using such refinements, the resolution of the vias fails to keep up with such reduction.

Indeed, a resolution for dielectric vias of the order of 200 to 250 micrometers is currently considered to be the limit for manufacturing the deposits by screen printing.

To overcome this limit in order to improve the density or resolution of the circuits, photosensitive dielectric pastes capable of making vias of less than 50 micrometers in diameter have been developed and methods for manufacturing multi-layer hybrid circuits using such pasta has been proposed in the literature.

The Applicant has posed the problem of bringing technical improvements to these processes in order to successfully apply them in an industrial environment.

The invention relates to a method of manufacturing a multilayer hybrid circuit.

According to a general definition of the invention, it comprises the following steps - a) on a substrate, depositing by screen printing a first level formed of a predetermined conductive material with patterns comprising a first set of marks arranged on predetermined areas of the first conductive level - b) on the first conductive level thus deposited, without covering said first set of marks, deposit by screen printing a first layer formed of a predetermined photosensitive dielectric material until a chosen thickness is obtained - c) dry the first dielectric layer photosensitive thus deposited - d) etching vias by microphotolithography, in the first dielectric layer thus dried, selectively with respect to the first conductive level, by aligning with said first set of marks, and baking at a chosen temperature and for a duration choose the first dielectric layer thus etched - e) on the first c dielectric sheet thus baked and without covering the first set of marks, deposit by screen printing a second layer formed of the same photosensitive dielectric material as the first layer and repeat steps c) and d) until a second dielectric layer is etched and baked; and - f) on the second baked dielectric layer thus obtained, deposit by screen printing a second level formed of a predetermined conductive material with patterns comprising a second set of marks arranged on predetermined areas of the second conductive level, and repeat steps b ), c), d), and e) until the circuit is completely manufactured.

Thus, for all the deposition and etching operations relating to the constitution of a stage of the circuit, it is planned to align with the set of marks inscribed on the conductive level of said stage, which makes it possible to improve, at level of depth of field, adjustment and development of the means involved in the constitution of said stage.

In practice, each dielectric layer consists of - a first sublayer formed of a predetermined photosensitive dielectric material, deposited by screen printing without covering the set of marks, and dried, and - a second layer formed of the same material dielectric than the first sublayer, deposited by screen printing on said first sublayer, without covering the set of marks, and dried.

This embodiment with two dielectric sublayers applies in particular when it is desired to reach a total thickness of dielectric, for example of the order of 40 micrometers, once dried.

According to another preferred embodiment of the invention, the method further comprises after step e), the following step - ei) on the second baked dielectric layer thus obtained, depositing by screen printing a predetermined conductive material to fill the vias etched in the first and second dielectric layers.

In practice, etching by microphotolithography includes the following steps - providing a photosensitive mask having opaque areas representative of the vias to be etched and transparent areas - exposing the photosensitive layer to be etched through the photosensitive screen - developing the photosensitive layer thus exposed so that the unexposed areas corresponding to the vias are selectively etched; and - drying and baking at a selected temperature and for a predetermined period of time the layer thus etched.

In practice, the deposition by screen printing comprises the following steps - providing a screen-printing mask with mesh of selected section - depositing the layer through the screen-printing mask; and - drying the layer thus deposited.

Preferably, the first and second sets of marks are arranged relative to each other according to a predetermined geometric relationship.

In practice, markers are crosses.

In another embodiment of the invention, the patterns are etched in the conductive level by microphotolithography.

The present invention also relates to a multilayer hybrid circuit obtained according to the manufacturing process mentioned above.

Very advantageously, the diameters of the vias of the circuit obtained according to the method according to the invention are of the order of 100 micrometers.

In practice, the substrate is partly formed of alumina.

In practice, the conductive level is formed from a material in the pasty form containing gold, copper or silver.

For example, the dielectric layers are formed of a photosensitive dielectric material in the form of a paste.

 Other characteristics and advantages of the invention will appear in the light of the detailed description below and of the appended drawings in which - FIG. 1 represents a flowchart illustrating the steps of the method according to the invention - FIG. 2 schematically represents the location marks according to the invention - Figure 3 is a schematic representation of an alignment mark in the form of a Greek cross according to the invention - Figures 4A to 4D schematically represent the stages of microphotolithography according to the invention; and - Figures SA to 5D schematically represent, in more detail, the etching of the vias according to the invention.

In Figure 1, there is shown a flowchart illustrating a method of manufacturing hybrid multilayer circuits which is inspired by that described in the document "A NEW THICK
PHOTOIMAGEABLE FILM TECHNOLOGY FOR HIGH DENSITY INTERCONNECT "by Gérard VANRIETVELDE, DU PONT DE NEMOURS, June 1992.

It is a process for manufacturing a multilayer hybrid circuit using a photosensitive dielectric paste and a conductive level traditionally deposited by screen printing.

The number of process operations takes into account the resolution of the vias to be obtained, that is to say here for example 50 micrometers.

During step 10 (FIGS. 1 and 4A), on a substrate S, a first level C1 formed of a predetermined conductive material is deposited in a conventional manner by screen printing.

For example, the substrate S is 90-99% alumina.

The conductive level C1 is deposited according to the conventional screen printing steps, that is to say deposit, through a screen printing screen comprising meshes of selected section, of a conductive ink.

For example, the conductive ink consists in part of gold, copper or silver.

For example, the thickness of the starting conductor level is of the order of 16 micrometers and after the drying (step 12) and baking (step 14) operation of the order of 9 micrometers.

The drying step 12 is carried out for example at a temperature of the order of 1500C for a period of the order of approximately 10 minutes.

The cooking step 14 is carried out in an oven at a temperature of the order of 8500C for a period of approximately 10 minutes.

The complete cycle relating to the constitution of a conducting level Cn is of the order of 60 minutes.

It should be noted that a first visual control operation V1, inserted between step 12 and step 14, as well as a second visual control operation V2, after step 14, are provided to visually check the correct conduct of the driver's deposit.

During the stage of deposition by screen printing of the conductive level, patterns are produced in this level.

In general, these patterns constitute in particular the conductive lines of the hybrid multilayer circuit.

According to the invention, it is planned to produce by screen printing patterns further comprising a set of marks R1 also called alignment patterns, arranged on predetermined areas of said conductor level.

Preferably, this set of marks R1 is disposed at the periphery of the conductor level C1 thus deposited.

Advantageously, this set of marks R1 comprises Greek crosses of selected dimensions.

In FIG. 2, the set of alignment marks comprises at least three Greek crosses individualized in Roll, R12 and R13 and produced on the substrate S outside the useful area
ZU of the circuit.

In practice, the substrate S forms a parallelogram and the crosses are located at the corners of said parallelogram.

Preferably, the crosses R11 and R12 are aligned with respect to each other in a plane parallel to that of the substrate, while the crosses R13 and R12 are aligned with each other in a perpendicular plane to that of the substrate.

For example, the length L1 and the width L2 of the branches of the crosses R11 to R13 are respectively of the order of 40 mils (1.016 mm) and 3.75 mils (95.25 micrometers) (Figure 3).

During step 16, on the first conductive level C1 thus deposited, without covering the set of marks R1, there is deposited by screen printing a first sublayer D111 formed of a predetermined photosensitive dielectric material.

The first D111 sublayer consists of a photosensitive dielectric paste. For example, the dielectric paste is that sold by the company DU PONT DE NEMOURS under the reference 6050 D.

This paste contains a monomeric photosensitive resin similar to that used in conventional photolithography (PHOTORESIST FILMS).

For example, the first D111 sublayer is deposited by screen printing through a screen mask comprising meshes from 325 to 200 mesh depending on the desired thickness.

In practice, this first starting D111 sublayer has a thickness of the order of 40 micrometers.

Once deposited by screen printing, the layer D111 is dried for a period of the order of 10 minutes at a temperature of 85 ° C., which leads to a thickness of the order of 20 micrometers.

According to the invention, the drying operation is carried out by means of hot plates.

The drying operation using hot plates allows rapid drying (faster than using an oven).

In particular, it prevents the appearance of the skin effect phenomenon (drying of the surface before drying of the core of the product): phenomenon which appreciably slows drying by preventing the solvents from being evacuated from the bottom to the top (the top being already dry, therefore more airtight to gases and solvents).

For example, the viscosity of the dielectric paste is of the order of 70 to 120 Pascals per second.

On the first dielectric sublayer D111 thus dried, provision is made for the deposition by screen printing of a second sublayer D112 formed of the same dielectric material as the sublayer Dll1.

According to the invention, this deposition by screen printing is carried out without covering the set of marks R1.

Advantageously, this second starting D112 sublayer has a thickness of the order of 40 micrometers in order to obtain a thickness of the order of 20 micrometers after drying by hot plates of a duration of the order of 15 minutes.

Thus, after step 18, a first layer D11 is obtained consisting of the first and second dry sublayers D111 and D112 with a total thickness of the order of 40 micrometers.

 At 1 after step 18, the circuit is in a configuration which corresponds to that of FIG. 4A with the conductive level C1 and an upper layer, here constituted by the dielectric layer D11.

During step 20 which also corresponds to FIGS. 4B and 5A, the dielectric layer D11 is exposed through a photographic PHM photomask or a hard mask made of glass or polyester.

The PHM photomask includes opaque areas OPA and transparent areas TRA. The opaque areas OPA represent the vias to be etched in the dielectric layer because it is a question here of subtractive photolithography.

LIG ultraviolet light, for example from a high-pressure mercury lamp, with a power of the order of 1000 Watts, illuminates the photomask for approximately 2 to 4 seconds. This exposure takes place in an atmosphere of nitrogen or air.

The nitrogen atmosphere advantageously removes oxygen which is a polymerization inhibitor.

The photosensitive resin included in the dielectric paste polymerizes (FIG. 5B) at the unexposed areas POLY corresponding to the VA vias.

During step 22 (FIG. 5C), the photosensitive resin thus polymerized is developed.

This development (FIG. 4C) is carried out from an DEV development system with aqueous diffusion, for example that usually used during microphotolithography stages for the printed circuit industry.

For example, the DEV system diffuses a chemical substance based on sodium carbonate at about 0.8%.

Development involves dissolving and removing areas
POLY that have not been exposed to light (Figure 5D).

This dissolution is carried out by chemical operations comprising a neutralization of the surface, a hydration of the ions and by the dissolution as well as the physical removal of said unexposed parts.

On the other hand, the exposed parts resist this chemical treatment, which makes it possible to obtain VA vias of a chosen diameter.

Then, the developed parts are dried either under pressurized air or in an oven at 750 Celsius for a few minutes.

Finally, the dielectric parts thus developed are baked by passing through an oven at a temperature of around 8500C in air for a period of around 10 minutes.

The complete cycle for the formation of an etched dielectric layer is approximately 60 minutes.

At the end of step 24, a baked dielectric layer of the order of 20 micrometers is thus obtained with resolution vias of the order of 100 micrometers or less.

Visual control operations V3 and V3bis are provided respectively between step 22 and step 24 and between step 24 and step 26 mentioned below.

Very advantageously, the etching of the vias by photolithography described above, selectively with respect to the conductive level Cl, is carried out by aligning with the set of marks inscribed in said conductive level Cl.

More specifically, the means for adjusting the screen printing and photolithography masks, as well as the means for exposing the photosensitive resin are adjusted and aligned with this set of marks R1.

This results in an important advantage in terms of adjusting the depth of field of the means mentioned above.

During step 26, on the first dielectric layer Dll thus etched and without covering the set of marks R1, a second layer formed of a photosensitive dielectric material identical to that of the first layer is deposited by screen printing and it is repeated steps 16, 18, 20, 22, 24 until a second etched dielectric layer D12 is obtained.

Steps 26, 28, 30, 32 and 34 relating to or associated with the second dielectric layer are thus identical respectively to steps 16, 18, 20, 22 and 24.

Very advantageously, the means for adjusting the screen printing and photolithography masks, the exposure means relating to the second layer D12 are also adjusted and aligned on the set of marks R1.

During step 36, the second etched dielectric layer thus obtained D12 and baked at 850 C is applied to the deposition by screen printing of a predetermined conductive material to fill with a conductive material the vias VAn etched in the first and second dielectric layers.

Then, during step 38, provision is made for heating the circuit to a temperature of the order of 80 ° C. for a duration of the order of 10 minutes, followed finally by cooking at 8500C (step 40).

A step relating to the visual control VS is also provided at the end of step 40.

The filling of the vias with a conductive material can be carried out through a metallic screen of the foil type, for example of electroformed nickel ("Stencil" in Anglosaxon).

For example, the conductive layer filling the VAn vias is a paste with a predetermined viscosity sold by the
DU PONT DE NEMOURS company under reference 5727.

This filling is carried out in the same way as a deposit by screen printing using the specific screen of the metallic foil type.

As a variant, the filling can be carried out from an operation by subtractive photolithography using a conductive ink of the type sold by the Company DU
PONT DE NEMOURS under reference 1056-2.

This conductive ink is in the form of a pasty ink having a predetermined viscosity and partly formed of gold.

At the end of step VS, the dielectric assembly consisting of the first and second layers D11 and
D12, the vias of which are filled, upon deposition by screen printing of a second conductive level C2 formed of a predetermined conductive material with patterns comprising a second set of marks R2 arranged on predetermined areas of the second conductive level C2.

Finally, steps 12 to VS are repeated until the complete manufacture of the circuit.

Preferably, the first and second sets of marks R1 and R2 are arranged with respect to each other according to a predetermined geometric relationship. In practice, they are spaced from each other by a distance of the order of 3 millimeters in the vertical plane.

 In practice, provision is made on the masks of the conductive levels VAn and Cn + 1 to further create a set of additional marks Pn comprising marks or test marks in the form of a Greek cross of smaller dimensions than those of the marks Rn and situated opposite on the vertical plane of said marks Rn.

For example, the length and width of the crosses Pn are respectively of the order of 30 mils (0.762 millimeters) and 2 mils (50.8 micrometers).

In a particular application, the circuit may consist of six stages, each comprising a conductive level Cn, two dielectric layers Dnl and Dn2, and a filling of vias VAn.

Alternatively, to obtain conductive lines of better revolution, the conductive level Cn consists of a photosensitive conductive material in the pasty form.

For example, the conductive paste is that sold by the
DU PONT DE NEMOURS company under reference 1056-2 made partly of gold.

The screen printing and photolithography steps relating to this conductive paste are substantially identical to those described above.

For example, the screen printing screen is a screen from 325 mesh to 400 mesh depending on the desired thickness.

The starting conductive layer Cn has a thickness of the order of 25 to 30 micrometers. It is advantageously dried on a hot plate at a temperature of around 85 C for 10 minutes to obtain a thickness of around 16 micrometers.

The part thus dried is then exposed through a photomask in a similar manner to that already described for the dielectric paste.

The unexposed parts are removed during the engraving.

Furthermore, a longer exposure time is required because of the reflective nature of the conductive materials.

The exposure time of a polymer base based on gold requires approximately 500 millijoules per square centimeter, while that based on copper requires 750 millijoules per square centimeter for a line.

The development of the photosensitive conductive layer uses a 0.8% sodium carbonate solution for approximately 15 seconds.

For gold, the developed parts are baked in an air oven at a temperature of 850, while for copper, it is baked in an atmosphere of nitrogen doped with oxygen.

The resolution of vias, tracks, or lines, etched by photolithography in the case of a conductive paste of gold or copper is here of the order of 25 micrometers.

The thickness of the baked conductive layer is of the order of 8 micrometers.

Thus, in the variant described above, a stage with a thickness of the order of 48 micrometers is obtained with a conductor with a thickness of 8 micrometers and two dielectric layers of the order of 20 micrometers each.

In another variant, the conductive level Cn is produced in two conductive sublayers. The first sub-layer is produced by screen printing with a 400 mesh screen and a photosensitive paste based on gold, the viscosity of which is chosen to obtain a fine thickness after drying.

For example, the thickness of the first conductive sublayer at the start is of the order of 15 micrometers. After the drying operation, it is of the order of 8 micrometers.

Finally, the first conductive sub-layer is exposed and developed.

The second conductive sublayer is deposited on the first conductive sublayer thus developed. It is produced using a screen printing process identical to that of the first undercoat.

The assembly consisting of the first and second conductive sub-layers thus produced has a total thickness of 16 micrometers (2x8). The first and second conductive sublayers are simultaneously etched and then fired at Celsius.

 The complete cooking cycle relating to the constitution of such a conductive level is of the order of 60 minutes. Such a variant makes it possible to further improve the resolution of the circuit.

In another embodiment of the invention, at the end of the exposure of the first conductive sublayer, provision is made to etch and then to bake the conductive lines thus produced in said first conductive sublayer.

The second conductive sublayer is then deposited by screen printing on the first conductive sublayer thus etched and baked. The density of the conductive layer obtained is thereby improved (increase in the electrical conductivity of the line).

Claims (16)

Claims 1. A method of manufacturing a multilayer hybrid circuit characterized in that it comprises the following steps - a) on a substrate (S), deposit by screen printing a first level (C1) formed of a predetermined conductive material with patterns comprising a first set of marks (R1) arranged on predetermined areas of the first conductor level (C1) ;; - b) on the first conductive level (C1) thus deposited, without covering the first set (R1), deposit by screen printing a first layer (dol) formed of a predetermined photosensitive dielectric material until a chosen thickness is obtained - c) drying the first photosensitive dielectric layer (dol) thus deposited - d) etching vias by microphotolithography, in the first dielectric layer thus dried, with respect to the first conductive level (Cl), by aligning with said first set ( R1), and bake at a selected temperature and for a selected period of time the first dielectric layer thus etched - e) on the first dielectric layer (dol) thus cooked and without covering said first set (R1), deposit by screen printing a second formed layer a photosensitive dielectric material identical to that of the first layer, and repeat steps c) and d) until a second dielectric layer (D12) is etched and baked; and - f) on the second dielectric layer (D12) thus baked, deposit by screen printing a second level (C2) formed of a predetermined conductive material with patterns comprising a second set of marks (R2) arranged on predetermined areas of the second conductor level (C2), and repeat steps b), c), d) and e) until the circuit is completely manufactured. 2. Method according to claim 1, characterized in that each dielectric layer (Dll, D12) consists of - a first sub-layer (D111) formed of a predetermined photosensitive dielectric material, deposited by screen printing without covering said set ( R1), and dried; and - a second sublayer (D112) formed of a dielectric material substantially identical to that of the first sublayer (D111), deposited by screen printing on said first dielectric sublayer, without covering the set of marks ( R1), and dried. 3. Method according to claim 1, characterized in that it further comprises step e) the following step - ei) on the second dielectric layer (D12) baked thus obtained, deposit by screen printing a predetermined conductive material to fill the vias etched in the first and second dielectric layers. 4. Method according to claim 1, characterized in that the etching by microphotolithography includes the following steps - providing a photographic screen or mask (PHM) having transparent areas (TRA) and opaque areas (OPA) representative of the vias to be etched - exposing the photosensitive layer to be etched through the screen (PHM) - developing the photosensitive layer thus exposed so that the unexposed areas corresponding to the vias are selectively etched; and - dry and bake the layer thus etched at a chosen temperature for a predetermined time. 5. Method according to claim 1, characterized in that the deposition by screen printing comprises the following steps - provide a screen mask with very fine mesh - deposit the layer through the screen mask; and - drying the layer thus deposited. 6. Method according to any one of the preceding claims, characterized in that the first and second sets of marks (R1 and R2) are arranged relative to each other according to a predetermined geometric relationship. 7. Method according to any one of the preceding claims, characterized in that the marks are Greek crosses. 8. Method according to any one of the preceding claims, characterized in that the patterns are produced in the conductive level by screen printing. 9. Method according to any one of claims 1 to 7, characterized in that the patterns are produced in the first conductive level by microphotolithography. 10. Method according to any one of the preceding claims, characterized in that the drying operation is carried out by hot plates. 11. Multilayer hybrid circuit obtained by implementing the method according to any one of claims 1 to 10.  12. Circuit according to claim 11, characterized in that the diameter of the vias is of the order of 50 micrometers. 13. Circuit according to any one of claims 11 and 12, characterized in that the substrate is formed in part of alumina. 14. Circuit according to any one of claims 11 to 13, characterized in that the conductive levels are formed from a paste containing gold, copper or silver. 15. Circuit according to any one of claims 11 to 14, characterized in that the dielectric layers are formed from a photosensitive dielectric paste. 16. Circuit according to any one of claims 1 to 15, characterized in that the total thickness of the assembly consisting of the first and second dielectric layers (Di1 and D12) is of the order of 40 micrometers.