FR2681991A1 - DIFFERENTIAL RECEIVER, DIFFERENTIAL AMPLIFIER AND METHOD FOR RECEIVING DIFFERENTIAL POWER SUPPLY VOLTAGES IN THE DIFFERENTIAL RECEIVER. - Google Patents

Abstract

The invention relates to a differential receiver comprising first and second transistors (Q1, Q2) connected in parallel to a data input; third and fourth transistors (Q3, Q4) connected in parallel to a reference voltage input line; a fifth transistor (Q5) which connects the first, second, third and fourth transistors to earth; a sixth transistor (Q6) which connects the first transistor to a voltage supply; and seventh and eighth transistors (Q7, Q8) for connecting the first and second transistors to a data output. The invention also relates to a differential amplifier and a method for receiving different voltages in the differential receiver.

Description

Differential receiver, differential amplifier and method for

  The present invention relates to a method for constructing a circuit normally operating at a voltage of less than 5 volts but capable of tolerating a supply voltage of 5 volts It also relates to a differential receiver that can tolerate an input logic signal from a device powered by a supply voltage of 5 volts, and a CMOS differential amplifier capable of connecting a logic circuit having voltage levels of up to 5 volts to a logic circuit powered by a lower voltage, equal to 3.3 volts, for example For all practical purposes, it is specified that CMOS is formed of the initials of Complementary Metal Oxide

  Semiconductor, an expression for metal transistors

  complementary semiconductor oxide.

  As the CMOS devices have become progressively smaller, the supply voltages have been correspondingly reduced, in order to mitigate the detrimental effects of voltage differences on increasingly smaller line sections. However, this decrease from nominal voltage of 5 volts to 3.3 volts did not occur at all manufacturers at the same time. It did not occur in all semiconductor devices with which

  other semiconductor devices must communicate.

  Thus, a VLSI chip designed to operate at a voltage of 3.3 volts may require an interface with another chip that operates at a voltage of 5 volts It is stated that VLSI is formed of the initials of Very Large Scale Integrated

  which means very high density of integration.

  Achieving the correct interface requires special circuit or device techniques to avoid imposing constraints on components designed to operate at a voltage of 3.3 volts. to perform additional manufacturing steps necessary to fabricate devices that can tolerate higher voltages Design variations may also involve the occupation of a larger chip area by buffer circuits. A typical CMOS receiver stage is simply a capacity ratio inverter, designed to operate with prescribed voltage levels (typically TTL, ie multi-transmitter transistor logic: maximum voltage level for logic O (V m) equal to 0.8 volt, minimum voltage level for logic 1 (V 11 in) equal to 2 volts) A typical CMOS receiver of this type is shown in Figure 1 However, the maximum input voltage in a standard system is likely to match the 5-volt supply If a voltage of volts is applied to the receiver stage of Figure 1, a

  transistor Q 2 will have gate-source and grid-gate voltages

  drain equal to 5 volts In the case of devices designed to operate normally at a voltage of 3.3 volts, the application of a voltage of 5 volts between the terminals of these junctions can cause an immediate destruction of the transistor. There is therefore a need for a CMOS receiver stage that can operate normally with a supply voltage of 3.3 volts, while being able to tolerate

  a supply voltage of 5 volts.

  For this purpose, the present invention proposes, according to one of its aspects, two complementary input transistors limiting the maximum voltage difference between the terminals of the transistor that receives the data input signal. The invention also proposes a group transistors that accelerate a transient behavior while protecting the input stages of the receiver It also offers two corresponding transistors to receive a reference voltage and to balance the

charge of the current in the circuit.

  According to another aspect, the invention allows the connection of logic devices with voltages

disparate feeding.

  The foregoing as well as other objects, advantages and features of the present invention will become more apparent.

  clearly from the following detailed description of a mode of

  preferred embodiment thereof, given by way of non-limiting example with reference to the accompanying drawings in which: Figure 1 shows a receiver stage of the prior art; Figure 2 shows a voltage tolerant CMOS receiver stage according to the present invention; and Figure 3 shows a preferred embodiment of the voltage tolerant CMOS receiver stage,

according to the invention.

  Referring to Figure 2 which shows a receiver stage having five transistors Q 1, Q 2, Q 3, Q 4 and Q 5, it can be seen that in this configuration the logic input signal is applied to a transistor Q 3, while a reference voltage V REF (approximately 11V, + Vmin1 / 21 or about 1.4 volts for TTL) is applied to a transistor Q 4. For a device powered by a voltage of 3.3 volts, the reference voltage is nominally from 1.6 to 1.7 volts For an ECL (transmitter-coupled logic) device, V REF is equal to about -0.9 volts All transistors shown in FIGS. 1, 2 and 3 are enrichment mode field effect devices This circuit has the advantage that the voltage at a node 3 will tend to follow the higher of the input voltage V IN and the reference voltage. V REF, to thus limit the voltage differences across Q 3 However, it has been found that n transistor Q1 limits the maximum high level on a node 1 and on the node 3 to (3.3 v Vtp (the threshold voltage of a PMOS device, namely a P-channel MOS device)) of a more importantly, Qi limits transient behavior such that node 1 and node 3 are out of phase with V IN, which has the effect of causing excessive voltages during the input transient. logic O to logic 1. A transistor Q 5 simply plays the role of a

  automatic polarization current receiver.

  The receiver stage shown in FIG. 3 solves this problem by including transistors Q 6, Q 7 and Q 8 V IN feeds the parallel combination of Q 3 and Q 6 Q 6 provides a current source for charging node 3 during the high voltage transition from logic O to logic 1 to V IN The gate width of Q 6 is small compared to the gate width of Q 3 and preferably equal to about 10% of the width of Q 3 La gate Q 6 is just large enough to load node 3 fast enough to follow an input ramp This action avoids excessive voltage differences across Q 3, especially when the logic device providing V IN operates at a higher voltage at 3.3 volts, such as a voltage of 5 volts for example The drain of Q 6 is directly connected to the supply of 3.3 volts and goes quickly, during a transition from logic O to logic 1, bring

  node 3 at a voltage of 3.3 volts.

  Node 1 can be loaded via Q 3 and is not limited by QI Transistor Q 7 compensates for the effect of Q 6 In other words, ignoring for a moment the effects of Q 6 and Q 7, Q 3 and Q 4 normally act as a differential amplifier When V IN and V REF are high, Q 3 and Q 4 draw the same current Now, Q 6 being in place, Q 7 must balance the current loads in the amplifier Adding Q 6 and Q 7 has a negligible effect on the characteristics of the amplifier in the normal operating area (V IN 3.3 v) However, when V IN> 3.3 v, the higher voltage applied on the node 3 causes higher voltages on the node 1, from which an inappropriate polarization effect on Q 2, except for the effect of Q 8 Normally, when V IN> V REF, Q 4 is switched off and Q 2 increases the output In this case, Q 4 is made nonconductive as appropriate, but Q 2 also

  tendency to switch off The transistor Q 8 counter

  If V IN is low (<0.8 v), Q 8 does not prevent the output from going down When V IN is high (> 2 v), Q 8 strengthens Q 2, and when V IN is very high (> 3.3 v), Q 8 provides all of the excitation at the output node. This means that, when V IN> 3, 3, the receiver can be considered operating outside its normal operating band, and in this case Q 8 takes precedence over the action of the differential amplifier In this case, Q 8 connects the 3.3 volts supply to node 2 and by

  consequently at the output voltage V OUT.

  Although the previous description focused on a

  preferred embodiment of the present invention, it is understood that it is not limited to the particular example described and illustrated here, and one skilled in the art will readily understand that it is possible to make it many changes and variants without leaving the

framework of the invention.

Claims (5)

  A differential receiver characterized in that it comprises first and second transistors (Q 1, Q 2) connected in parallel to a data input; third and fourth transistors (Q 3, Q 4) connected in parallel with a reference voltage input line; a fifth transistor (Q 5) which connects the first, second, third and fourth transistors to earth; a sixth transistor (Q 6) which connects the first transistor to a voltage supply; and seventh and eighth transistors (Q 7, Q 8) for connecting the first   and second transistors at a data output.   Differential receiver according to Claim 1, characterized in that the transistors are field effect.   Differential receiver according to Claim 1, characterized in that the sixth and seventh transistors (Q 6, Q 7) are P-channel field effect transistors, while the other transistors are N-channel field effect transistors. Differential receiver according to claim 2, characterized in that the gate width of the second transistor (Q 2) is small compared to the gate width. of the first transistor (Ql).   Method for receiving any of the different power supply voltages in a differential receiver, characterized in that it comprises the steps of receiving an input logic signal in two first and second transistors (Q 1, Q 2) parallel; receiving a reference voltage (V REF) in two third and fourth parallel transistors (Q 3, Q 4); connecting the first, second, third and fourth transistors to the earth via a fifth transistor (Q 5); connecting the first transistor to a bias voltage supply with a sixth transistor (Q 6); and connecting the first and second transistors to a data output using seventh and eighth transistors (Q 7, Q 8). 6 differential amplifier characterized in that it comprises a bias current supply; a reference voltage source; a first transistor (Qi) adapted to be connected to an input logic signal; a second transistor (Q 2) connected in parallel with the first transistor, the drain of the second transistor being connected to the bias current supply; a third transistor (Q 3) connected in parallel with the first transistor, the drain of the third transistor being connected to the bias current supply, while the source of the third transistor is connected to an output node; a fourth transistor (Q 4) which connects the drain of the first transistor to the bias current supply; a fifth transistor (Q 5) connected to the reference voltage source, the drain of the fifth transistor being connected to the output node; a sixth transistor (Q 6) connected in parallel with the fifth transistor, the drain of the sixth transistor being connected to the bias current supply; a seventh transistor (Q 7) which connects the sources of the first, second, fifth and sixth transistors to earth; and an eighth transistor (Q 8) connected, at its gate, to the drain of the first transistor, at its drain, to the bias current supply and, at   level of its source, at the output node.   Differential amplifier according to claim 6, characterized in that the fourth and eighth transistors (Q 4, Q 8) are P-channel field effect transistors, while the other transistors are N-channel field effect transistors. Differential receiver according to claim 6, characterized in that the gate width of the second transistor (Q 2) is small compared to the gate width. of the first transistor (Q 1).   9 differential receiver according to claim 6, characterized in that the gate width of the sixth transistor (Q 6) is small compared to the gate width of the fifth transistor (Q 5).