FR2680891B1 - Interruptions transparentes pour le systeme avec adressage de la memoire etendue integree. - Google Patents

Interruptions transparentes pour le systeme avec adressage de la memoire etendue integree.

Info

Publication number
FR2680891B1
FR2680891B1 FR9210352A FR9210352A FR2680891B1 FR 2680891 B1 FR2680891 B1 FR 2680891B1 FR 9210352 A FR9210352 A FR 9210352A FR 9210352 A FR9210352 A FR 9210352A FR 2680891 B1 FR2680891 B1 FR 2680891B1
Authority
FR
France
Prior art keywords
interruptions
transparent
extended memory
memory addressing
integrated extended
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9210352A
Other languages
English (en)
Other versions
FR2680891A1 (fr
Inventor
James Kardach
Cau Nguyen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of FR2680891A1 publication Critical patent/FR2680891A1/fr
Application granted granted Critical
Publication of FR2680891B1 publication Critical patent/FR2680891B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Storage Device Security (AREA)
FR9210352A 1991-08-30 1992-08-28 Interruptions transparentes pour le systeme avec adressage de la memoire etendue integree. Expired - Fee Related FR2680891B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/753,605 US5274834A (en) 1991-08-30 1991-08-30 Transparent system interrupts with integrated extended memory addressing

Publications (2)

Publication Number Publication Date
FR2680891A1 FR2680891A1 (fr) 1993-03-05
FR2680891B1 true FR2680891B1 (fr) 1997-06-20

Family

ID=25031379

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9210352A Expired - Fee Related FR2680891B1 (fr) 1991-08-30 1992-08-28 Interruptions transparentes pour le systeme avec adressage de la memoire etendue integree.

Country Status (6)

Country Link
US (1) US5274834A (fr)
JP (1) JPH05250183A (fr)
DE (1) DE4228756C2 (fr)
FR (1) FR2680891B1 (fr)
GB (1) GB2259164B (fr)
HK (1) HK165095A (fr)

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JPH06230979A (ja) * 1992-06-17 1994-08-19 Cyrix Corp 改良されたシステム管理方法および装置
JPH06139031A (ja) * 1992-10-27 1994-05-20 Ricoh Co Ltd プリンタコントローラ
JP3135094B2 (ja) * 1993-03-13 2001-02-13 株式会社リコー 統合ビジネス用ネットワークシステム
US5509139A (en) * 1993-03-22 1996-04-16 Compaq Computer Corp. Circuit for disabling an address masking control signal using OR gate when a microprocessor is in a system management mode
US5590297A (en) * 1994-01-04 1996-12-31 Intel Corporation Address generation unit with segmented addresses in a mircroprocessor
US5564030A (en) * 1994-02-08 1996-10-08 Meridian Semiconductor, Inc. Circuit and method for detecting segment limit errors for code fetches
US5577219A (en) * 1994-05-02 1996-11-19 Intel Corporation Method and apparatus for preforming memory segment limit violation checks
US5970237A (en) * 1994-06-14 1999-10-19 Intel Corporation Device to assist software emulation of hardware functions
US5583806A (en) * 1994-10-17 1996-12-10 Advanced Micro Devices, Inc. Optimized binary adder for concurrently generating effective and intermediate addresses
US5638532A (en) * 1994-12-06 1997-06-10 Digital Equipment Corporation Apparatus and method for accessing SMRAM in a computer based upon a processor employing system management mode
US5680578A (en) * 1995-06-07 1997-10-21 Advanced Micro Devices, Inc. Microprocessor using an instruction field to specify expanded functionality and a computer system employing same
US5768574A (en) * 1995-06-07 1998-06-16 Advanced Micro Devices, Inc. Microprocessor using an instruction field to expand the condition flags and a computer system employing the microprocessor
US5822778A (en) * 1995-06-07 1998-10-13 Advanced Micro Devices, Inc. Microprocessor and method of using a segment override prefix instruction field to expand the register file
US5857116A (en) * 1995-10-27 1999-01-05 Compaq Computer Corporation Circuit for disabling an address masking control signal when a microprocessor is in a system management mode
US5819080A (en) * 1996-01-02 1998-10-06 Advanced Micro Devices, Inc. Microprocessor using an instruction field to specify condition flags for use with branch instructions and a computer system employing the microprocessor
US5787492A (en) * 1996-04-09 1998-07-28 International Business Machines Corporation Address limit check apparatus with conditional carry logic
US5909582A (en) * 1996-04-26 1999-06-01 Nec Corporation Microcomputer having user mode interrupt function and supervisor mode interrupt function
US6742080B1 (en) 1996-09-06 2004-05-25 Intel Corporation Disk block allocation optimization methodology and application
US5802593A (en) * 1996-09-06 1998-09-01 Intel Corporation Method and apparatus for improving disk drive performance
US5983310A (en) 1997-02-13 1999-11-09 Novell, Inc. Pin management of accelerator for interpretive environments
US5978882A (en) * 1997-04-25 1999-11-02 Novell, Inc. Real-mode, 32-bit, flat-model execution apparatus and method
US5987604A (en) * 1997-10-07 1999-11-16 Phoenix Technologies, Ltd. Method and apparatus for providing execution of system management mode services in virtual mode
US6230259B1 (en) 1997-10-31 2001-05-08 Advanced Micro Devices, Inc. Transparent extended state save
US6157996A (en) * 1997-11-13 2000-12-05 Advanced Micro Devices, Inc. Processor programably configurable to execute enhanced variable byte length instructions including predicated execution, three operand addressing, and increased register space
US6578193B1 (en) 1998-03-24 2003-06-10 Novell, Inc. Endian-neutral loader for interpretive environment
US6141732A (en) * 1998-03-24 2000-10-31 Novell, Inc. Burst-loading of instructions into processor cache by execution of linked jump instructions embedded in cache line size blocks
US6356996B1 (en) 1998-03-24 2002-03-12 Novell, Inc. Cache fencing for interpretive environments
US6192455B1 (en) * 1998-03-30 2001-02-20 Intel Corporation Apparatus and method for preventing access to SMRAM space through AGP addressing
US6157981A (en) * 1998-05-27 2000-12-05 International Business Machines Corporation Real time invariant behavior cache
US6240482B1 (en) * 1998-06-02 2001-05-29 Adaptec, Inc. Host adapter having a plurality of register sets and corresponding operating nodes
US6263412B1 (en) 1998-06-24 2001-07-17 Phoenix Technologies Ltd. Method and apparatus for RAM emulation using a processor register set
US7099898B1 (en) * 1999-08-12 2006-08-29 International Business Machines Corporation Data access system
EP1122643A1 (fr) * 2000-02-07 2001-08-08 Siemens Aktiengesellschaft Circuit et procédé pour le traitement des interruptions
US6760441B1 (en) * 2000-03-31 2004-07-06 Intel Corporation Generating a key hieararchy for use in an isolated execution environment
US6601122B1 (en) * 2000-04-17 2003-07-29 International Business Machines Corporation Exceptions and interrupts with dynamic priority and vector routing
US6981132B2 (en) 2000-08-09 2005-12-27 Advanced Micro Devices, Inc. Uniform register addressing using prefix byte
US6877084B1 (en) 2000-08-09 2005-04-05 Advanced Micro Devices, Inc. Central processing unit (CPU) accessing an extended register set in an extended register mode
US6694401B2 (en) * 2001-12-28 2004-02-17 Intel Corporation Method and apparatus for executing real-mode interrupts from within extended SMRAM handler
US10503523B2 (en) * 2017-06-30 2019-12-10 Intel Corporation Technologies to improve system boot performance and reliability

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US3577185A (en) * 1969-10-02 1971-05-04 Ibm On-line system for measuring the efficiency of replacement algorithms
CH625931B (de) * 1979-01-09 1900-01-01 Breveteam Sa Textiles flaechengebilde und dessen verwendung.
JPS599937B2 (ja) * 1980-02-20 1984-03-06 富士通株式会社 情報処理装置
US4434462A (en) * 1980-11-24 1984-02-28 Texas Instruments Incorporated Off-chip access for psuedo-microprogramming in microprocessor
US4519032A (en) * 1982-06-09 1985-05-21 At&T Bell Laboratories Memory management arrangement for microprocessor systems
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Also Published As

Publication number Publication date
DE4228756A1 (de) 1993-03-04
GB2259164B (en) 1995-01-18
GB2259164A (en) 1993-03-03
HK165095A (en) 1995-11-03
FR2680891A1 (fr) 1993-03-05
DE4228756C2 (de) 1996-10-24
US5274834A (en) 1993-12-28
JPH05250183A (ja) 1993-09-28
GB9216240D0 (en) 1992-09-09

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Legal Events

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