FR2677201A1 - Control configuration for a buffer memory of a time-based switch - Google Patents

Abstract

Control arrangement for a buffer memory (4) of a time-based switch (1) intended for switching incoming link channels and outgoing link channels, the respective numbers of which differ. The configuration, equipped with a microcontroller (8) associated with a time base (5) which is placed under the control of an external clock system governing the various time-based frames in force on the links (2, 3) which are connected to the switch, includes a memory (6) for control in writing, or in reading, of the type with addressing by its contents. This memory compares the channel address information which it holds with each of the channel address information items in the greater number which are successively transmitted to it in totality in the course of each time frame.

Description

Time switch buffer control arrangement
The invention relates to a control arrangement for a time switch buffer memory serving incoming and outgoing channels whose respective numbers differ.

The buffer of a time switch is conventionally organized to ensure the same determined number of successive switches between a certain number of incoming time channels and a certain number of outgoing time channels during successive frames which, of the same duration, are subdivided into as many equal time intervals each, and at the usual rate of switching between an incoming and an outgoing channel per frame time interval.

For this purpose, the buffer memory of a switch has a number of separate memory locations at least equal to the number "n" of switches to be made in each frame.

Each location is designed to temporarily store a word from an incoming channel.

The writing of words, coming from inbound channels, in the buffer memory is carried out at individually addressable locations of the buffer memory, at the usual rhythm of at most one word originating from a channel per frame time interval, the memory therefore comprising "n" different location addresses.

When the number of incoming channels capable of accessing a buffer memory in a given time switch is equal to the number of outgoing channels accessible from this memory, it is conventional to write the buffer memory using a counter providing a different location address for each of the time intervals of a frame, this address remaining identical for the intervals of the same rank during successive frames.

A read control memory is then associated with the buffer memory, it is read at the same rate as the latter so as to address one of the buffer memory locations at each time interval and consequently to cause the transmission of the word contained at this location on one of the outgoing time channels. This read control memory must then normally also have at least "n" individual locations for storing addresses of locations in buffer memory.

In known manner, the write and read addresses of a buffer memory can also be obtained by inverting the device described above, a control memory being provided for write addressing and a counter for read addressing.

It is also known to have two memories, one for write addressing of the buffer memory and the other for read addressing, in particular when the actual number "m" of channels capable of being served as input. or at the buffer output differs from the number of channels actually switched, a concentration or deconcentration being for example provided at the time switch respectively upstream or downstream of the buffer memory.

In these latter cases, one of the control memories must have a number of individual address storage locations normally corresponding to the real number "m" of channels which is the largest, which can be prohibitive when this is the case. number is itself large.

The invention therefore provides a control arrangement for a time switch buffer memory intended for switching incoming link channels and outgoing link channels whose respective numbers differ, provided with a microcontroller associated with a time base placed under the control of an external clock system governing the different time frames in force on the links connected to the switch. This arrangement also has at least one control memory for writing or for reading, in buffer memory, digital information modules to be transmitted from incoming time channels to outgoing time channels.

According to a characteristic of the invention, this arrangement comprises a control memory, of the type for addressing by its content, having a number of locations for the storage of channel address information, corresponding to the number of outgoing channels or which is the lowest, to store the channel addresses, chosen from those in greatest number, which correspond to channels to be switched with channels chosen from those in lowest number. This memory compares the channel address information which it stores with each of the largest number of channel address information which are successively transmitted to it during each time frame.

The invention, its characteristics and its advantages are explained in the following description, in conjunction with the figures listed below.

The single figure shows a diagram of a time switch buffer control arrangement according to the invention.

The time switch 1, presented in FIG. 1, is assumed intended to allow the communication of a given number "m" of unitary time channels, here assumed to be transmitted by an input time multiplex link 2, with a given number " p "of unitary time channels assumed to be transmitted by an output time multiplex link 3, within the framework of a time network.

Each unitary time channel has a time interval during each of the successive frames on the multiplex link 2 or 3 which supports it. This time interval usually keeps the same rank during successive frames for the same channel and allows the transmission of a digital information module, which is for example in the form of a byte.

The same basic frame duration being conventionally chosen for a given time network, it is however possible to have frames which, for different links, have different structures and for example numbers of time intervals, therefore numbers of channels, by different grid.

In the example considered here, the number "m" of time channels at the time switch input 1, that is to say here on the input link 2, is assumed to be significantly greater than the number "p" of channels at the switch output here on output link 3, "m" being for example equal to 4096 while "p" is equal to 128.

The number "n" of switches that the time switch 1 must be able to perform between incoming and outgoing time channels in each frame therefore implies that it has a switching buffer memory, here referenced 4, comprising at least one number "n "of separate memory locations each intended for the temporary storage of at least one digital information module, such as for example a byte.

The number "n" should preferably be at least equal to the smaller of the two numbers "m" and "p", that is to say "p" in the example proposed.

For reasons of saving space and cost, it is generally sought to reduce to the minimum the number of memory locations and their size to what is strictly necessary for a given switch.

The assignment of a buffer storage location for writing to an incoming time channel can possibly be done by fixed cyclic addressing, when the number "m" of incoming channels is at most equal to the number of possible switching operations per frame, the addressing can then be achieved by means of a counter of a time base 5, receiving signals from a clock system of the time network, via a link referenced H, as is known.

In other cases and in particular in the envisaged embodiment where the number "m" of incoming channels is large, a control memory 6 is provided which makes it possible to assign each of the "n" locations in buffer memory 4 to one of " n "of" p "incoming channels according to present needs.

This control memory 6 is conventionally read at the same rate as the buffer memory 4 under the control of the time base 5 to which it is connected by a clock link referenced "C1".

The addressing in reading of the buffer memory 2 is also capable of being carried out cyclically at the rate provided for the buffer memory 4, under the action of a counter, for example assumed to be included in the time base 5, which provides the sequence of buffer memory location addresses to be read, in particular if a write control memory 6 is associated with the buffer memory 4, in the control arrangement of the latter.

In the example envisaged, the addressing in reading of the buffer memory 2 is provided to be carried out under the control of a control memory 7 comprising at least "p" individual address locations of buffer memory location.

The control memory 7 here comprises a number "p" of locations equal to the number "n" of locations in buffer memory 4, each location is capable of receiving digital information of outgoing channel address in buffer memory provided either by a microcontroller 8 of a marker of the time switch 1, either by a counter not shown of this marker, via a link 9 and as required.

Each digital address information conventionally corresponds to the rank number of the time interval of the channel in the frame at the output of buffer memory 4.

The reading of this address information takes place at the same rate as that of the buffer memory 4, under the control of the time base 5 which cyclically supplies the sequence of addresses to be read in the control memory 7, for example by via a counter not shown and via a link 10, as well as control signals, via the clock link "C1".

A decoder it successively receives the addresses supplied by the control memory 7 and deduces from each a command to read the location in the buffer memory 4, via individual write command links such as rO, rl ... rn.

In the proposed embodiment, the control memory 6 for writing the buffer memory consists of a memory of the type addressed by its content.

This control memory 6 therefore comprises a memory unit, proper, 12 associated with a plurality of comparators 13.

The memory unit 6 comprises a number of storage locations which is chosen equal to the number of channels capable of being successively switched by the buffer memory 2 during a frame, that is to say to the number "n "considered above, this number here being equal to the number" p "of outgoing channels and much less than the number" m "of incoming channels of the switch in question.

Each storage location in memory unit 6 is capable of receiving digital information for the address of the incoming channel which, in the example proposed, is supplied to it by the microcontroller 8, via the link 9, as required.

Each digital address information corresponds to the rank number of a channel time interval in the frame in force on the input link 2, in the example chosen.

The memory unit 12 also receives from the time base 5, via the clock link "C1", the time control signals which it needs.

Each storage location is connected to an input of a comparator 13 which is specific to it and a second input of which is connected to a link 14 to which all the second comparator inputs 13 are connected in parallel. In the example envisaged, each location is dimensioned to store digital information whose dimension is at least equal to that of an incoming time channel address, that is to say at least twelve bits for 4096 channels.

The link 14 successively transmits the "m" digital address information of incoming channels to each frame, this information being supplied to it by the time base 5, via a counter not shown.

Each comparator 13 compares the content of the location of the memory element 12 to which it is connected with each of the address information successively transmitted by the link 14 so as to produce a write command in a determined buffer memory location 4, via an individual write command link, such as wO, wl, ... .won.

The time switch 1 presented therefore makes it possible to switch, during a frame, a number "n" of digital information modules chosen from among the "p" modules appearing successively on the input link 2 during the duration of this frame, in order to selectively transmit them via the output link 3.

The microcontroller 8 inscribes in the locations of the memory unit 6, the digital information corresponding to the time intervals of the incoming time channels whose digital information modules are to be switched via the buffer memory 4, so as to trigger the writing of the modules appearing at each frame on the input link 2 in the respective locations reserved for them in this buffer memory, when the indicated time interval number transmitted by the link 14 corresponds to at least the one of the digital address information recorded in the memory unit 12.

 It is therefore possible to transmit the same module by several time channels of the output link 3 by writing the same digital address information in several locations of the memory unit 12, so that several comparators are able to simultaneously recognize the channel time interval at the input of this module and entail the simultaneous recording of this module in as many storage locations in buffer memory 4 each corresponding to a different interval of frame channel time on the output link 3 .

 It is also possible to use a memory addressable by its content, as mentioned above, as a control memory for reading a switching buffer memory of a time switch, if necessary, the organization write and read control memories, as defined above, then being for example inverted.

Claims (3)

1 / Control arrangement for buffer memory (4) of time switch (1) intended for switching incoming link channels and outgoing link channels whose respective numbers differ, provided with a microcontroller (8) associated with a base time (5), placed under the control of an external clock system governing the different time frames in force on the links (2, 3) connected to the switch and at least one control memory (6 or 7) for writing or for reading in the buffer memory the digital information modules to be transmitted from the incoming time channels to the outgoing time channels, characterized in that it includes a control memory (6), of the type for addressing by its content , with a number of channel address information storage locations, corresponding to the lowest number of incoming or outgoing channels, for storing the channel addresses, chosen from among those in greatest number s large, which correspond to channels to be switched with channels chosen from those in smallest number and in that this memory compares the channel address information which it stores with each of the channel address information in number the largest which are successively transmitted to it in full during each time frame. 2 / control arrangement according to claim 1, for buffer memory (4) of time switch (1), characterized in that it comprises a control memory (6) of the type addressed by the content which comprises a number of storage locations equal to the number of time channels switched as output by the switch buffer, said memory being written by the microcontroller (8) supervising the switch and being read from the digital address information of incoming channels supplied by the associated time base (5). 3 / control arrangement according to claim 1, for buffer memory (4) of time switch (1), characterized in that it comprises a control memory (6) of the type addressed by the content which comprises a number of storage locations equal to the number of time channels switched as output by the switch's buffer memory, each location being dimensioned to store digital information whose dimension is at least equal to that of a time channel address for a channel chosen from those whose number is the greatest.