FR2671417B1 - Procede pour la fabrication d'une carte a memoire et carte a memoire ainsi obtenue . - Google Patents
Procede pour la fabrication d'une carte a memoire et carte a memoire ainsi obtenue .Info
- Publication number
- FR2671417B1 FR2671417B1 FR9100067A FR9100067A FR2671417B1 FR 2671417 B1 FR2671417 B1 FR 2671417B1 FR 9100067 A FR9100067 A FR 9100067A FR 9100067 A FR9100067 A FR 9100067A FR 2671417 B1 FR2671417 B1 FR 2671417B1
- Authority
- FR
- France
- Prior art keywords
- memory card
- manufacture
- card
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Theoretical Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Credit Cards Or The Like (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9100067A FR2671417B1 (fr) | 1991-01-04 | 1991-01-04 | Procede pour la fabrication d'une carte a memoire et carte a memoire ainsi obtenue . |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR9100067A FR2671417B1 (fr) | 1991-01-04 | 1991-01-04 | Procede pour la fabrication d'une carte a memoire et carte a memoire ainsi obtenue . |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2671417A1 FR2671417A1 (fr) | 1992-07-10 |
FR2671417B1 true FR2671417B1 (fr) | 1995-03-24 |
Family
ID=9408454
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9100067A Expired - Fee Related FR2671417B1 (fr) | 1991-01-04 | 1991-01-04 | Procede pour la fabrication d'une carte a memoire et carte a memoire ainsi obtenue . |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2671417B1 (fr) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5689136A (en) * | 1993-08-04 | 1997-11-18 | Hitachi, Ltd. | Semiconductor device and fabrication method |
FR2735284B1 (fr) * | 1995-06-12 | 1997-08-29 | Solaic Sa | Puce pour carte electronique revetue d'une couche de matiere isolante et carte electronique comportant une telle puce |
FR2750250B1 (fr) * | 1996-06-20 | 1998-08-21 | Solaic Sa | Procede de protection d'une galette de circuits integres, et galette de circuits integres obtenue |
FR2754619B1 (fr) * | 1996-10-14 | 1998-12-11 | Solaic Sa | Circuit integre ayant une face active recouverte d'une couche isolante et carte a circuit integre le comportant |
DE19642563C1 (de) * | 1996-10-15 | 1998-02-26 | Siemens Ag | Chipkarte mit einer Kontaktzone sowie Verfahren zur Herstellung einer solchen Chipkarte |
FR2756975B1 (fr) * | 1996-12-05 | 1999-05-07 | Solaic Sa | Circuit integre ayant une face active recouverte d'une couche isolante et carte a circuit integre le comportant |
FI990862A (fi) * | 1999-04-16 | 2000-10-17 | Jorma Kalevi Kivilahti | Uusi elektroniikan juotteeton valmistusmenetelmä |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2581480A1 (fr) * | 1985-04-10 | 1986-11-07 | Ebauches Electroniques Sa | Unite electronique notamment pour carte a microcircuits et carte comprenant une telle unite |
FR2584236B1 (fr) * | 1985-06-26 | 1988-04-29 | Bull Sa | Procede de montage d'un circuit integre sur un support, dispositif en resultant et son application a une carte a microcircuits electroniques |
JPS6314455A (ja) * | 1986-07-07 | 1988-01-21 | Hitachi Maxell Ltd | 半導体装置 |
JPH01256161A (ja) * | 1988-04-05 | 1989-10-12 | Toshiba Corp | 印刷配線板装置 |
FR2631200B1 (fr) * | 1988-05-09 | 1991-02-08 | Bull Cp8 | Circuit imprime souple, notamment pour carte a microcircuits electroniques, et carte incorporant un tel circuit |
-
1991
- 1991-01-04 FR FR9100067A patent/FR2671417B1/fr not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
FR2671417A1 (fr) | 1992-07-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |
Effective date: 20091030 |