FR2669447A1 - METHOD AND APPARATUS FOR TRANSFERRING DATA IN A SINGLE INSTRUCTION. - Google Patents

Abstract

A method and apparatus for transferring single instruction data is provided. The apparatus (103) responds to a read instruction from a processor (105) and transfers data from a peripheral device contained in a receiver (101) to a memory contained in the processor (105). As soon as the peripheral device is selected, the apparatus couples the latter to the memory via the data bus (113). Following the coupling, the device creates a write signal in memory causing the validation of a write function and de-energizes a read signal, which causes the invalidation of the read function.

Description

The present invention relates generally to a method and an apparatus

  data transfer in a single instruction, and it relates more particularly to the reception of data, coming from a peripheral device, in the

external memory of a processor.

  The techniques traditionally used for data transfer employ either the continuous use of the

  processor for the duration of the transfer, or a provision

  external control device which is specially assigned to the trans-

  fert These usual ways of doing things are well known in general and are widely used in conceptual fields using the computer. The programmed means which use

  processors are inexpensive and cost effective from the point of view

  short, but, however, they are not suitable for calculation Each transfer cycle requires at least two instruction cycles, and the processor is not able to perform any other calculation

  Throughout the duration of the data transfer An example of use

  use of a programmed means to solve the problem of trans-

  fert data from a peripheral device in a memory can be found in "Microprocessors and Microcomputers, Hardware

  and Software ", by Tocci and Laskowski, at page 224 The provisions

  specialized control devices do not use the processor during the entire transfer operation, but these control devices must obtain control of the data bus to transfer the data The process by which control of the data bus is obtained on the part of the processor requires that the control device sends a request for use of the bus and receives from the processor a transfer of use of the bus; this adds an unknown delay to the number, at least equal to two, of instruction cycles for each transfer of use of the bus. In addition, the control device will use the data bus during all or part of the data transfer, which limit the amount of data that the processor can transfer between itself and memory An example of the use of a specialized controller to solve the problem of transferring data from a peripheral device to a memory can be found in the following application note, by Thomas Hardy, "A transparent DMA using a MC 6809 E MPU and a MC 6844 DMAC", (1984) The use of traditional techniques keeps the designer with one of the following problems, namely an inefficient use of the computing power of the processor, or else a data bus which is not always available for the processor, which limits the

  amount of computation that can be performed by the processor during

for a while.

  While the above examples are good

  adapted to their applications, there is nevertheless the need for a pro-

  inexpensive, space-saving transfer cessation, which uses only one instruction cycle from the processor to load data from a peripheral device into the external memory of the processor and leaves the use of the data bus available of

processor.

  The invention provides a device for transferring data in a single instruction, which, in response to a single triggering event originating from a control device, transfers data

  data from an output device to an input device.

  The device, in response to the single trigger event, produced at

  minus a signal which selects the input device and the

  positive output Once the output device has been selected, the device L couples the output device to input device A

  Following the coupling of the output and input devices, the device

  reil creates, for the input device, at least one

  signal which causes the validation of a write function.

  The following description, intended for illustration

  of the invention, aims to give a better understanding of its characteristics and advantages; it is based on the appended drawings, among which: FIG. 1 is the block diagram of a radiofrequency data transmission system; Figures 2 and 3 together constitute the block diagram of a receiver that can use a data transfer device in a single instruction; Figure 4 is a memory layout map for the memory shown in Figure 2; and

  Figure 5 is a flowchart of the operations performed

  killed by the controller for data transfer from the analog to digital converter of phase signals (209) to

memory (303).

  A radio frequency transmission system, which transmits

  carries a data signal from a transmitter 107 to a receiver 101 is shown in Figure 1 In a radiotelephone system, the transmitter 107 would be the transmitter of a fixed station serving a radio coverage area containing mobile transceivers or portable, of which a receiver, namely the receiver 101, is

  shown in Figure 1 This radio receiver contains a process

  sor 105 which performs calculations on the data received by the radio receiver The data which is received by the radio receiver must be transferred to the processor 105 for the calculations to be carried out The transfer of the data in phase (I) and of the data in quadrature ( Q), from receiver 101 to processor 105, is

  produced by the control block 103.

  FIG. 2 represents the block diagram of the radio receiver 101 The receiver 101 obtains radio frequency (RF) signals from the fixed transceiver 107 As soon as the signals are received, the receiver 101 filters, in a filter 221, the signals and mixing, in a mixer 219, the RF signals with the signal from a local oscillator (LO) 223 After passing through an additional filter 217, the resulting signals are intermediate frequency (IF) signals A mixer 201 adds the signals of a local oscillator 225 to the IF signals and a mixer 203 subtracts from the IF signals the signal of the local oscillator 225, which produces baseband signals (BB) The BB signals then pass through low-pass filters 205 and 207 to form

  signals in phase (I) and signals in quadra-

  ture (Q) The signals I are the result of the direct mixing of the signal of the local oscillator 225 with the signals IF, while the signals Q are the result of the phase shift (90) of the signal of the local oscillator 225 and the mixture of the phase shifted signal with the IF signals The baseband signals I and Q are respectively applied as input to two analog-digital converters

  (ADC) 209 and 211, in which they are sampled at inter-

  regular intervals by the sampling clock signal, the resulting signals obtained being stored in buffers 213 and 215 After sampling, the data I and Q are primed in order to be transferred to the place of digital processing, o calculations will be performed on the data The processor 105 can access the data contained in the buffers 213 and 215, via the data bus 113 If the processor 105 requests data from the analog-digital converters 209 and 211, the control module 103 controls data transfer To make the data available on the data bus 113, you must

  validate the outputs of the three-state buffers 213 and 215.

  The digital processing part of the processor 105 is represented by the block diagram of FIG. 3 It consists of a digital signal processor (DSP, for example the DSP 56001 available from the company Motorola Inc or an analogous DSP) 301 and a memory 303 The digital signal processor 301, the memory 303, the control device 103 and the buffers 213 and 215 of the analog-digital converters are conventionally interconnected by the data bus 113 and the address bus 111 The bus addresses 111 is used by the processor to point to a particular register location in the memory 303 or the analog-digital converters 209 and 211 Specialized control lines, for example the lines RD, WR and

  CS (respectively associated with reading, writing and selecting

  chip), are used to perform functions on the particular register which has been selected by the address bus

  111 The three-state buffers 213 and 215 of the analog converters

  digital-digital are in the form of registers in the memory location maps 401 and 403 of memory 301 of the

  digital signal processor to authorize the process

  sor of digital signals to Read in these buffers as if they were storage locations The available memory of the processor consists of internal random access memory (RAM) and external random access memory and read-only memory (ROM) The addressing of the memory is performs according to the memory location maps of FIG. 4 The digital signal processor 301 is used by the radio receiver to perform equalization calculations on the data received. In the preferred embodiment, the calculations include: (1) automatic frequency control (AFC), (2) correlation, (3) adaptation filtering, (4) power measurements, and (5) automatic gain control (AGC) Data used for calculations are the sampled data

  coming from buffers 213 and 215 of analog-digital converters

  Risk placed in the receiver 101 The data and the results of the calculations are stored in the memory 303 and are extracted from the memory 303 by combined use of the data bus 113, the address bus 111 and the location cards in memory 401 ,

403 and 405.

  The memory location cards used by the digital signal processor 301 are presented in FIG. 4 The addressable storage locations of the digital signal processor 301 are separated into three distinct cards: the memory 401 of data X, the memory 403 of data Y and program memory 405 These memory location cards are all three formed of storage locations internal with respect to the digital signal processor 301 and external with respect to the digital signal processor 301 The numbers preceded by the sign Z along the left side of the memory location cards 401, 403 and 405 are the hexadecimal addresses used by the digital signal processor 301 to refer to specific locations of the memory location cards Data memories X and Y, 401 and 403, and the program memory which are internal to the process eur of digital signals 301 have addresses ranging from 0000 to OOFF and, in memory X, from $ FFCO to $ FFFF All the other addressable storage locations are external to the digital signal processor 301 The external RAMs relating to the memory blocks of data X and Y are addressed between 92000 and $ 2800 The addresses relating to the buffers of the analog-digital converters 213 and 215 are comprised between 94000 and 94800 It is noted that the locations associated with the buffer 213 of the analog-digital converter for the signals I, either I ADC,

  are in memory block X and the associated slots

  listed in buffer 215 of the analog-digital converter for the Q signals, ie Q ADC, are in the memory block Y; this allows the digital signal processor 301 to choose between the I and Q data by toggling the X / Y memory selection line The peripherals "on chip" are addressed in the memory 401 of X data between 9 FFCO and 9 FFFF The results calculations performed by the digital signal processor 301 are stored in the memories 401 and 403 of data X and Y The results of the automatic frequency control calculations (AFC) are written in the data memory Y at 9 FFFO, and the results automatic gain control (AGC) calculations are written in the data memory Y at 9 FFDO and 9 FFEO, respectively for the least significant bits and the most significant bits The external program ROM is addressed between 88000 and SEOOO in the

  405 program memory card.

  We also note that, in FIG. 4, the following indications are presented by way of example The memory 401 of data X has a capacity of 2 K × 24 for its external RAM, and a capacity of 2 K × 24 for its block of memory associated with I ADC The memory 403 of data Y has identical capacities for its external RAM and its b Loc Q ADC, and its address SFFCO is assigned to a

BUG ROM.

  The transfer of data on the data bus is controlled by the controller 103 If the digital signal processor 301 requests a reading in one or the other of the buffers 213 and 215 of the analog-digital converters, the controller modifies the normal reading program of the digital signal processor 301 The reading instruction coming from the digital signal processor 301 is considered as a single triggering event which emanates from a control device As shown in the flowchart of FIG. 5, the transfer process from the control device 103 is triggered in step 501 by a read instruction from the digital signal processor 301 the first test is performed in step 517 in order to check whether the read instruction is intended to one of the two buffers 213 and 215 of the analog to digital converters of the receiver The control device 103 controls The bus addresses by looking for an address between

  94000 and 94800, because i L knows that these are the address locations-

  wise of the buffers 213 and 215 of the analog-digital converters of the receiver If the Read request is made for one of the buffers of the digital converters, bit 14 (A 14) present on the address bus will be high and the bit 13 (A 13) will be low In the case where the reading is intended for one of the buffers 213 and 215 of the logic-digital ana converters, the control device 103 decides, in step 517, in which L aa logic converter -digital i L will read Once this is determined, the controller produces an excitation signal L for the X / Y memory selection line of the digital signal processor if the line is energized in the high state at L ' step 503, the digital signal processor 301 will address the memory 401 in the b Data loc X associated with I ADC, while the low state relates to the b Data loc Y associated with Q ADC in the memory 403 Si e L The is excited in the High state, at Then, in step 505, The device command itif 103 produces a sign L which goes Lid The outputs of the buffer 213 of the logic-digital analog converter of data in phase, which allows the data I to pass on the data bus 113 If the line of selection of memory XIY is in the Low state, a When the control device 103 produces a sign L which goes on The outputs of the buffer 215 of the analog-digital converter of quadrature data, which authorizes the Q data to pass on the data bus 113 to Step 511 The previous validation signal selects the appropriate output device Since the external memory 303 of the digital signal processor consists of several memories of 8 K x 8 bits, only the 11 bis The least significant are necessary to address a any location inside the memories Higher order bits (A 12-A 15) are used by the control device to select between memory or memory chips other peripheral devices found in the memory location cards 401, 403 and 405 Since the lower bits of the address of the external memories and the address of the memories of the Logic-digital converters are identical, the only change necessary for effectively modify the address contained in the location cards in memory 401, 403 and 405 between the analog-digital converters 213 and 215 and the external memory 303 consists in the excitation of the chip selection line (CS) relating to the external memory In step 507, the control device 103 produces signals which de-energize the read line (ARD) and excite the Line CS of the external memory, what is called a read instruction

  altered, or modified, or ARD Then, in step 509, the device

  command tif 103 excites the write line (AWR) of the external memory and the chip selection line (CS) of the external memory, which is called an altered or modified write instruction, namely AWR Si, in step 503, the initial address of the digital signal processor 301 appears outside the window between 94000 and 94800, then an instruction to

  normal reading of digital signal processor 301 is executed

  step 513 This ends the program of the controller 103, in step 511 The controller 103 responds by determining whether the read request from the signal processor

  numeric 301 refers to one of the buffers 213 and 215 of the

  analog-to-digital converter, choosing between buffer 213, associated with the analog-digital converter of data I and buffer 215 associated with the analog-digital converter of data Q, by creating the corresponding write address and

  executing the write instruction.

  The preferred embodiment satisfies the requirements of radiotelephones with regard to the size and cost of the

  control device and processor usage The disposi-

  tif control 103 is implemented in the form of a device "16 L 8 PAL", which is an inexpensive programmable element and of reduced size The transfer process requires only one

  Read instruction from the digital signal processor

  risks 301 to carry out the entire transfer from one of the two buffers 213 and 215 of the analog-digital converters to

  the external memory 303 of the digital signal processor 301.

  This meets, or even exceeds, the requirements listed in the

preamble to the description.

  Of course, the Man of Art will be able to imagine,

  from the device and the method of which the description comes

  to be given for illustrative purposes only and in no way limited-

  tif, various variants and modifications outside the scope of the invention. g

Claims (8)

  1 data transfer apparatus (105) in a single instruction, which, in response to a single triggering event from a control device, transfers data from an output device (209, 211) to a data processing device input (303), characterized by: means which responds to the single triggering event by producing (301) at least one control signal, which selects the input device and the output device;   means (113) for coupling data from the device   tif output to the input device when the output device has been selected; and a means which responds to the single triggering event by creating (103) at least one command sign L coupled to the device   input, which causes the validation of a write function.   2 Apparatus according to claim 1, characterized in that   the input device further comprises an input device exit (303).   3 Apparatus according to claim 2, characterized in that   said control signal (s) which are applied to the device   input sitive further include means for invalidating a read function.   4 Data transfer device in one instruction   tion, employing a digital receiver which provides an L signa   output corresponding to radio signals received and transmitted   transferring data from an output device (303) to an input device (209, 211) in response to a single triggering event, characterized by: means for converting the output signal into digital data (209, 21-1); means which responds to the single triggering event by producing (303) at least one signal, which selects the input device and the output device;   means (113) for coupling data from the device   tif output to the input device when the output device has been selected; and means which responds to the single triggering event by creating (103) at least one control signal coupled to the device   input, which causes the validation of a write function.   Apparatus according to claim 4, characterized in that the input device (303) further comprises an input-output device. 6 Apparatus according to claim 5, characterized in that said one or more control signals which are coupled to the input device further comprises means for invalidating a read function.   7 Data transfer device in one instruction   tion, which, in response to a read instruction from a digital signal processor (301), transfers data to an external memory (303) of the digital signal processor from at least two peripheral devices (209, 211), characterized by: means which responds to the single triggering event by choosing (103) a first peripheral device between the two or more of two peripheral devices; means which responds to the single triggering event by producing (103) an output enable signal which is coupled to said first peripheral device; means which responds to the single triggering event by producing (111) an address which corresponds to a location in the external memory of the digital signal processor; means (113) for coupling said first device   device to the external memory of the digital signal processor   risks when said first peripheral device has been selected   tioned; and means which responds to the single triggering event by creating (103) a read disabling signal and a write enabling signal which are coupled to the external memory of the digital signal processor.   8 Apparatus according to claim 7, characterized in that   the peripheral device (209, 211) further comprises a converter   analog-to-digital weaver using three-state pads on its digital outputs.   9 Apparatus according to claim 8, characterized in that said coupling means (113) further comprises a data bus between said tri-state buffers and the external memory of the digital signal processor.   Method allowing, in response to a single triggering event coming from a control device, to transfer   data from an output device to an input device, character-   terized by the following operations: producing, in response to the single triggering event, at least one signal, which selects the input device and the output signal (503); coupling data from the output device to the input device when the output device has been selected (505); and creating, in response to the single triggering event, a control signal, which is coupled to the input device to   cause validation of a write function (509).   11 Method according to claim 10, characterized in that it further comprises the operation of invalidating a read function (507).