WO1992006566A1 - A single instruction data transfer method and apparatus - Google Patents

A single instruction data transfer method and apparatus Download PDF

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Publication number
WO1992006566A1
WO1992006566A1 PCT/US1991/005877 US9105877W WO9206566A1 WO 1992006566 A1 WO1992006566 A1 WO 1992006566A1 US 9105877 W US9105877 W US 9105877W WO 9206566 A1 WO9206566 A1 WO 9206566A1
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WO
WIPO (PCT)
Prior art keywords
means
device
triggering event
input device
single
Prior art date
Application number
PCT/US1991/005877
Other languages
French (fr)
Inventor
Craig E. Rupp
Original Assignee
Motorola, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US59098690A priority Critical
Priority to US590,986 priority
Application filed by Motorola, Inc. filed Critical Motorola, Inc.
Publication of WO1992006566A1 publication Critical patent/WO1992006566A1/en

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B1/00Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06Receivers
    • H04B1/16Circuits

Abstract

A single instruction data transfer apparatus (103) which responds to a read instruction from a processor (301) is disclosed. The apparatus transfers data from a peripheral device (213, 215) to a memory device (303). Upon selection of the peripheral device (213, 215), the apparatus (103) couples the peripheral device (213, 215) to the memory device (303) via the data bus (113). Following the coupling, the apparatus (103) creates a memory (303) write signal which causes a write function to be enabled and de-asserts read signal which causes the read function to be disabled.

Description

A Single Instruction Data Transfer Method and

Apparatus

Field of the Invention

This invention relates generally to data transfer processing and more specifically to receiving data from a peripheral device into the external memory of a processor.

Background of the Invention

Traditional techniques used for data transfers typically employ either the continuous use of the processor unit for the length of the transfer or an external dedicated controller assigned to the transfer. Such routines are generally known and widely used throughout the computer design environment. Programmed routines which use the processor are inexpensive and size efficient, however, they are computation inefficient. Each transfer cycle takes a minimum of two instruction cycles and the processor is unable to make any other computations during the entire length of the data transfer. An example of using a programmed transfer to solve the problem of transferring data from a peripheral device to memory can be found on page 224 of Microprocessors and Microcomputers, Hardware and Software by Tocci and Laskowski. Dedicated controllers do not utilize the processor for the entire transfer routine, however, the controllers must obtain control of the data bus to transfer data. The process of obtaining control of the data bus from the processor requires the controller to send a bus request and receive a bus grant from the processor; this adds an unknown delay of at least two instruction cycles for each bus grant. Additionally, the controller will employ the data bus for all or part of the data transfer, thus limiting the amount of data the processor can transfer between itself and the memory. An example of using a dedicated controller to solve the problem of data transferal from a peripheral device to memory can be found in the following application note by Thomas Hardy, A Transparent DMA using a MC6809E MPU and a MC6844 DMAC, (1984). The use of traditional techniques leaves the designer with either the inefficient use of the processor's computing power or a data bus not always available to the processor, thus restricting the amount of calculations that can be performed by the processor within a certain amount of time. Although the above examples are well suited to their applications, a need exists for an inexpensive, small, transfer process which only uses one processor instruction cycle to load data from a peripheral device to the external memory of the processor and relinquish the use of the data bus for the use of the processor.

Summary of the Invention

The present invention encompasses a single instruction data transfer apparatus responding to a single triggering event from a governing device to transfer data from an output device to an input device. The apparatus, responding to the single triggering event, generates at least one signal which selects the input device and the output device. Upon selection of the output device, the apparatus couples the output device to the input device. Following the coupling of the output and input devices, the apparatus creates at least one signal to the input device which causes a write function to be enabled.

Brief Description of the Drawings

Figure 1 is a block diagram of a radio frequency data transmission system.

Figure 2 and 3 are, together, a block diagram of a receiver which may employ a single instruction data transfer apparatus.

Figure 4 is a memory map of the memory shown in FIG. 2.

Figure 5 is a process flowchart of the controller 103 for a data transfer from teh inphase ADC (209) to the memory (303).

Description of a Preferred Embodiment

A radio frequency system conveying a data signal from a transmitter 107 to a receiver 101 is shown in FIG. 1. In a radiotelephone system, the transmitter 107 would be a fixed site transmitter serving a radio coverage area which would be populated by mobile or portable transceivers, the receiver 101 of which is shown in FIG. 1. This radio contains a processor 105 which performs calculations on the data received by the radio. The data which is received by the radio must be transferred to the processor 105 for these calculations to be performed. The transfer of the in-phase (I) data and the quadrature (Q) data from the receiver 101 to the processor 105 is handled by the controller block 103.

FIG. 2 depicts a block diagram of a radio receiver 101. The receiver 101 acquires radio frequency (RF) signals from the fixed transceiver 107. Upon receipt of the signals, the receiver 101 filters 221 the signals and mixes 219 the RF signals with a local oscillator (LO) 223. After passing through an additional filter 217, the results are intermediate frequency signals (IF). Mixer 201 adds LO to the IF signals and mixer 203 subtracts LO from the IF signals, this results in base band (BB) signals. The BB signals is then passed through low pass filters 205, 207 to form in-phase (I) and Quadrature (Q) signals. The I signals are a result of directly mixing the LO 225 with the IF frequency and the Q signals are a result of phase shifting the LO 225 by 90 degrees and mixing it with the IF frequency. The I and Q BB signals are input into the two Analog to Digital Converters (ADC) 209, 211 where they are sampled at regular intervals by the sample clock and the results are stored in the buffers 213, 215. After sampling, the I and Q data is primed for transfer into the digital processing environment, where calculations will be performed on the data. The data in the buffers 213, 215 can be accessed by the processor 105 via the data bus 113. If the processor 105 requests data from the ADCs 209, 211 the controller module 103 controls the transfer of the data. The data is made available on the data bus 113 when the outputs of the tri-state buffers 213, 215 are enabled.

The digital processing environment of processor 105 is represented by the block diagram of FIG. 3. It consists of a digital signal processor (DSP, such as the DSP56001 available from Motorola, Inc. or similar DSP) 301 and a memory 303. The DSP 301, the memory 303, the controller 103 and the ADC's buffers 213, 215 are conventionally interconnected by the data and the address busses 113,111. The address bus 111 is used by the processor to point to a specific register location in the memory 303 or to the ADCs 209, 211. The dedicated control lines, such as the RD, WR and CS, are used to perform functions on the specific register selected by the address bus 111. The ADC's tri-state buffers 213, 215 are arranged as registers in the DSP's 301 memory maps 401, 403 enabling the

DSP to read from these buffers as if they were memory locations. The available processor memory consists of internal RAM and external RAM and ROM. The memory is addressed according to the memory maps of FIG.4. The DSP 301 is used by the radio to perform the equalization calculations on the data received by the radio. In the preferred embodiment the calculations include the following: (1) automatic frequency control (AFC), (2) correlation, (3) match filter, (4) power measurements, and (5) automatic gain control (AGO. The data used for the calculations are the sampled data from the ADC's buffers 213, 215 located in the receiver 101. The data and the results of the calculations are stored in the memory 303 and retrieved from the memory 303 by the combined use of the data bus 113, the address bus 111 and the memory maps 401, 403, 405. The memory maps utilized by the DSP 301 are described in FIG. 4. The addressable memory locations of the DSP 301 are broken into three individual maps; the X data memory 401, the Y data memory 403 and the program memory 405. All three memory maps have memory located internally to the DSP 301 and externally to the DSP 301. The numbers preceded by a $ along the left side of the memory maps 401, 403, 405 are the hexadecimal address locations used by the DSP 301 to refer to specific locations in the memory maps. The X and Y data memory 401, 403 and the program memory internal to the DSP 301 are addressed from $0000 to $00FF and in X memory from $FFC0 to $FFFF. All of the other addressable memory is external to the DSP 301. The external RAM for the X and Y data memory banks are addressed between $2000 and $2800. The addresses for the buffers of the ADCs 213, 215 are between $4000 and $4800. Notice that the I ADC buffer 213 location is in the X memory bank 203 and the Q ADC buffer 215 location is in the Y memory bank 205; this allows the DSP 301 to choose between the I and Q data by toggling the x y memory select line. The on chip peripherals are addressed in the X data memory 401 between

$FFC0 and $FFFF. The results of the calculations performed by the DSP 301 are stored in the X and Y data memory 401, 403. The results of the AFC calculations are written to Y: $FFF0, and the results of the AGC calculations are written to Y:$FFD0 and Y:$FFE0. The external program ROM is addressed between $8000 and $E000 in the program memory map 405. The transfer of data on the data bus is monitored by the controller 103. If the DSP 301 requests a read from either of the ADC buffers 213, 215, the controller alters the standard DSP 301 read routine. The read instruction from the DSP 301 is considered a single triggering event from a governing device. Referring to FIG. 5, the transfer process from the controller 103 is triggered at 501 by a read instruction from the DSP 301. The first test is carried out at 517 to check if the read command is for one of the receiver's two ADC buffers 213, 215. The controller 103 checks the address bus for an address between $4000 and $4800 knowing that these are the address locations of the receiver's ADC buffers 213, 215. If the read is requested for one of the ADC buffers, bit 14 (A14) on the address bus will be high and bit 13 (A13) will be low. If the read is for one of the ADC buffers 213, 215, the controller 103 decides which ADC to read from at 507. Upon determining this, the controller generates the DSP's x/y memory select line. If the line is asserted high 503, the DSP 301 will be addressing memory in the X data bank 401, low signifies memory in the Y data bank 403. If it is asserted high, at 505 the controller 103 generates a signal which will enable the outputs of the in-phase ADC's buffer 213; allowing the I data onto the data bus 113. If the x/y memory select line is low, then the controller 103 generates a signal which will enable the outputs of the quadrature ADC's buffer 215; allowing the Q data onto the data bus 113 at 511. The preceding enable signals select the appropriate output device. Since the DSP's external memory 303 consists of several 8K x 8 bit memories, only the 11 least significant bits are necessary to address any location within the memories. The higher order bits (A12 - A15) are used by the controller to select between memory chips or other peripheral devices in the memory maps 401, 403, 405. Since the lower bits of the external memory's address and the ADCs' memory address are identical, the only change necessary to effectively alter the address in the memory map 401, 403, 405 from the ADCs 213, 215 to the external memory 303 is to assert the chip select (CS) line for the external memory. At 507, the controller 103 generates signals which de-assert the external memory's read fine and assert the external memory's CS line, this is referred to as an altered read instruction. Next, the controller 103 asserts the external memory's write line and the external memory's CS line at 509, this is referred to as an altered write instruction. If the original DSP 301 address was outside of the $4000 - $4800 window at 503, then a standard DSP 301 read instruction would have been performed at 513. This completes the controller's 103 routine at 511. The controller 103 is responsible for determining if the requested DSP 301 read is for one of the ADC's buffers 213, 215, selecting between the I or the Q ADC buffer 213, 215, creating a corresponding write address and executing the write command.

The preferred embodiment fulfills the radiotelephone's requirements of size of the controller, cost of the controller and use of the processor. The controller 103 is implemented in a 16L8 PAL which is an inexpensive and small programmable part. The transfer process requires only one read instruction from the DSP 301 to carry out the entire transfer from one of the two ADC's buffers 213, 215 to the external memory 303 of the DSP 301. These meet or exceed the requests listed in the background of the invention. What is claimed is:

Claims

Claims
1. A single instruction data transfer apparatus, responding to a single triggering event from a governing device, transferring data from an output device to an input device, comprising:
means, responsive to the single triggering event, for generating at least one control signal which selects the input device and the output device;
means for coupling the output device data to the input device when the output device is selected; and
means, responsive to the single triggering event, for creating at least one control signal coupled to the input device which causes a write function to be enabled.
2. A single instruction data transfer apparatus in accordance with claim 1 wherein the input device further comprises an input/output device.
3. A single instruction data transfer apparatus in accordance with claim 2 wherein said at least one control signal coupled to the input device further comprises means for disabling a read function.
4. A digital radio telephone system employing a digital receiver which provides signal output corresponding to received radio signals and transferring data from an output device to an input device in response to a single triggering event, comprising:
means for converting the signal output to digital data;
means, responsive to the single triggering event, for generating at least one signal which selects the input device and the output device;
means for coupling the output device data to the input device when the output device is selected; and
means, responsive to the single triggering event, for creating at least one control signal coupled to the input device which causes a write function to be enabled.
5. A single instruction data transfer apparatus in accordance with claim 13 wherein the input device fiirther comprises an input/output device.
6. A single instruction data transfer apparatus in accordance with claim 14 wherein the at least one control signal coupled to the input device further comprises means for disabling a read function.
7. A single instruction data transfer apparatus, responding to a read instruction from a digital signal processor (DSP), transferring data from at least two peripheral devices to an external memory of the DSP, comprising:
means, responsive to the single triggering event, for choosing a first peripheral device from the at least two peripheral devices;
means, responsive to the single triggering event, for generating an output enable signal coupled to said first peripheral device;
means, responsive to the single triggering event, for generating an address corresponding to a location in the external memory of the DSP;
means for coupling said first peripheral device to the external memory of the DSP when said first peripheral device is selected; and
means, responsive to the single triggering event, for creating a read disable and a write enable signal coupled to the external memory of the DSP.
8. A single instruction data transfer apparatus in accordance with claim 16 wherein the peripheral device further comprises an ADC employing tri-state buffers on digital outputs.
9. A single instruction data transfer apparatus in accordance with claim 17 wherein said means for coupling further comprises a data bus between said tri-state buffers and the external memory of the DSP.
10. A method of responding to a single triggering event from a governing device to transfer data from an output device to an input device, comprising:
generating at least one signal, in response to the single triggering event, which selects the input device and the output device;
coupling the output device data to the input device when the output device is selected; and
creating a control signal, responsive to the single triggering event, coupled to the input device which causes a write function to be enabled.
11. A method of responding to a single triggering event in accordance with claim 19 further comprising the step of disabling a read function.
PCT/US1991/005877 1990-10-01 1991-08-19 A single instruction data transfer method and apparatus WO1992006566A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US59098690A true 1990-10-01 1990-10-01
US590,986 1990-10-01

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
BR919105908A BR9105908A (en) 1990-10-01 1991-08-19 Apparatus for data transfer, digital radio telephone system and the process of responding to a single trigger event
GB9211279A GB2254527A (en) 1990-10-01 1992-05-28 A single instruction data transfer method and apparatus

Publications (1)

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WO1992006566A1 true WO1992006566A1 (en) 1992-04-16

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BR (1) BR9105908A (en)
CA (1) CA2072662A1 (en)
FR (1) FR2669447A1 (en)
GB (1) GB2254527A (en)
MX (1) MX9101387A (en)
WO (1) WO1992006566A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984000653A1 (en) * 1982-08-03 1984-02-16 Motorola Inc Method and apparatus for measuring the strength of a radio frequency signal
US4638453A (en) * 1983-03-28 1987-01-20 Motorola, Inc. Signal processing unit
US4704734A (en) * 1986-02-18 1987-11-03 Motorola, Inc. Method and apparatus for signal strength measurement and antenna selection in cellular radiotelephone systems
US4776033A (en) * 1984-08-25 1988-10-04 U.S. Philips Corporation Selective calling and dialing arrangement for a mobile radio station in a radio transmission system
US4955070A (en) * 1988-06-29 1990-09-04 Viewfacts, Inc. Apparatus and method for automatically monitoring broadcast band listening habits

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NO173305C (en) * 1985-07-01 1993-11-24 Honeywell Inc Computer
GB2215945A (en) * 1988-03-26 1989-09-27 Stc Plc Digital direct conversion radio

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984000653A1 (en) * 1982-08-03 1984-02-16 Motorola Inc Method and apparatus for measuring the strength of a radio frequency signal
US4638453A (en) * 1983-03-28 1987-01-20 Motorola, Inc. Signal processing unit
US4776033A (en) * 1984-08-25 1988-10-04 U.S. Philips Corporation Selective calling and dialing arrangement for a mobile radio station in a radio transmission system
US4704734A (en) * 1986-02-18 1987-11-03 Motorola, Inc. Method and apparatus for signal strength measurement and antenna selection in cellular radiotelephone systems
US4955070A (en) * 1988-06-29 1990-09-04 Viewfacts, Inc. Apparatus and method for automatically monitoring broadcast band listening habits

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Publication number Publication date
GB9211279D0 (en) 1992-07-22
MX9101387A (en) 1992-06-05
GB2254527A (en) 1992-10-07
FR2669447A1 (en) 1992-05-22
BR9105908A (en) 1992-11-03
CA2072662A1 (en) 1992-04-02

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