FR2662888A1 - Device for generating a clock signal at lower frequency than the frequency of a reference clock signal, and not an integer submultiple of it - Google Patents

Abstract

This device comprises: - means (1) for deriving, from the frequency F of the reference clock signal, I frequencies F DIVIDED Xi, which are integer submultiples of the frequency F, with Xi a positive integer, I an integer equal to or greater than 1, and i varying from 1 to I, - means (2) for subtracting pulses from the reference clock signal, at the mean frequency of the sum of the frequencies F DIVIDED Xi thus derived, - a frequency divider (3) for dividing by an integer number N, operating on the output signal of the pulse subtraction means and supplying the clock signal at frequency F' sought, with: N < F DIVIDED F' < N+1 F - NF' = A A = F. ( SIGMA DIVIDED i=1 1 DIVIDED Xi) Application especially to digital telecommunications equipment.

Description

Device for generating a clock signal of frequency lower than the frequency of a reference clock signal and not an integral sub-multiple thereof.

 The present invention relates to a device for generating a clock signal of frequency lower than the frequency of a reference clock signal and not an integral sub-multiple thereof.

 Such a device is capable of receiving numerous applications, and can be used in particular in digital telecommunications equipment, such as digital multiplexing equipment, where it is in fact generally necessary to have simultaneously several clock signals of determined frequencies, whereas cost and space constraints lead to a reduction in the number of oscillators usually used in this equipment to supply the various clock signals sought.

The subject of the present invention is a device for generating a clock signal of frequency F ′ lower than the frequency F of a reference clock signal and not an entire sub-mutiple thereof, essentially characterized in that what it includes
means for developing, from the reference clock signal, I clock signals of sub-multiple frequencies F
Xi integers of the frequency F of this signal, with Xi positive integer, I integer greater than or equal to 1, and i varying from 1 to I,
means for subtracting pulses for subtracting pulses from the reference clock signal at the average frequency from the sum of the frequencies F thus produced,
Xi
- a frequency divider by an integer N, operating on the output signal of the pulse subtraction means and providing the desired clock signal of frequency F 'with N <F <N + l
F '
F - NF '= A

According to another characteristic of the invention, the means for producing I clock signals of frequencies F comprise a
Xi battery of I frequency dividers in parallel by whole numbers Xi, operating on the reference clock signal.

According to another characteristic of the invention, the frequencies F and A verifying the relationship A = F. Ni, with Ni and N2
N2 positive integers, the means for developing I clock signals of frequencies F include a frequency divider-counter by N2
Xi operating on the reference clock signal and a decoding circuit of Ni particular states of this frequency counter-divider.

Other objects and characteristics of the present invention will appear on reading the following description of an exemplary embodiment, said description being made in relation to the attached drawings in which
FIG. 1 is a block diagram of a device according to the invention,
FIG. 2 is a diagram of a device according to the invention, usable in the case of particular values of frequencies taken by way of example,
FIG. 3 is a diagram of the device shown in principle in FIG. 2,
- Figure 4 shows an alternative embodiment of the device shown in Figures 2 and 3.

 The frequency of the reference clock signal is designated by F and the desired frequency by F ′.

Let N and N + l be two positive integers verifying the relation
N <FCN +1
F '
and let A be the number verifying the relation
F - NF '= A
with O <A <F '
According to the invention, to develop the clock signal of frequency F 'sought from the reference clock signal of frequency F, A is expressed as a function of F in the form of a series of integer sub-multiples of F , which can possibly be reduced to a single element

 with Xi positive integer whatever i.

The desired frequency F 'expressed by the ratio F' = FA,
N the frequency generation device according to the invention, represented in principle in FIG. 1, then comprises
means 1 for developing, from the reference clock signal, HF, I clock signals of sub-multiple frequencies F
Xi integers of the frequency F of this signal,
- means for subtracting pulses 2 receiving the reference clock signal HF as well as each of the I clock signals of frequencies F supplied by the means 1, for subtracting
Xi of the pulses to the reference clock signal, at the average frequency of the sum of the frequencies F thus produced,
Xi
a frequency divider 3 by an integer N, operating on the output signal of the pulse subtraction means and supplying the clock signal HF ', at the frequency F' sought.

In the embodiment shown in FIG. 1, the means 1 for developing the frequencies F comprise a battery
Xi of I frequency dividers, 11 to 11, by whole numbers Xi, in parallel, operating on the frequency reference clock signal
F. It will be noted that, as a function of the values of the numbers Xi, at least some of the divisors li may include circuits common to several of them.

 FIG. 2 shows the block diagram of a device according to the embodiment given in FIG. 1, applicable in particular to equipment for multiplexing digital trains incident at 2048 kbit / s into an outgoing digital train at 34368 kbit / s , with the formation of digital intermediate trains at 8448 kbit / s, and corresponding to the values F = 34368kHz and F '= 8448 kHz.

In this example, the numbers N, I and Xi have the following values
N = 4 1 = 2
X1 = 60
X2 = 179.60 = 10740
In Figure 2 are referenced
- H34 the reference clock signal of frequency F equal to 34368 kHz,
HO, 5728 the frequency signal 572.8 kHz obtained at the output of the frequency divider 11 by 60,
- HO, 0032 the 3.2 kHz frequency clock signal obtained at the output of the frequency divider 12 by 10740 consisting of the frequency divider by 60, followed by a 1'2 frequency divider by 179 receiving the signal as an input HO, 5728,
- H33 the clock signal of frequency 33792 kHz obtained at the output of the pulse subtraction means 2, the latter drawing pulses from the reference signal H34 at the average frequency of 576 kHz equal to the sum of the two frequencies 572.8 kHz and 3.2 kHz.

 A more detailed embodiment of this device, and in particular means 2 for subtracting pulses, is given in FIG. 3.

The pulse subtraction means 2 comprise two flip-flops of type "D", 46 and 47, whose clock inputs CLK receive the clock signal H34, and whose inputs D are respectively connected to an inverting output, referenced S, of the divisor of
Qof the frequency divider frequency 1 and at the inverting output S of the frequency divider 2.

 The pulse subtraction means also include two "non-OR" gates 48 and 49, the inputs of which are connected to the output Q of the flip-flop "D" 46 and to the non-inverting output, referenced S, of the frequency divider 11, for the "non-OR" gate 48, at the Q output of the flip-flop "D" 47 and at the non-inverting output S of the frequency divider 1'2, for the "non-OR" gate 49.

 The output signals of the "non-OR" gates 48 and 49 are applied to an "OR" gate 43 whose output constitutes the output of the means 2 for subtracting pulses.

 An alternative embodiment of the device which is the subject of FIGS. 2 and 3 is shown in FIG. 4.

sous la forme
A = F. N1
N2
avec N1 et N2 entiers positifs
qui est, pour les valeurs de fréquences considérées, la suivante
576 = 34 368. 3
179 et qui correspond donc aux valeurs suivantes pour I et Xi 1=3
X1 = X2 = X3 = 179
La fréquence moyennne 576 kHz s'obtient alors par soustraction de 3 impulsions sur 179 à la fréquence de référence 34368 kHz. Dans le dispositif représenté sur la figure 4 les moyens 1 d'élaboration des fréquences F comportent alors un compteur-diviseur
Xi de fréquence 10 par 179, suivi d'un décodeur 11 de-trois états particuliers de ce compteur, par exemple les états 0,60 et 120.This variant is based on a particular writing of the relation

Under the form
A = F. N1
N2
with N1 and N2 positive integers
which is, for the frequency values considered, the following
576 = 34,368. 3
179 and which therefore corresponds to the following values for I and Xi 1 = 3
X1 = X2 = X3 = 179
The average frequency 576 kHz is then obtained by subtracting 3 pulses out of 179 from the reference frequency 34 368 kHz. In the device represented in FIG. 4, the means 1 for developing the frequencies F then comprise a counter-divider
Xi of frequency 10 by 179, followed by a decoder 11 of three particular states of this counter, for example states 0.60 and 120.

 The pulse subtraction means 2 comprise an OR gate with four inputs receiving respectively the reference signal H34 and the three output signals from the decoder 11.

 A frequency divider by four, 3, is, as in FIGS. 2 and 3, arranged at the output of the pulse subtraction means 2.

sous la forme

avec
M1, M2 entiers positifs
j entier positif
Yj entier positif différent de M2 et différent de Yk quel que
soit k différent de j compris entre 1 et J et donc
M1 + J = I, le dispositif de génération de fréquence suivant l'invention pourra comporter, pour l'élaboration des I signaux d'horloge de fréquences
F, J diviseurs de fréquence en parallèle par les nombres Yj, opérant
Xi sur le signal d'horloge de référence et fournissant J signaux de fréquences F , et un compteur-diviseur de fréquence par M2 opérant
Yj également sur le signal d'horloge de référence et suivi d'un décodeur de M1 états particuliers de ce compteur-diviseur fournissant M1 signaux distincts de fréquence F
M2 Particular examples of embodiment of the invention have been described, but it is obvious that the invention is not limited to these particular examples. In particular, according to the values of the frequencies F and F 'leading to a particular writing of the relation

Under the form

with
M1, M2 positive integers
j positive integer
Yj positive integer different from M2 and different from Yk whatever
let k be different from j between 1 and J and therefore
M1 + J = I, the frequency generation device according to the invention may include, for the preparation of the I frequency clock signals
F, J frequency dividers in parallel by the numbers Yj, operating
Xi on the reference clock signal and providing J signals of frequencies F, and a counter-divider of frequency by M2 operating
Yj also on the reference clock signal and followed by a decoder of M1 particular states of this counter-divider providing M1 distinct signals of frequency F
M2

Claims (3)

 F - NF '= A  F '  N <F (N + 1  - a frequency divider (3) by an integer N, operating on the output signal of the pulse subtraction means and supplying the clock signal of frequency F 'sought, with  Xi  - means (2) for subtracting pulses for subtracting pulses from the reference clock signal, at the average frequency, from the sum of the frequencies F thus produced,  Xi integers of frequency F, with Xi positive integer, I integer greater than or equal to 1, and i varying from 1 to I,  - Means (1) for developing, from the frequency F of the reference clock signal, I sub-multiple F frequencies Claims: 1) Device for generating a clock signal of frequency F 'lower than the frequency F of a reference clock signal, and not an integral sub-multiple thereof, characterized in that it behaves  2) Device according to claim 1, characterized in that the means (1) for developing I clock signals of frequencies F  Xi have a battery of I frequency dividers in parallel (ll, ... lI) by whole numbers Xi, operating on the reference clock signal. 3) Device according to claim 1, characterized in that the frequencies F and A verifying the relationship  A = F. N1  N2 with positive integers N1 and N2, the means (1) for generating I clock signals of frequencies F comprise a counter-divider  Frequency Xi (10) by N2 operating on the reference clock signal and a circuit (11) for decoding N1 particular states of this frequency counter-divider.