FR2652926A1 - METHOD FOR OPERATING THE MEMORY IN A VIRTUAL ADDRESSING TYPE COMPUTER SYSTEM AND DEVICE FOR IMPLEMENTING SAID METHOD. - Google Patents

Abstract

The method and apparatus for using the memory in an information processing system of the virtual addressing type is characterized in that a first memory domain DX is organized around a logical address of NX bits in size. In the memory domain DX, a plurality of address spaces EAX of identical structure is defined and relative addressing of a size NL less than NX is allowed. One of the address spaces EAX (hereinafter the current address space EAC) is assigned temporarily and interchangeably to a second memory domain DL organized around an address that is NL bits in size.

Description

The invention relates to a method for exploiting memory in a

  virtual address type computer system and apparatus for carrying out said method. The known concept of virtual addressing (or virtual memory) makes it possible to offer the system and its users a logical memory capacity much greater than that of the physical memory. In combination with the concept of segmentation also known that divides the virtual memory zones (called segments) independent of each other, virtual addressing has proved particularly well suited to the multi

  programming and multiprocessing.

  The steady and significant increase in the capacity of the physical components constituting the memory of a computer system (1 MB DRAM dynamic random access memories are currently available on the market) requires a corresponding increase in virtual memories. However, operating systems designers for computer systems are confronted with various problems related to addressing, among which: the size of the addressing format becomes insufficient

and must be extended.

  -the new extended addressing operating system must be compatible with the old one to allow, at least for a fairly long transition period, the execution of the existing user programs designed

  according to the old operating system.

  The object of the invention is a high-capacity virtual memory operation method which satisfies the compatibility requirement with a great deal of flexibility.

for users.

  More particularly, the invention proposes a method for exploiting the memory in a computer system of the virtual addressing type, characterized in that: -on organizes a first memory domain DX around a NX bit size addressing, -on defines in the memory domain DX a plurality of address spaces EAX of identical structure and admitting a relative addressing of dimension NL bits less than NX, -on temporarily and interchangeably assigns one of the address spaces EAX (hereinafter called current space EAC) to a second memory domain DL organized around a

NL bit size addressing.

  In a first mode of implementation of the method according to the invention, an address format FX1 of dimension NX makes it possible to access the EAX spaces by extension of a relative addressing format FL of dimension NL by means of a complementary zone containing at least one field intended for

  receive the identifier of the corresponding EAX space.

  Thus by the temporary assignment of one of the EAX interchangeable address spaces to the DL domain and the particular reformatting of the addresses according to the two available address sizes NL and NX (for example 32 and 64 bits) the new organization of the memory offers the possibility of using both address dimensions concurrently. The organization of the virtual memory according to the invention thus appears to be much greater than a simple linear extension of memory which does not offer the possibility for existing programs to take advantage of this extension. According to another embodiment of the method in accordance with the invention, the memory domain DL comprises a permanent address space EAPCB of identical structure to that of the address spaces EAX, the space EAPCB being detectable in the domain DX by an identifier of

value equal to zero.

  Advantageously, the address spaces are of the segmented type, optionally in several dimensions

  and / or sharable by several processes.

  According to yet another embodiment of the method according to the invention, a plurality of segments accessible from a second are defined in the memory domain DX.

  FX2 addressing format of NX dimension.

  The implementation of the method according to the invention shows all its flexibility in the execution of the processes by the computer system. More particularly, according to yet another variant of the invention: for the address spaces of dimension NL, the spaces EAX and possibly the space EAPCB, PD procedure descriptors of identical basic structure are chosen, -on defines address space descriptors (hereinafter referred to as CASDs) of the same basic structure as the PD procedure descriptors, -on organized from an executable process in a given address space, the call an executable procedure in another address space by

  through a CASD type descriptor.

  Advantageously, the CASD descriptors comprise a field intended to receive the identifier of the address space containing the called procedure and the pointer of the called procedure in the new address space. Thus an existing program designed according to the limited-size addressing mode DL is likely by the set of procedure calls in other address spaces to take full advantage of the new capabilities of the system. It is also possible for these old programs to be contained in full including the code

  in the new address spaces.

  The invention also relates to a computer system comprising the hardware and software means for implementing the method presented above in all its variants. More precisely, the computer system comprises a central subsystem structured around one or more central processors (CPU) and a memory

  each processor comprising micro-means

  programmed to perform the management of the central memory and IOC input / output controllers to peripheral subsystems, in particular of the mass memory type of sufficient capacity for virtual addressing and software means, in particular a set of grouped programs under the name of operating system, to allow in association with the

  micro-programmed means the implementation of the invention.

  The invention is now described with reference to the accompanying drawings in which: - Figure 1 is a diagram of a computer system implementing the method according to the invention, - Figure 2 is a schematic representation of the segmentation. of the virtual memory according to the invention, - Figure 3 is a schematic representation of the organization of 32 and 64 bit memory domains according to the invention, Figure 4 is a representation of the FX2 format of a first data descriptor FIG. 5 is a diagrammatic representation of the addressing development from the descriptor illustrated in FIG. 4, Another 64-bit / 4MB / ITS64 64-bit data descriptor according to the invention, FIG. 7 is a schematic representation of an addressing development from the descriptor illustrated in FIG. FIG. 8 is a schematic representation of the FL format of the 32-bit 64K / 4MB / ITS32 data descriptor used in the implementation of the invention; FIG. 9 is a diagrammatic representation of the format of the register; CSR according to the invention, - Figure 10 is a schematic representation of the format of an absolute address descriptor in physical memory AA64 64-bit dimension according to the invention, - Figure 11 (Figures 11 (1) and 11 (2)) is a diagrammatic representation of a PCB process control block according to the invention; FIG. 12 is a schematic representation of a stack element according to the invention, FIG. schematic of a PD32 procedure descriptor used in Mode 32 and in Mode 32/64; FIG. 14 is a schematic representation of a CASD procedure descriptor used in the event of a change of address space, FIG. 15 is a representation sch of a PD64 procedure descriptor used in Mode 64, - Figure 16 is a schematic representation of a particular format of the instruction counter register IC used in the invention; - Figure 17 is a schematic representation of the mechanism of basis of a procedural descriptor type procedure call and used in the context of the invention, - and FIGS. 18, 19 and 20 are schematic representations of the dynamic process mode change mechanism, according to cases N 1, 2 and 3

provided in the invention.

  By convention, in the continuation of the exposition the initials "**" will designate the mathematical expression "exponent", for example 2 ** 10 = 1024. Similarly, the initials "<>" will designate

  the mathematical expression "different from".

  In the embodiment of the invention described here by way of non-limiting example, the computer system has been designed to remain compatible with existing systems supporting 32-bit addressing. As a result, the system according to the invention incorporates, to varying degrees, certain hardware and software elements of the current systems. In order not to overload the following presentation, it will focus on the presentation of the invention itself. Also the reader will be able to refer for more details on the available documentation and more particularly on the US Pat. No. 4,385,352 concerning a device for developing and calculating an address in a segmented memory, and on US Pat. No. 4,297,743 concerning a call mechanism

  procedure and cooperating stack mechanism for computer.

  In addition, it seems appropriate to recall at this stage of the presentation the following few definitions: - Process: a process is defined as an ordered sequence of operations defined by instructions that are likely to be executed asynchronously by the sub - central system. As a result, several processes can be active and share resources provided by the system, but in a given processor, only one process is running at a given time. A process group is a set of associated processes required to execute a job step for which specific resources have been temporarily allocated by the system. Each process has in memory an area called process control block (PCB) in which the information needed to execute the process by the user can be saved.

system.

  -Proceedure: A procedure is defined as an identifiable set of program instructions appropriately

  linked to be executed as part of a process.

  To switch from one procedure to another or use the various services of the operating system (especially when operating programs structured in a modular way), we use a particular mechanism (detailed during the presentation) called call of procedure. One of the merits of the invention is to have kept this call mechanism (very appreciable for the degree of performance of the system) its effectiveness despite the two addressing dimensions. Addressing space: area of the memory allocated to a process and accessible by the latter. Most often the addresses used by a process are logical addresses and not absolute addresses in the main memory. - Segmentation of the main memory: To meet the virtual memory needs of a process, the address space is assigned statically during the construction of the process or dynamically during the life of the process in segments of variable dimensions generally non-contiguous . The process thus has access to its own segments of memory, or associated segments, through a segment descriptor system describing them. These descriptors are contained

  in tables managed by the operating system.

  In order to minimize the size of the tables in the main memory, segment sharing levels coded from (0) to (3) have been defined. Regardless of the sharing levels, the system may incorporate a system of privilege between processes, for example a system using the ring concept described in the application for

U.S. Patent 4,177,510.

  Referring to FIG. 1, the computer system comprises two main subassemblies, the central subsystem 100 comprising in particular the central memory MMU 102 and the peripheral subsystem 104. The central subsystem 100 is structured around the central subsystems 104. CPU 106 central processors connected to IOC input / output controllers 108. These controllers 108 communicate through I / O input / output channels with the peripheral subsystem 104 through UCP peripheral control units, they themselves connected by AD 112 adapters to the most diverse PER 114 devices, including mass memories (disk memories), active screen and keyboard terminals, printers and data transmission devices. Number of

  Peripherals can reach several hundred.

  The central memory MMU 102 is constituted by a network of dynamic random-access memory (DRAM) semiconductor chips with a total maximum capacity of 1024 gigabytes (1024 GB). Optionally, there is provided in each processor a cache (not shown) to reduce the access and transfer times of

  information most often processed.

DOMAIN OF ADDRESSING

  Figures 2 and 3 illustrate schematically

  the organization of the virtual memory according to the invention.

  The main memory is organized into three types of segments of increasing size: - segments of 64 kilobytes or 2 ** 16 bytes (64 KB) segments of 4 megabytes or 2 ** 22 bytes (4 MB)

  - segments of 4 gigabytes or 2 ** 32 bytes (4 GB).

  The segments of the first two types are grouped in batches, hereinafter called 64K / 4MB address spaces or EAX spaces, with a total capacity of 256 Megabytes or 2 ** 28 bytes and consisting of: 32 segments type 4 MB and

2040 segments type 64 KB.

  Finally, the 64K / 4MB address spaces and the 4GB segments are grouped into 4 slots with a unit capacity of 68,000 Terabytes (1 Terabyte equaling 2 ** 40 bytes) and consisting of: 2 ** 24 segments of type 4 GB and

2 ** 24 64K / 4MB address space.

  The 4 slices correspond to the four levels of division of the segments, respectively the level (0) or "system", the level (1) or "undefined", the level (2) or "group of

  process "and level (3) or" process ".

  The total capacity of the virtual memory thus constituted is 272.000 terabytes, (capacity between 2 ** 58 and 2 ** 59 bytes). Obviously, the memory domain thus constituted DX requires logical addressing of compatible NX dimension. The NX dimension can be contained in a 64-bit pointer. Similarly EAX address spaces of limited memory capacity allow a relative logical addressing whose NL dimension can be

contained in a 32-bit word.

  EAX spaces are identifiable by a serial number or more generally by a more elaborate identifier; for example in the embodiment of the invention presented here, the identifier (illustrated in FIG. 9) consists mainly of a zone indicative of the level of division of the segments and a

  order number in the corresponding memory slot.

  Referring to FIG. 3, it will be noted that within the memory domain DX, a memory domain DL has been defined comprising one of the 64K / 4MB EAX addressing spaces temporarily and interchangeably allocated to this DL domain which admits a 32-bit address dimension. This EAX type space assigned to the DL domain is hereinafter called current address space EAC. To improve compatibility with existing programs designed under 32-bit addressing, a permanent address space called EAPCB space with the same structure as the 64K / 4MB spaces is assigned to the DL memory domain. In the DX domain this EAPCB space is identifiable by its value identifier equal to zero (all bits of the identifier field are zero-valued). So the memory domain DL supporting a 32-bit addressing has a

capacity of 512 megabytes.

  Figures 4 and 6 show the two types of

  data descriptors using 64-bit addressing.

  In general, these formats are structured around 32-bit words (numbered from 0 to 31 from left to right) sometimes joined together in the form of double words of 64 bits (the bits of the second word then being numbered from 32 to 63 from left to right). These formats are likely to be used also for data and for instructions. Data are in binary form but can be interpreted as binary, decimal, floating or alphanumeric. Data bits are interpreted in groups of four when encoded in decimal-coded-binary, in groups of eight for alphanumeric data, in groups of 64 or 128 bits for floating data, and in groups of 1 to

64 for binary data.

  Byte locations in main memory are numbered consecutively from scratch. Each number corresponds to the physical address of the byte. According to the example described, a word is formed of 32 bits, that is to say of 4 bytes. Also, a group of bytes can be aligned on a half word, a word, a double word or a quad word, if the address of the left byte of the group is respectively a multiple of 2, 4, 8 or 16. In this case, an entire group of data bytes can be bulk extracted from the memory. The location of the data in the memory is obtained from a data (address) descriptor by an address development mechanism

detailed later.

  Figure 4 illustrates the FX2 format of a 64-bit data descriptor corresponding to the larger segments, ie 4 gigabytes. The descriptor called 4GB / ITS64 comprises two words and is broken down as follows: a first field formed of the first two bits O and 1 and called TAG contains the binary value 01, a second field formed of bits 2 and 3 and called RING contains a binary value representative of the privilege level associated with the pointer during access to the data of the addressed segment (ring number), - a third field formed of bits 4 and 5 and called XTAG contains a binary value representative of the standard code of the descriptor . More precisely, XTAG = 00 corresponds to a direct addressing (the address development leads to the sought object), XTAG = 01 corresponds to an absolute addressing in physical memory and which is obtained by a concatenation of the XSN and XSRA fields (this operation will be described later with reference to FIG. 10), XTAG = 10 corresponds to indirect addressing (the address development leads to another 64-bit data descriptor itself leading directly or indirectly to the object sought ), XTAG = 11 corresponds to a fault leading to a special exception procedure, - a fourth field formed of bits 6 and 7 and called SHR contains a binary value representative of the sharing level, from (0) to (3), of the addressed segment, that is to say of the memory slot in which this segment is located, - a fifth field formed of bits 8 to 31 (24 bits) and called XSN contains a binary value representative of the sequence number of segment addressed in the corresponding memory slot, - a sixth field formed of bits 32 to 63 (2nd word) and called XSRA contains a binary value representative of the displacement in the segment (relative address) of the object

  the process is seeking access.

  The address development (illustrated in FIG. 5) of this 4GB / ITS64 descriptor is carried out as follows from the data contained in specific areas of the PCB memory block (process control block) corresponding to the process searching for the access to the addressed 4GB segment. For this purpose, the PCB block illustrated in part in FIG. 5 comprises 4 zones of a length of a double word (2 words of 32 bits) called ASDW4 (for SHR = 0), ASDW5 (for SHR = 1), ASDW6 (for SHR = 2) and ASDW7 (for SHR = 3). The zones ASDW4 / 7 (double word of address space) are really significant only insofar as the content of the field P (bit 32 or Presence bit) is equal to unity. This field P indicates the presence in memory of the structure sought, here a segment descriptor table called XST. In the case where this presence bit P equals zero, an exception procedure is initialized in order to load into memory the

Descriptor list searched.

  The fields ASDW4 / 7 comprise two other fields, the first one named NBMAX (bits 8 to 31) defines the number of entries in the table XST (maximum 2 ** 24) and the second named XSTA (bits 33 to 63) is a pointer that defines the absolute address in multiples of 16 of the first entry of the XST table. This absolute address will therefore be obtained by adding 4 zeros on the low-weight side to the value of XSTA. Generally speaking, in the following

  description, the term "input" will refer to the first octet

  of an element of a table, while the term "pointer" designates a value representative of the absolute address

  such an entrance. The pointer will often be a sub

multiple of the absolute address.

  The content of the XSN field of the 4GB / ITS64 descriptor is then used to access twice the XST table.

  DSD.4 segment descriptor formed of a quad word.

  In addition to the presence bit P (bit 0) and the various protection fields, this quadruple word, corresponding to a double direct descriptor, comprises a PTWAA address pointer (bits 32 to 63) giving in multiples of 16 the absolute address the first entry in the table of PTWA page table words, and a segment dimension field (bits 64 to 87) whose value increased by one unit gives multiple

  4096 bytes the size of the segment.

  The content of the XSRA field of the 4 GB / ITS64 descriptor is then used in part. In fact, the field XSRA is divided into three zones (see FIG. 4), a PTN subfield (bits 32 to 41) corresponding to the page table number PT, a subfield PTE (bits 42 to 51) corresponding to the number in the page table of the corresponding segment, and a subfield PRA (bits 52 to 63) corresponding to the relative address of the structure sought in the page whose dimension is 4

Kilobytes is 2 ** 12 bytes.

  Thus, the content of the PTN subfield gives the sequence number of the entry in the table of PTWA page table words (maximum size MAX = 2 ** 10 entries) and allows

  to access the word (32 bits) of table of searched pages.

  The latter comprises in addition to the presence bit P, the absolute address PTA of the first entry of the searched page page PT (maximum size MAX = 2 ** 10 entries). The content of the subfield PTE gives the order number of the entry sought in the page table PT and provides access to the page descriptor and which comprises in addition to the presence bit P, the absolute address of the first byte of the page. This mechanism that translates a virtual address (also called segmented address) into real address is generally associated with an acceleration device using associative memory to directly match the real addresses to virtual addresses for subsequent uses of these addresses. Figure 6 illustrates the FX1 format of another 64-bit data descriptor corresponding to segments embedded in the 64K / 4MB spaces. This descriptor called 64K / 4MB / ITS64 comprises two words and is broken down as follows: the first field called TAG formed of bits 0 and 1 contains a binary value representative of the descriptor code. More particularly, TAG = 00 corresponds to direct addressing, TAG = 01 refers to a type descriptor of 4GB / ITS64 type, TAG = 10 corresponds to indirect addressing, TAG = 11l corresponds to a defect leading to a

special exception procedure.

  the second field formed of the bits 2 and 3, and denominated RING contains a binary value representative of the privilege level associated with the pointer during access to the data of the addressed segment (ring number), the third field formed of the bits 4 to 8 (4 bits) called STN contains a binary value representative of the sequence number of an entry in the word table of STWA segment tables, - the fourth and fifth fields called STE and SRA representative of the number of an entry in the ST segment table and the relative address of the searched object in the segment under consideration, have two different formats depending on the type of segment addressed. The addressing to a segment of type 4MB (STE is defined by bits 8 and 9 and SRA by bits 10 to 31) corresponds to a decimal value of STN between 0 and 7. The addressing to a segment of type 64KB (STE is defined by bits 8 to 15 and SRA by bits 16 to 31) corresponds to a value

  decimal of STN between 8 and 15.

  As before, the SRA field has two subfields, the subfield PTE corresponding to the order number of the entry in the page table (length 10 or 4 bits depending on the type of segment) and the subfield PRA ( bits 20 to 31) corresponding to the relative address in the page of

the object sought.

  The second word of the 64K / 4MB / ITS64 descriptor comprises the sixth, seventh and eighth fields: the sixth field (bits 32 to 37) contains the zero bit value; the seventh field (bits 38 to 39) called SHR contains a value binary representative of the shared level of the addressed segment, and the eighth field (bits 40 to 63) called ASN contains the serial number allowing the identification of the space

corresponding EAX address.

  The address development (illustrated in FIG. 7) of this 64K / 4MB / ITS64 descriptor is performed as follows from the data contained in specific areas of the corresponding PCB memory block. For this purpose the PCB block (illustrated in part in FIG. 7) comprises 4 zones of a length of a double word called ASDWO (for SHR = 0), ASDW1 (for SHR = 1), ASDW2 (for SHR = 2 ) and ASDW3 (for SHR = 3). As before, the ASDW0 / 3 address space double words are really significant only insofar as the content of the presence bit P (bit 32) is equal to 1. The ASDW0 / 3 zones comprise two other fields, the first named NBMAX (bits 8 to 31) defines the number of entries, in the main table of XSTWA segment table words (maximum 2 ** 24) and the second named XSTWAA (bits 33 to 63) is a pointer that defines the absolute address in multiples of 16

  of the first entry of the XSTWA table.

  The content of the ASN field of the descriptor 64K / 4MB / ITS64 is then used to access the corresponding word XSTW which comprises, in addition to the presence bit P, the STWAA field (pointer) representative of the absolute address of the first input of a table of STWA segment table words. The STN field of the 64K / 4MB / ITS64 descriptor then makes it possible to access the word containing the STA (pointer) field which defines the absolute address in multiples of 16

  of the first input of the ST segment table. The contents of the STE field of the descriptor 64K / 4MB / ITS64 are then used

  to access in the ST table double DSD.2 segment descriptor consisting of a double word. In addition to the presence bit P (bit 0) and the various protection fields, the double word corresponding to a direct descriptor comprises a PTA address pointer (bits 8 to 31) giving in multiples of 16 the absolute address of the first input of the corresponding page table PT and a field of dimension SZ (bits 46 to 55) whose value increased by one unit gives in multiples of 4096 bytes the size of the segment. The content of the subfield PTE makes it possible to access in the table PT the page descriptor corresponding to the searched page and which comprises, in addition to the presence bit P, the pointer PAGE of the absolute address of the first byte of

the searched page.

  FIG. 7 also shows, under the name STWA (0.0), the table of segment table words corresponding to SHR = 0 and ASN = 0. Access to this particular table which corresponds to the EAPCB address space can be achieved directly with appreciable time saving from a particular area of the PCB block, called space-address word or ASW.0, of dimension equal to one word and which contains the pointer of the absolute address of the first entry of the STWA table (0.0). This faculty is very interesting in terms of the compatibility of the system according to the invention with respect to existing programs structured on 32-bit addresses according to the format FL given in FIG. 8. It is thus possible to share data in both addressing domains to

32 bits (DL) and 64 bits (DX).

  Given the identity of the structures used in the 32 bit address DL domain (EAPCB space and EAC space) with the EAX address space structures consisting of the 64KB and 4MB segment lots, the format of the data descriptor in 32-bit addressing referred to as 64K / 4MB / ITS32 shown in FIG. 8, has a structure identical to that of the first word of the 64K / 4MB / ITS64 descriptor illustrated in FIG. 6, it being understood that the RING and EAR fields are equivalent. An address in the EAPCB space is obtained by TAG = 00. On the other hand TAG = 01 leads to an address in the current address space EAC identifiable among the spaces EAX. For this purpose a special register CSR has been created to store the value of the identifier of the space EAC, that is to say of the identifier of the EAX spaces which is then temporarily assigned to the domain DL. This CSR register, the format of which is illustrated in FIG. 9, has the size of a word and is identical to that of the second word of the 64K / 4MB / ITS64 descriptor. I1 consists of three fields, the first formed of the bits O to 5 each containing the binary value 0, the second SHR formed of the bits 6 and 7, contains a value representative of the sharing level of the addressed segment, and the third ASN formed bits 8 to 31 contain the identification (actually the serial number in the corresponding memory slot) of the batch of segments

  forming the address space EAX considered.

  Figure 10 illustrates the format of an AA64 64-bit descriptor for absolute addressing in physical memory. This format is derived from the 4GB / ITS64 descriptor shown in Figure 4 corresponding to the 4GB type segments and in which the XTAG = 01 field. The MBZ field formed from bits 6 to 24 (incorporating the SHR field which is not significant in this case) is set to a value equal to zero. The first eight most significant bits of the absolute address are arranged in the field formed by the bits 24 to 31 while the least significant bits of the same absolute address are arranged in the field formed by the second word of the descriptor, ie the bits 32 to 63. As a result, the absolute addressing capacity is 2 ** 40 bytes or 1024 gigabytes. Absolute addressing from a 32-bit descriptor is not possible directly. It is necessary beforehand to perform a format change operation to switch to a 64-bit format, an operation that

will be described later.

MODES OF EXECUTION OF PROCESSES

  The different versions of memory addressing that have been presented are used fully in the three process execution modes implemented in the computer system in the context of the invention: the first mode called "Mode 32" uses the 32-bit addressing. - The second mode called "Mode 64" uses 64-bit addressing. - The third mode called "Mode 32/64" uses double addressing for certain segments and under conditions

  details detailed later.

  The first mode is derived from what is used by the applicant in his system called "DPS7". In particular the PCB process control block corresponding directly to this Mode 32 has substantially the same format as that described in US Patent 4,297,743. It can be recalled that the PCB block contains the memory areas corresponding to the 8 base registers (32 bits per register), 16 general registers (32 bits per register), 4 scientific calculation registers (64 bits per register), a storage zone or backup of the IC register (instruction counter) (32 bits), a storage area of the T register (stack vertex) (32 bits), a storage area of the register STR (status register) (8 bits). However, absolute addressing is no longer allowed on 32 bits but can be obtained after changing the mode of the process to Modes 64 or 32/64. Indeed the standard code TAG = 01 is used for

  virtual address developments in 32/64 Mode.

  Thus the first mode of execution known as Mode 32 is capable of managing ITS32, direct (TAG = 00), indirect (TAG = 10) and defect (TAG = 11) descriptors, to access only segments of the EAPCB space. In addition the process has the possibility to generate in memory new pointers for the other modes and to transfer data from or to the other segments of the virtual memory

  using a special instruction called XMOVE.

  The mode 64 process mode is the equivalent of Mode 32 but adapted to the new DX memory domain and its 64-bit addressing. The list of instructions is close to that corresponding to Mode 32 but completed with new instructions concerning: - the activation test of the new 64-bit environment, - the test of the current operating mode, - the XMOVE operation, - the instructions corresponding to the new page and segment descriptors and the management of

memory allocation tables.

  To enable execution in Mode 64, the PCB process control block has a new format shown in Fig. 11 (Figs. 11 (1) and 11 (2)) and briefly described below. With respect to the address of the input byte to the PCB block (zero reference byte), the block includes memory areas reserved for measuring the execution times of the process (addresses -60 to 0); zones occupying bytes -60 to -17 being optional. Note that the numbers next to the memory locations specify the displacement in bytes relative to the zero reference location of the PCB control block. From byte 0 up to and including byte 15, four main process words PMW.0 to PMW.3 are stored in memory. The word PMW.0 occupies bytes 0 to 3 and has four one-byte fields each, a CAP capability field, a PRI priority field, an EXE process execution status field (for example, "pending "," ready ", etc.) and a DEXT execution field. The details concerning the contents of the four fields of the word PMW.0 are given in the

U.S. Patent 4,297,743.

  The PMW.1 process main word is stored in bytes 4 to 7. The STR status byte stores the STR status register of the system. The next byte (MBZ encoded) is set to zero. The following two-bit ES field indicates the execution mode of the process according to the value of its contents: ES = 00 Mode 32 ES = 01 Mode 32/64 ES = 10 Mode 64 ES = 11 Illegal PCB The contents of the ES field is may be modified by the software before executing a START command, thereby changing the execution mode of the process, or using

specialized instructions.

  The main PMW.2 process word is used to communicate additional information about the process state, while the word PMW.3 has two significant fields, the DCN field (bits 0 to 7) concerning the rights of the process to execute certain specific instructions and the CPSM field (bits 16 to 31) concerning a

  mask processors allowed to execute the process.

  The PCB block then comprises the two space words

  address ASW.O / 1 already presented (providing the address of the tables describing the STWA segment tables), then a sub-block consisting of bytes 24 to 51, significant for ES = 00 or 01 and consisting of the exception word EXW , of the SKW stack word storing the contents of the stack top register T used for the procedure calls, of the ICW word storing the contents of the instruction counter IC used to know the address of the instruction to be executed, of the word CSW storing the contents of the register CSR used to know the sequence number or the identification of the current address space EAC and to terminate the three stack base words SBW.1 to SBW.3. These words include the respective segmented addresses of the first bytes of the stack segments for the rings (0),

(1 and 2).

  Bytes 52 to 83 correspond to 8 words of a storage area of the ZMRB basic registers (insignificant in ES = 01 mode and ES = 10). These basic registers have a 32-bit format similar to that described for

  ITS32 descriptor with reference to FIG. 8.

  Bytes 84 to 147 correspond to 16 words of a storage area of the general registers ZMRG whereas bytes 148 to 179 correspond to 8 words of a zone of

  storage of ZMRS scientific registers.

  Bytes 180 to 255 correspond to a non-significant sub-block when ES = 00; the first word of this sub-block comprises a first field BREM of one byte used for the storage of the contents of a register BREM (mask of the extended basic registers) usable in Mode 32/64, ie ES = 01, and a second field set to zero MBZ. Bytes 184 through 247 correspond to the storage area of extended base registers EXZMRB (8 double words). These basic registers have 64-bit formats similar to the formats described for the ITS64 descriptors (TAG = 01 and TAG <> 01) with reference to FIGS. 4,6, and 10. The bytes 248 to 255 correspond to a main double word EXPMW.2 process. Bytes 256 to 303 are significant only in Mode 64 (ES = 10) and include an EXICW double word storing the contents of the extended instruction counter, an EXSKW double word storing the contents of the stack top extended T register. the three

  double words EXSCW.0 to EXSBW.2 and the double word EXEXW.

  Finally, the PCB block according to the new format has a zone of 8 words of exception report storage ZMRE (bytes 304 to 352), a zone (bytes 336 to 367) of four double words of address space ASDW.0. to ASDW.3 (see FIG. 7) for the 64K / 4MB type segments and a zone (bytes 368 to 399) of four ASDW.7 address space double words to ASDW.7 for the 4GB type segments. The Mode 32/64 process execution mode has been designed for better use of 64K / 4MB segments and to allow bridges between the two DL and DX memory domains, in particular to enable

  migration to 64-bit addressing.

  The 32/64 Mode uses the content of the BREM register which makes it possible to store in one byte the length of the eight ITS descriptors contained in the basic registers (1 bit BREMi per basic register BRi, with i ranging from 0 to 7). The value "0" of the contents of the bit BREMi indicates that the corresponding base register BRi contains an ITS descriptor of a format of 32 bits while the value "1" of the bit BREMi indicates that this same base register BRi contains a descriptor ITS in a 64-bit format. The basic register storage and download instructions use the BREM registry contents to decide which conversions (32-> 64) or (64-> 32) are possible. More specifically, if BREMi = 1, the basic register BRi comprises a 64-bit virtual address and the address development is done from the contents of the fields SHR, ASN, STN, STE and SRA. Conversely, if BREMi = 0, the basic register BRi comprises a 32-bit virtual address. If the TAG code contained in the register BRi is different from 01, then the address development is carried out on 32 bits; in the opposite case (TAG of BRi = 01), a dynamic extension of address format is carried out taking into account the contents of the SHR and ASN fields of the current space register CSR (the TAG field of the new descriptor

  ITS 64 bits thus obtained is automatically set to 00).

  In addition, certain address developments are made from the content of basic registers BR having a TAG code = 10. Two cases are possible: - a TAG code = 10 in a basic register BRi whose BREMi = 0 (32-bit address) corresponds to an ITS32 data descriptor of TAG = 00, - a TAG code = 10 in a descriptor of ITS data accessed in memory and associated with a BREMi = 0 must be suffixed by the contents of the CSR register when the contents of the original home registry that was used for the development

address has a TAG code = 01.

  Finally, when the TAG code of an ITS data descriptor moved in memory from a register whose BREMi = 0 (32-bit address) is different from 10 (or 11), then this descriptor is suffixed by the content of the CSR register if

its code TAG = 01.

  So a process running according to Mode 32/64 is

  capable of handling 32-bit and 64-bit addresses.

  To enable these address format changes and to move from a 32-bit environment to a 64-bit environment, two special instructions have been created: - The XLBD instruction loads two words (8 bytes) from the X address into the base register BRi and places the value 1 in the BREMi, - the instruction XSTB arranges the contents of the basic register BRi in two words (8 bytes) starting from the address X after an extension of the format from 32 to 64 bits if BREMi = 0

and if the code TAG = 01.

PROCEDURE CALL MECHANISMS

  In general, computer systems make extensive use of so-called procedure call operations whereby a process executing a procedure is able to call another APE procedure for execution and then return to the original APT procedure of resume his own execution. This concept of procedure call is very advantageous for the exploitation of modular programs. The Applicant has described in US Pat. No. 4,297,743 a method and a device using a stack memory structure well adapted to this type.

procedure call operation.

  A stack is a particular memory segment consisting of contiguous elements accessed by the LIFO system (last in, first out). A stack element is created at each procedure call and is used to store the information allowing the return to the calling process. We thus obtain in the stack a

call summary status.

  In the operating system, the location of the active stack element is kept in the base register BR0, while the next available location is kept

  in a special register T, or stack top register.

  In addition, the transmission of certain parameters is performed by a basic register chosen by the programmer. A procedure call begins with the execution of a PRSK instruction (stack preparation) which has the effect of saving the contents of the STR register in the stack and providing the programmer-user with the pointer of a zone that is susceptible to to receive the parameters and in which will be loaded the information to be transmitted to the called procedure. The call of the procedure is then completed by the execution of the instruction ENT (entry of the procedure) according to the following steps: - ring control (in case of need of change of ring, a sub-procedure of "door" is then executed), saving of the contents of the register of the instruction counter IC, - loading of the basic register BR0 (pointing to the parameters), - determination of the entry point of the procedure by a procedure descriptor of which the address is given in the instruction ENT, - loading a pointer designating the link data in a given base register, for example the register BR7, - entering the new procedure by loading the new ring number the where appropriate and the address of the entry point in the IC instruction counter register. An area of the current stack element, called ZT work area, is also available to the called procedure by storing local variables. The return is made by the EXIT instruction (procedure output), from the contents of the storage areas of the stack concerning the registers and the counter

IC instructions.

  For security reasons, there is provided a stack structure by ring number. For each stack the particular format of an element will depend on the execution mode of the calling process. Figure 12 illustrates schematically

  the format of a stack element used in 32/64 Mode.

  If we consider FIG. 12, the stack element according to the Mode 32/64 is constituted on a 32-bit width of three main zones: the work zone ZT, the zone for storing or saving information ZS (before the call of the new procedure) and the communication zone ZC (in which are stored the necessary information for the execution of the called procedure). These three areas are created by the PRSK instruction, the first byte of the ZC area is designated by the

basic register BR0.

  The first word of the zone ZS is constituted by the backup zone mask or SAM, which is as follows: a "format" field of 4 bits, in this case, of contents 0100, - a zone BR of 8 bits constituting a designation mask for the 8 basic registers BR0 to BR7 (with a view to their storage), - a 16-bit GR area constituting a designation mask for the 16 general registers GR0 to GR15, and a 4-bit SR area constituting a mask of

  designation for 4 scientific registers SR0 to SR3.

  The second word is reserved for the backup of the CSR register while the third word is reserved for the backup of the BREM register. Then comes the backup zone of the BRSA basic registers (2 words per register, with a reset of the second word when BREMi = 0), then the ORSA save zone of the other registers. The last-to-last word is used for the backup of the STR status register (1 byte) and the possible number of the partial memory extension in which the current procedure of the calling process was operating. Finally, the last word PTV of the ZS save area contains the previous value of the register T, the value of the register T at the beginning of

the PRSK instruction.

  The communication zone ZC whose input is given by the pointer contained in the basic register BR0 starts with the word PSA which contains the pointer of the word SAM. Next is the word ICC which contains the address of the instruction following the instruction ENT. In addition, the contents of the NBP field (number of bytes of the parameter area) of the PRSK instruction are stored in the NBP field of the stack element. The communication area ends with the PARAM parameter area whose end is bordered by the stack top byte T. The T-register is updated

  after each stack element creation.

  When executed in Mode 32, the stack format is similar to that previously described with reference to FIG. 12, with the following modifications: the content of the "format" field of the word SAM is set to 0000, the words CSR and BREM are eliminated, - the backup of the contents of the basic registers is

  performed on one word instead of two.

  When executed in Mode 64, the stack format is similar to that previously described about the 32/64 Mode with reference to FIG. 12, with the following modifications: the content of the "format" field of the word SAM is set to 1000, - the words CSR and BREM are eliminated, - the backup areas of the basic registers, the areas PTV, PSA and ICC have the dimension of a double word. Thus, the address of the first byte of the PARAM zone is obtained by a displacement of 20 bytes, starting from

  the address pointed by the content of the register BR0.

  Access to the various procedures implemented as part of the call mechanisms is achieved through procedure address descriptors called PD procedure descriptors. Of course, the formats of the procedural descriptors depend on the mode

execution of the process.

  If the execution is carried out in Mode 32 or in Mode 32/64, the format of the procedure descriptor, denominated PD32, is in conformity with that illustrated in FIG. 13. The first word M.0 comprises the field TAG (bits 0 and 1), the EPRN field (bits 3 and 4) is equivalent to the RING field (ring number) and the segmented address field (SEG, SRA) of the called procedure (bits 4 to 31) in cases where TAG < > 0. The SEG field makes it possible to identify a segment number and has the same meaning as the set of STN and STE fields of the descriptors of FIGS. 6 and 8. Similarly, the SRA field defines the displacement in the segment defined by SEG. Optionally, a second 32-bit word M.1 contains the EXPARAM extension parameters. More precisely: - for TAG = 00 (direct descriptor), the procedure descriptor is limited to one word and the segmented address corresponds to that of the entry point of the procedure; for TAG = 01 (extended descriptor), the descriptor comprises two words; the segmented address corresponds to that of the entry point of the procedure; moreover, the content of the second word is loaded into the basic register BR7 during the entry of the procedure; for TAG = 10 (CASD descriptor), the descriptor called CASD address space change descriptor

  presents the format shown in Figure 14.

  The first word M.0 of the CASD descriptor comprises in addition to the TAG field set at 10, an NXM field (bits 2 and 3) defining the execution mode of the called procedure and the PDA1 (SEG, SRA) field (bits 4 to 31) of the segmented address of the descriptor of the called procedure. The second word M.1 comprises a zone of 6 bits set to zero and an additional field PDA2 (SHR, ASN) (bits 38 to 63) of

  the segmented address of the called procedure descriptor.

  If the execution is carried out in Mode 64, the format of the procedure descriptor, denominated PD64, is in conformity with that illustrated in FIG. 15. The format presents at least two words (M.0 and M.1), and so optional two extension words (M.2 and M.3). The structure of the words M.0 and M.1 is similar to that already described for the ITS64 data descriptors in 64-bit addressing. In addition, the words M.2 and M.3 include parameters

extension EXPARAM1 / 2.

  - For TAG = 00 or (TAG = 01 and XTAG = 00) (direct descriptor) the dimension of the descriptor is two words and the address

  Segmented is the entry point of the procedure.

  - For TAG = 10 or (TAG = O1 and XTAG = 10) (extended descriptor), the dimension of the descriptor is four words, the segmented address is that of the entry point of the procedure and the content of the words M. 2 and M.3 is loaded

in the basic register BR7.

  - For TAG = 11 or (TAG = 01 and XTAG <> (00 or 10), there is a connection to exceptional procedures

provided by the system.

  In general, a procedure descriptor incorporated in an unprotected segment may be placed in any segment compatible with the addressing used and the method of execution of the method: in Mode 32, the procedure descriptor is placed in a 64K / 4MB space segment accessible by SHR and ASN equal to zero. It can also be placed in any segment of the 64K / 4MB (EAX) spaces, if it is referenced via a CASD descriptor itself located in a segment of the 64K / 4MB space accessible by SHR and

ASN equals zero.

  - in Mode 64, the procedure descriptor can be placed in any type of segment, as long as the process is authorized to access this segment, - in Mode 32/64, the procedure descriptor can be placed in any segment of the type 64K / 4MB or 4GB, if it is

  referenced by a 64-bit virtual address (BREMi = 1).

  It can be placed in any 64K / 4MB segment if it

  is referenced through a CASD descriptor.

  It can be directly referenced if the 64K / 4MB segment is accessible with SHR and ASN equal to zero, or

with the contents of the CSR register.

  Regardless of the mode of execution, the procedure call mechanism fulfills the following four main functions: a) Checking the access right, ie the caller's right (APT) to call the called party (APE) according to the respective ring values, b) Determination of the new ring number, c) Update of the battery and battery registers,

  d) Connection to the entry point of the procedure.

  In Mode 32 and Mode 32/64, the call and return mechanisms differ slightly depending on the need for an automatic change of mode of execution and / or the presence of a nonaccessible procedure descriptor

  directly by a 32-bit virtual address.

  For the rest of the presentation, the following definitions will be used: PCB Address Space (EAPCB): Set of segments directly accessible when the process is executed

in Mode 32.

  Current Address Space (EAC): The set of segments belonging to the EAX address space accessible through the contents of the CSR register. If the CSR register is zeroed, the EAPCB space and the current EAC address space represent the same set of segments. New address space (NEA): Set of segments belonging to the address space accessible by

  via the second word of a CASD descriptor.

  During the execution of a process, the invention provides three cases of dynamic change of execution mode during a procedure call and during the corresponding return. These cases called DYN1, DYN2 and DYN3 are respectively described with reference to FIGS. 18, 19 and 20. Previously, it is expedient to present the

  various formats of the IC instruction counter register.

  More particularly, FIG. 16 illustrates the format of the IC register corresponding to Mode 64 for TAG = 00. In this case, the format (consisting of a double word) is similar to that described for the 64K / 4MB / ITS64 descriptors (illustrated in FIG. 6) with equivalence between the RING field (shown in FIG. 6) and the PRN field (FIG. shown in Figure 16). For TAG = 10, the format of the IC register is similar to that described for the 4GB / ITS64 descriptors (shown in Figure 4). In Modes 32 and 32/64 the IC register consists of a single word whose format is similar to that described for the 64K / 4MB / ITS32 descriptors (illustrated in FIG. 8) with equivalence between the EAR field (shown in FIG. 8) and the PRN field of the IC register. In Mode 32 the TAG field is always equal to 00. On the other hand, in Mode 32/64 the TAG field can take the value 00 (the register IC contains the virtual address of the next instruction to be executed) or the value 01 (the instruction register content must be concatenated with the contents of the CSR register to form the virtual address of the

  next statement to execute).

  In general, a procedure call mechanism in a given address space EA, from an APT calling procedure to a procedure called APE, and using a PD procedure descriptor is performed according to the schema of the procedure. Figure 17. The use of a procedure descriptor in a calling mechanism makes it easy to perform the consistency checks necessary to ensure the integrity of the system. Moreover a software convention exploiting the mechanism of indirection makes it possible to have a static and dynamic resolution very powerful external references to the program to be executed (this indirection is marked on

  Figures 17 to 20 by the asterisk following the code ENT).

  For this purpose, the compiler groups the references to be solved in a table called the LKS link editing section. The procedure calls external to the CODE instruction code use an indirection to reach the PD descriptor of the procedure called APE. The advantages of this method are numerous: -It allows the independence of the code and references

external to the program.

  -It allows dynamic link publishing with code sharing using local search rules (each program must have a private link sub-section). -It allows dynamic link editing on machines with instruction cache memory without dump of

  the cache memory after resolution of the external reference.

  -Finally, the resolution of an external reference is made only once regardless of the number of uses

in the code.

  As a first approximation the compiler produces two objects. The first contains the CODE object-code (set of instructions to execute) and the second an LKS link-editing section that contains a word by external reference to resolve plus constants used by the code. In addition, an appendix table contains the symbolic names of the external references (for static or dynamic link editing). The LKS link editing section and the CODE code can be grouped into a single segment for segment saving reasons. Similarly, several compilation units can be grouped together. At execution, the instruction ENT (ENTER) will look for the displacement X with respect to the base BR7 or directly a descriptor of procedure PD if there is no indirection at this level (case illustrated in FIG. 17) or another descriptor of address if there is an indirection (for example in the cases illustrated in Figures 18, 19 and 20). The PD procedure descriptor is read after the access controls (privileges) to obtain the entry point address in the called procedure and

  the value to be stored in the basic register BR7.

  Thus, the procedure call mechanism involves both the PRSK and ENT instructions. The first PRSK instruction prepares the stack area that is used to save the context (set of instant contents of the registers assigned to the process) and passing parameters. This instruction has for argument a SAM mask designating the registers to be saved, the size of the parameters zone and the number of the register which will contain at the end of the instruction an address allowing to arrange the parameters in the reserved zone. The second instruction ENT performs the "control transfer", that is, the transition to a new instruction code sequence to be executed. Separating the preparation from the call of the call itself frees records for

  perform the sequence of passage of the parameters.

  It should be noted that the register pointing the context is the base register BR0 for the context of the calling procedure. This is the register cited in the PRSK statement for the new context until the execution of the ENT call statement. As the basic register BR0 is systematically saved, it is

  possible to trace the chain of calls.

  On return, the EXIT statement unpacks the context and resets the different registers with the saved values.

  Case No 1 (DYN1): from Mode 32 to Mode 32/64.

  Switching from 32 to 32/64 mode simply by inserting an address space change descriptor

  CASD on the path to the PD procedure descriptor.

  The two words of the CASD descriptor form a 64-bit address for reading the PD procedure descriptor. Since the resolution of the external references is done under the control of the operating system without changing the format of the LKS table or the procedure descriptor, the insertion of the CASD descriptor is completely transparent to the old programs. The second word of the CASD descriptor (same format as the CSR register) indicates which is the new NEA address space that will be activated as EAC space. The code or link editing section of the called procedure does not need to be in the EAC space. The fact of placing all or part of the space EAC depends on the use that one wants to make of the new possibilities offered by the invention (extension of the virtual space, absolute addressing, access to

the DX space).

  Thus, the dynamic change occurs during a call procedure (CALL), for example with the execution of an instruction ENT, in the case where the first descriptor leading to the procedure called APE is of type CASD. This access is performed as shown in Figure 18. The IC instruction counter register

  has a 32-bit format with the TAG field set to 00.

  The IC register points in the EAPCB space to the address of an ENT entry in the instruction code table (CODE table). The instruction ENT contains an address field called an address significant syllable of an indirection calling the base register BR7 (see US Patent 4,385,352 and US Patent 4,297,743). The development of the address syllable in combination with the content of the basic register BR7 points to an entry in the link table (LKS table) whose content makes it possible to point to the real procedure descriptor PD of the PD32 type located in the new NEA address space. The TAG field of the PD descriptor is set to the value 01, significant of a double word format, and the segmented addressing fields of the PD descriptor are loaded with the content of the corresponding fields of the CASD descriptor. Thus, the system will conventionally use the first word of the descriptor PD to determine in the CODE table of the new address space NEA the input of the instruction code of the procedure called APE and the second word of the descriptor PD to determine the input in the LKS link table and find the information

  necessary to perform the procedure called APE.

  In addition, the TAG field of the register IC is loaded into the field of bits 2 and 3 of the first word of the CASD descriptor which then becomes a direct descriptor (TAG = 00). Finally,

* Process execution mode goes into 32/64 Mode (ES = 01).

  When executing an EXIT return statement, the dynamic change to the 32/64 mode will occur with unstacking the ZS zone if the APT calling procedure was executable in this mode, ie if the field "format" (first 4 bits) of the SAM word of the stack element

corresponding is equal to 0100.

  Case N 2 (DYN2): from 32/64 Mode to 32/64 Mode (pseudo

  change). When a process is run in 32/64 Mode, the dynamic mode change mechanism is used to change the current EAC address space. In this case, the dynamic change mechanism remains close to

  that previously described; it is illustrated in Figure 19.

  The CASD descriptor is used to point the PD procedure descriptor in the new address space. In addition, the field TAG of the register IC is loaded into the field of bits 2 and 3 of the first word of the descriptor CASD. Finally, the CSR register is responsible for the content of the second word of the CASD descriptor (the previous content having been saved in the stack). Of course, the mode of execution of the process remains the Mode

32/64.

  Case 3 (DYN3): from 32/64 Mode to 32 Mode.

  When a process is run in 32/64 Mode, the

  dynamic change is allowed by the ENT instruction.

  This change occurs when the field of bits 2 and 3 of a CASD descriptor is equal to "10". The corresponding dynamic change mechanism is illustrated in

figure 20.

  Here again, the CASD descriptor is used to extract the PD procedure descriptor. In addition, the TAG field of the register IC is set to 00 and the register CSR is loaded with the content of the second word of the descriptor CASD (the previous content having been saved in the stack). Finally,

  Process execution mode changes to Mode 32.

  When executing the EXIT instruction, the dynamic change will occur according to the value of the first 4 bits

  the SAM word of the stack (0000 = Mode 32 or 0100 = Mode 32/64).

  Thus the dynamic change of execution mode gives a lot of flexibility to the user vis-à-vis

  existing programs written in a 32-bit format.

  These programs are likely to be localized (including code) in the 64-bit DX memory domain. They are also likely to call procedures and other programs and / or subroutines written in a 64-bit format and executable in 32/64 Mode. In this last mode of execution, programs are able to

  manage both types of 32 and 64 bit addressing.

  The invention is not limited to the only method described herein but also relates to a computer system comprising hardware and software means for implementing the above method presented in all its variants. The system according to the invention comprises the processor subsystem 100 structured around one or more CPU 106 central processors and a central memory

  MMU 102, each processor comprising micro-means

  programmed to perform the management of the main memory 102 and IOC input / output controllers 108 to the peripheral subsystem 104, in particular to mass storage means of sufficient capacity for virtual addressing, and software means , in particular a set of programs grouped under the name of operating system, to allow in association with the micro-programmed means the implementation of the method according to the invention. In a practical way, the specific operations described in the context of the invention are carried out by software and / or micro-programming and / or

logic circuits.

Claims (14)

  1. A method of operating the memory in a computer system of the virtual addressing type, characterized in that: - a first DX memory domain is organized around a logical addressing of NX bits dimension, defined in the DX memory domain a plurality of EAX addressing spaces of identical structure and allowing for relative addressing of dimension NL less than NX, - one temporarily and interchangeably affects one of the address spaces EAX (hereinafter called current address space EAC) to a second memory domain DL   organized around NL bit size addressing.   2. Method according to claim 1, characterized in that a first FX1 addressing format of size NX is constructed to access the EAX spaces by extension of a relative address format FL of dimension NL by means of a complementary zone containing at least one field intended to receive the identifier of the corresponding EAX space. 3. Method according to claim 2, characterized in that is stored in a reserved register (CSR register) the complementary area containing the identifier of the space current addressing EAC.   4. Method according to one of the preceding claims,   characterized in that the memory domain DL comprises an EAPCB permanent address space of identical structure to that of the EAX address spaces, the EAPCB space being detectable in the DX domain by an identifier of value equal to zero.   5. Method according to one of the preceding claims,   characterized in that the address spaces are of the segmented type, optionally in several dimensions   and / or sharable by several processes.   6. Method according to one of the preceding claims,   characterized in that in the memory domain DX a plurality of accessible segments is defined from a   another FX2 addressing format of NX dimension.   7. Method according to one of the preceding claims,   characterized in that the FX1 and FX2 formats incorporate an AA64 variant allowing direct absolute addressing physical memory.   8. Method according to one of the preceding claims,   characterized in that a mode of execution of the processes (Mode 32/64) supporting the two dimensions is defined NX and NL addressing.   9. Method according to claim 8, characterized in that one defines another mode of execution of processes (Mode 32) supporting the dimension of addressing NL, the two modes of execution of processes Mode 32 and Mode 32 / 64 being switchable from one to the other, either automatically by   Dynamic change is by programming.   10. Method according to one of the preceding claims,   characterized in that: - for address spaces of NL dimension, EAX spaces and, where appropriate, the EAPCB space, PD procedure descriptors of identical basic structure are selected, - descriptors of space change are defined of addressing (hereinafter referred to as CASD), of basic structure identical to that of PD procedure descriptors, - it is possible, from an executable process in a given address space, to call a procedure APE executable in another address space, by   through a CASD type descriptor.   11. Method according to claim 10, characterized in that the CASD type descriptors comprise a field intended to receive the identifier of the address space containing the procedure called APE and the pointer of the procedure called in this new space. NEA addressing.   The method according to claim 9 taken in combination with claim 11, characterized in that the automatic switching is performed dynamically on a procedure call by identifying in a procedure descriptor the typical code-type of a CASD descriptor.   13. Method according to one of the preceding claims of   type in which a process uses for the execution of basic instructions of the address registers called basic registers BR, characterized in that: - two sets of basic registers of dimension NL and NX are defined, one organizes in a zone memory BREM a mask whose content of each bit BREMi is representative of the NL and NX dimension of the address loaded or extracted from the corresponding register BRi, - it is verified during the address movements the compatibility of the address loaded or extracted with the content of the corresponding BREMi dimension bit and, if necessary, an automatic address reduction or extension is carried out with a change as a result of the   corresponding BREMi dimension bit.   14. Computer system for implementing the memory addressing method of the virtual addressing type   according to one of the preceding claims, characterized in   that the computer system comprises a processor subsystem 100 structured around one or more CPU 106 central processors and a central memory MMU   102, each processor comprising micro-means   programmed to perform the management of the central memory and IOC input / output controllers 108 to the peripheral subsystem 104, in particular to mass memory means of sufficient capacity for virtual addressing, and software means, including a set of programs grouped under the name of operating system, to allow in association with said micro-programmed means the implementation of the   Method according to one of the preceding claims.