FR2635607A1 - INTERNAL METHOD FOR PROGRAMMING AUTOMATIC CONTROL AND REDUNDANCY FOR MEMORY CIRCUITS AND APPARATUS FOR APPLYING THE METHOD - Google Patents

Abstract

An internal programming is carried out of redundancy bit decoders or of redundancy word decoders 7 which contain associative memory cells which can be reset to zero and which are associated with the redundancy bit lines 2.4 or with the redundancy word lines. 2.5, in that, for the programming of the redundancy, a redundancy validity FF 34 is placed; 44 reset at the start of automatic control, the positive termination of the automatic control process is ensured by releasing the locked control inputs RAS; CAS; WE; A0 ... A9; DIN; DOUT and, where appropriate, by a signal sent to an output pin MR and in that, in the case of a memory array 2 having no errors, an irreversible memory element can be programmed.

Description

The present invention relates to an internal programming method

automatic control and

  redundancy for memory circuits with maximum integration

  male. It is used for automatic programming of the redundancy of faulty memory circuits during

  memory implementation or in response to an incentive

external tion.

  For the reduction of the duration of the verification of the control devices, various methods are known, apart from the known m-bit control mode. A document from the IEEE-International Test Conference of 1987 describes a parallel test process which is carried out

  on the control device on the basis of inter-

  nes additional. It allows a reduction of the time of

  proportional control to N 1/2, which, in case of

  increase in the integration rate, implies a significant reduction, compared to known control methods, of the time required for control. It is also possible to reduce the duration of external verification by carrying out a complete internal control of the memory circuit by means of an internal processor with automatic control. The principle of the method is exposed in IEEE - International Test Conference 1987, p. 45, where the error addresses of the memory circuit are indicated and where internal redundancy programming is carried out

  by means of irreversible programmable memory elements

  wheat. The drawback of programming such irreversible memory elements is the fact that the operating conditions in the event of high voltages or high currents are not typical and that additional technological operations are required to

the use of EEPROM cells.

  The object of the invention is to develop an internal method for programming automatic control.

  and redundancy for memory circuits and a device

  tif for the application of the process which require only the necessary technology to manufacture the memory circuit and which, when programming lines

  redundant, do not give operating conditions

not typical.

  This object is achieved, according to the invention, because the internal automatic control processor checks, from the start of operation, the memory circuit and that the defective lines are replaced by redundant lines by means of cells.

  static memory programmed accordingly.

  The invention relates to an internal method of automatic control programming and redundancy for memory circuits, in which the internal method

  control system is started after application

  cation of the operating voltage and obtaining internal stability. After switching on, the external control inputs, the addresses as well as the data inputs and outputs of the memory circuit A are locked. Then, an internal automatic control processor necessary for the application of the method, is subjected to an internal control. Then, the data paths of the memory circuit are checked and finally the matrix and the memory cells are subjected to a check. During these operations, the error addresses are recorded and stored in a memory.

  recording bank of the automatic control processor

  tick, and the distribution of error addresses gives the

  optimal redundancy structure. When the program-

  tion of the redundancy has been made, the bit lines of

  redundancy or words are subject to automatic control

tick.

  According to the invention, the determined redundancy structure implements an internal programming of

  redundant bit or word decoders that contain

  Associative memory cells which can be reset. After the memory circuit is again switched off, these associative memory cells lose their information and are programmed again each time they are switched back on. The redundancy bit or word decoders are associated, in a known manner, with the lines of the redundancy bits, or of words. In addition, in redundancy programming, a redundancy validity FF associated with the redundancy bit decoder or corresponding words is introduced, at the time of recording of the errors, in the associative memory cells and is reset to zero at time of the start of the implementation of the process. According to the automatic control process, the positive cessation of the automatic control process is indicated by a signal applied to an output pin and / or by the release of control inputs, addresses and locked data inputs and outputs. When the memory array has no errors, an irreversible memory element is programmed if necessary. This makes it possible to block the automatic control when the memory circuit is switched on, since there is no longer any need for redundancy programming in this case. It is therefore possible to select case types for a stake

in fast operation.

  The device allowing the application of the method consists of a memory circuit comprising a matrix, sensor amplifiers, bit and word decoders, control logic and data input and output stages. The matrix contains decoders of redundancy bits or of words associated with

  lines of redundancy bits or words in a layout

  usual tion. In addition, the memory circuit contains an automatic control processor and processing and operating logic. The processor

  automatic control contains a firmware memory

  mes, control logic, firmware order counter, arithmetic logic unit (ULA), recording bank and bus drive stage

to three states.

  The registration bank comprises, with a number of registers which corresponds to the number of redundancy lines and at the rate of four lines of the redundancy bits or words per register, 2 (Rx. Ry) = 32 registers. The processing and start-up logic contains an automatic control state multiplexer and a start-up logic circuit which are connected to the periphery via a pin

Release.

  According to the invention, the processor control logic is connected to the control signal register via a control signal bus which conducts the address signals to be replaced. The control signal register is linked, via a column or line control signal bus,

  to redundancy bit or word decoders.

  The redundancy bit or word decoder contains associative memory cells according to the number of address lines that are necessary according to

the form of organization.

  Each associative memory cell contains an sRAM cell and a comparator which is controlled by the sRAM cell and by the address signals on the

  address lines and which is connected to a selection line

  redundancy common to all associative memory cells of a redundancy bit decoder

or words.

  Each redundancy bit or word decoder is associated with a write signal decoder which is controlled by a corresponding signal bus.

  control by columns and rows and including the writing line

  The output ture is connected to the gates of the sRAM cell selection transistors in the associative memory cells. In addition, each redundancy bit or word decoder is associated with a redundancy validity flip-flop (FF), the reset input of which is linked to a control line in the column or row control signal bus. and whose entry of

  positioning is connected to the writing line.

  This FF assumes the role of a main fuse and the associative memory cells assume the role of traditionally programmed redundancy address fuses. The output of the redundancy validity FF is connected to a transistor which is inserted between the redundancy selection line and the ground

  and which, in the state set back from the FF, constantly maintains

  the redundancy selection line is inactive.

  In addition, the processing and operating logic contains an open drain transistor controlled by the state multiplexer, a trigger type flip-flop with reset signal for the external start-up of the automatic control process and, the case

  if necessary, other means of programming.

  In one embodiment of the invention, the state multiplexer is connected via a control line to a programming circuit which, on the side of its output, is connected by a control line to an element of irreversible memory. In this system, the memory element is, on the output side, connected to the start-up logic circuit. It is programmed for a non-defective matrix, that is to say when it is not necessary to switch on lines of redundancy bits or words. Therefore, memory circuits

  are selected for quick action. The avan-

  This consists, apart from the reduction of the duration of the check, in that it is also possible to repair long-term bit errors, since each setting

  circuit is accompanied by programming.

  Various other features of the invention

  moreover emerge from the detailed description which

follows.

  An embodiment of the object of the invention

  tion is shown, by way of nonlimiting example, at

attached drawing.

  Fig. 1 is a block diagram of a circuit 1 MdRAM comprising an automatic control processor for the application of the control programming method

automatic and redundancy.

  Fig. 2 represents the block diagram of the circuit of the

  automatic control processor.

  Fig. 3 represents the block diagram of the logic circuit for processing and starting the processor

automatic control.

  Fig. 4 shows a redundancy bit decoder. Fig. 5 shows a redundancy word decoder.

  Fig. 6 schematically represents the course

ment of the process.

  The memory circuit 1 shown in FIG. 1 consists of the following blocks, which are connected in a known manner inside the dRAM. A memory array 2, comprising bit lines 2.1 and word lines 2.2 as well as memory cells 2.3 at the points of intersection, contains four lines 2.4 of redundancy bits and four lines 2.5 of redundancy words.

  The matrix 2 which can be organized under different

  annuities, is associated with sensor amplifiers 3, a bit decoder 4 and a word decoder 5 as well as a redundancy bit decoder 6 and a redundancy word decoder 7. A control logic 8 with external control signals RAS, CAS, WE and address signals A0 ... A9 is connected, via a CASB bus A column addresses to bit decoders 4 and bit decoders of redundancy 6 and, via a RASB bus of line addresses, to the word decoders 5 and to the redundancy word decoders 7. A data input stage 9 and a data output stage 10 are linked, via an internal IDAB data bus,

to the sensor amplifiers 3.

  The order process in dRAM is

  provided by known command lines not shown

  tees. Furthermore, the memory circuit 1 comprises a processor 11 for automatic control and a logic 12 for processing and starting up the processor 11l for automatic control which, together with the redundancy bit decoders 6, the word decoders of redundancy 7, redundant bit lines 2.4 and 2.5 lines

  of redundancy words, constitute the necessary device

  to apply the process.

  Fig. 2 schematically represents the process

sor 11 of automatic control.

  The automatic control processor 11 comprises a memory 13 with firmware, a logic 14 for controlling the processor, which is connected to the memory 13

  microprograms and a 15 order counter for micro-

  programs as well as a ULA 16 comprising a 10-bit word width which is connected, via an ARB bus with a 10-bit wide ULA register, to a recording bank 17 constituted by 32 registers 17.0 ... 17.31 at 10 bits each. In this system, the outputs of registers 17.29 ... 17.31 are connected to a three-stage bus stage 18 for the row and column address bus and the RASB, CASB, IDAB data bus. Furthermore, the automatic control processor 11 includes a control signal register 19 which is connected, via a PRST bus of control signals to the processor control logic 14. Furthermore, the control signal register 19 is connected via a column control bus PRSTC to redundancy bit decoders 6 and, via a control signal bus PRSTR via lines, to decoders 7 of redundancy words. The processor control logic 14 is connected, via a command line bus BIZ, to the processing and control logic 12 of the

  11 automatic control processor.

  Via the command line EXE, the processor control logic 14 is connected to the control logic 8 for locking the external control signals =, A-, WE and address signals

A0 ... A9.

  Fig. 3 represents the processing logic 12

  and controlling the automatic control processor 11.

  This logic comprises an automatic control state multiplexer 20 which is connected to the automatic control processor 11 by the command line bus BIZ and to the control logic 8 via a

DSTB command line bus.

  The state multiplexer 20 is located at the gate of an open drain transistor 21, the drain of which is connected to an output pin MR and to a flip-flop of the type

  trigger 22 of reset signals.

  The reset signal trigger output

  started externally is connected, via

  diary of a BIRST command line, to a logic start-up circuit 23 and causes an external start-up of the automatic control process. Furthermore, the state multiplexer 20 is connected, via

  from a PREN command line to a programming circuit

  tion 24 which is itself connected, via a

  IPRST command line, to an irreverent memory element-

sible 25.

  The memory element 25 is, on the output side, connected by a command line BISTE and the DSTB bus of command line is connected by a command line POST to the logic starting circuit 23 which, on the output side, is connected by a BIS command line to the BIZ command line bus. As shown in fig. 4,

  each of the redundancy bit decoders 6 is made up of

  killed by nine associative memory cells 30.0 ...

  30.8. Each of these associative memory cells 30.n contains an sRAM cell 31 comprising four transistors 31.1 ... 31.4 which constitute a memory FF and two selection transistors 31.5, 31.6 for writing information in the cell sRAM 31. The selection transistors 31.5, 31.6 are interposed between the corresponding address line An CAS; Year. CAS and the corresponding output Q; SRAM 31 cell Q and their

  doors are connected to a writing line WRR.

  In addition, each memory cell associates

  tive 30.n contains a comparator 32 which enters a RAL redundancy selection line associated with all of the associative memory cells 30.0.

  30.8 and the mass, .. DTD: comprises two circuits in series with each two transis-

  tors nMOS 32.1 ... 32.4. Their doors are triggered by A.n CAS address lines; A.n CAS as well as by

Q outputs; Q of the sRAM cell 31.

  A write signal decoder 33, to which the column control signal bus PRSTC is directly connected, leads, to the output, the corresponding write line WRR. A redundancy validity FF 34 consisting of four transistors 34.1 ... 34.4 contains, between the outputs P; Pet the mass M, two transistors 34.5; 34.6, the transistor 34.5 being directly connected to the control line BHES of the PRSTC signal bus

  control by columns and transistor 34.6 being direct

  connected to the WRR writing line.

  A transistor 34.7, to which the output P is directly connected, is interposed between the redundancy selection line RAL and the ground M. A pMOS transistor 35.1 controlled by the output P and a precharge transistor 35.2 controlled by the precharge clock TBV are inserted between the operating voltage Ucc and the RAL line for selection of redundant DC. the RAL redundancy selection line and an internal control clock dRAM constitute the inputs of an AND gate 36 comprising the RBL as an output

  of redundancy bit line selection signals.

  Furthermore, the redundancy selection line RAL is connected to a negator 37 whose output conducts the deselection control signal DEBL for the decoders of

bits 4 of memory array 2.

  Fig. 5 represents a redundancy word decoder 7 which contains 8 associative memory cells 40.0 ... 40.7 constituted by an sRAM cell 41 and by a comparator 42. This structure corresponds to that of

6 redundancy bit decoder.

  A write signal decoder 43, which is directly connected to the line control signal bus PRSTR, leads, from the output side, to the corresponding write line WRR. A redundancy validity FF 44 comprising the transistors 44.1 ... 44.7 is controlled by the command line BRES of the line control signal bus PRSTR and by the write line WRR and in turn controls the transistor 44.7 which is interspersed

  between the corresponding RAL redundancy selection line

  dantes and the mass M. A NAND gate 45.1 controlled by the line of

  TSWL command and by the RAL line for selection of redundancy

  dance controls a post-charge transistor 45.2 which is interposed between the supply voltage Ucc and the redundancy selection pipe RAL, and a negator 45.3 whose output guides the deselection control signal DEWL for the word decoder 5 of the

memory array 2.

  Furthermore, the device comprises, inserted between the supply voltage Ucc and the line RAL for selecting the redundancies, a pROS transistor 46.1, which is controlled by the redundancy validity FF 44, and a precharge transistor 46.2 controlled by a clock

TWV preload.

  The RAL redundancy selection line is connected by a negator 47 to a negator 48 and by the gate of a drive transistor 49.1 between the output and the ground. The negator 48 is connected, by a barrier transistor 50 controlled by a Ucc, to the gate of a second drive transistor 49.2 between the supply voltage Ucc and the output, the output conducting the

  RWL signal for selection of redundancy word lines.

  Fig. 6 schematically represents the course

  ment of the process. At the time of applying the voltage

  supply unit Ucc, the control unit 8 gives, -

  when internal stability is reached, through

  median of the command line POST of the command line DSTB bus, the release signal to apply

  the values processed and the start-up logic 12.

  The memory circuit 1, which is not yet in action, signals this state at the periphery via the command line bus BIZ, the state multiplexer 20,

  of transistor 21 and of output pin MR.

  The activated control signal BIS starts the process stored in memory as firmware. First, through the EXE command line

  and by activating all external control signals

  nes RAS, CAS, WE, address signals AO ... A9 and

  DIN and DOUT data inputs and outputs are locked

  lées. The connection with the RASE bus, CASB of addresses by lines and by columns and with the IDAB data bus is established exclusively for the automatic control processor 11. The first part of the automatic control consists of the control of the automatic control processor 11 which itself consists of the formation of checksums for the memory 13 with firmware, the control of the ULA 16, the control of the bank 17 and the control of the processor control logic 14. These controls

  involve the intervention of a firmware, that is

  that is to say the modification of the counter 15 of firmware orders by the processor control logic,

  the sending of a micro-order in the memory 13 of micro-

  programs by the order counter 15, the processing of the order value read by the processor control logic 13, the sending of the resulting control signals to P'ULA 16 and to the recording bank 17 , and the preparation of the following micro-order by a new one

  modification of the order counter 15.

  During the next stage of the process, the deco-

  bit and word daters 4, 5 are controlled by means of

  internal read and write cycles through

  CASB bus median; RASB of addresses by columns and

IDAB data lines and bus.

  When these process operations have ended

  Born with success, the next stage of the process consists in controlling the read and write cycles of the memory array 2 and in recording and storing the addresses of bit errors in the bank.

  17 of the processor 11 of the automatic control

  tick. Due to the typical internal organization of a dRAMS, several memory cells are read or written simultaneously via the internal data bus. The control is carried out by means of a common known memory control algorithm, Corsican for example

Marching type control.

  If this matrix control does not highlight

  no bit error, this state is reported via

  medium of the command line BIZ bus, multi

  state plexer 20 which, via the signal line PREN which is now activated, switches on the programming circuit 24, which brings back A

  zero irreversible memory element 29 via

  IPR command line. In the event of a new start-up, which can be carried out via the output pin MR and the reset signal trigger (BIRST command line), the new start-up is blocked by the intermediary from the BISTE command line. As a result, these memory circuits 1 can be selected for special applications since switching on does not trigger any automatic control, for example for immediate start-ups.

  In the next stage of the process, the use

  optimal position of the redundant parts of the matrix 2 is determined by the calculation for a given error scheme and the addresses determined by the calculation are

  applied, via the CASB bus, RASB from a-

  dresses by columns and rows, with bit decoders and

  redundancy words 6; 7 and registered through

  PRSTC bus median; PRSTR of control signals by columns and lines, to the corresponding associative memory cells 30.n; 40.n. In addition, the corresponding WRR write line is activated and the selection transistors 31.5; 31.6 or 41.5; 41.6 cells from

  associative memory 30.n, 40.n selected are open

  your. As a result, the error addresses that are asso-

  listed directly at the corresponding address lines A.n CAS; A.n CAS or A.n RAS; A.n RAS are registered in cell sRAM 31; 41. Furthermore, during redundancy programming, the redundancy validity FF 34; 44 reduced to zero at the start of the process or at the time of a new start-up, by the BRES command line is reduced to the initial value by the

transistors 34.6; 44.6.

  Therefore, the transistor 34.7, 44.7 is closed and the RAL redundancy selection line can take an active high potential. The inscription of all the addresses of errors entails the replacement of the defective lines by lines 2.4; 2.5 bits and words

redundancy.

  During the next stage of the process, the programmed lines 2.4; 2.5 bits and redundancy words

  are also checked according to the con-

  trôl81e. In case, when errors have been highlighted, there are still lines 2.4; 2.5 of bits and redundancy words which are free, they are

  selected and subject to control.

  In the event of non-repaired errors

  bles, the memory circuit remains in an inactive state while, when the method does not give rise to errors, the automatic control processor resets the state multiplexer 20 via the bus BIZ of control lines, so that the open drain transistor 21 is closed again and the signal applied to the output pin MR for a voltage

  applied externally becomes active.

Claims (3)

  1. Internal method of automatic control and redundancy for memory circuits, in which, after application of the operating voltage and obtaining internal stability, the automatic control method recorded and stored internally is   activated, the external control inputs and the addresses   its as well as the data inputs and outputs of the memory circuit being locked, an automatic control processor used then being subjected to an internal control, the data circuits of the memory circuit being controlled and the matrix and the memory cells being then checked for error addresses   then being recorded in a bank of registers   of the automatic control processor and the optimal redundancy structure being determined from   the distribution of error addresses for the possibilities   repair tees and, afterwards, the redundancy bit lines or word lines being subjected to automatic control, characterized in that, taking into account the determined redundancy structure, a   internal programming of redundant bit decoders (6)   dance or redundancy word decoders (7) which contain resettable associative memory cells (30) and which are associated with redundancy bit lines (2.4) or redundancy word lines (2.5), in that, for redundancy programming, a redundancy validity FF (34; 44) is set to zero at the start of the automatic control, the positive control process is positively terminated by the release of the control inputs locked (RAS; CAS; WE; AO ... A9; DIN; DOUT) and, if necessary, by a signal sent to an output pin (MR) and in that, in the case of a matrix of   memory (2) with no errors, you can program   sea an irreversible memory element (25).   2. Device for applying the automatic control and redundancy programming method according to claim 1, this device consisting of a memory circuit comprising a matrix, sensor amplifiers, bit and word decoders, logic control, information input and output stages, the matrix containing bit lines or redundancy words and bit decoders   or corresponding words, the memory circuit   also providing an automatic control processor as well as a processing and start-up logic, the automatic control processor containing a firmware memory, a control logic, a counter of firmware orders, a unit of   arithmetic logic processing, a record bank   with a corresponding number of registers   the number of redundancy lines and a drive floor   bus with three states, the processing and start-up logic containing an automatic control state multiplexer and a start-up logic circuit which are connected to the periphery, characterized in that the logic (14) of processor control (14) is connected, via a PRST control signal bus, which carries the address signals to be replaced, to a control signal register (19), in that the control register control signals (19) is connected, via a bus (PRSTC; PRSTR) of control signals by columns and lines, to bit or redundancy word decoders (6; 7), in that the bit or word decoders (6; 7) contain cells (30.n; 40.n) of associative memory each constituted by an sRAM cell (31) and by a comparator (32) according to the number of lines of addresses (An; An) imposed by the form of organization, and in that at each decoder (6; 7) of bits or of redo words ndance is associated with a decoder (33; 43) of write signals controlled by the corresponding bus (PRSTC; PRSTR) of control signals by columns or by lines, the write line (WRR) located on the output side is connected to the gates of selection transistors (31.5 ; 31.6) or (41.5; 41.6) in the associative memory cells (30.n; 40, n), in that with each decoder of bits or redundancy words (6; 7) is associated a validity FF redundancy (34; 44) whose reset input is connected to a control line (BRES) in the bus (PRSTC; PRSTR) of control signals by columns and lines, whose positioning input is connected to the write line (WRR) and the output (P) of which is applied to the gate of a transistor inserted between a   redundancy selection line (RAL) known by it-   even in redundant bit and word decoders   (6; 7) and mass (M), in that the processing logic   ment and start-up contains an open drain transistor (21) controlled by the state multiplexer (20) and a trigger type flip-flop (22) of reset signals   zero and, where appropriate, other means of programming tion.   3. Device according to claim 2, character-   in that the state multiplexer (20) is connected, via a control line (PREN), to a programming circuit (24) which, on the output side, is connected, via from a command line (IPRST), to an irreversible memory element (25), and in that the irreversible memory element (25) is, from the   output side, connected to a start-up logic (12).