FR2633467A1 - FREQUENCY MULTIPLIER WITH PROGRAMMABLE MULTIPLICATION RANK - Google Patents

Abstract

This frequency multiplier circuit with variable multiplication rank is of the type comprising a comb generator 1 receiving at input a signal at the base frequency fe to be multiplied and delivering at output a composite pulse signal A comprising a plurality of harmonic lines of the frequency base, this comb generator being followed by a bandpass filter 2 selectively tunable on one N.fe of these harmonic lines. According to the invention, the comb generator 1 is formed by logic means having two complemented outputs Q, Q /, a synchronous input H whose activation controls the passage of these outputs from one logic state to another, and an asynchronous input R whose activation controls, independently of the state of the asychronous input, the passage of these outputs to states complementary to those which are generated by activation of the synchronous input; the signal at the base frequency is biased beforehand so that its excursion takes place around the transition voltage controlling the passage from one logic state to another, this signal being applied to the synchronous input of the logic means; and a first output Q of these means is connected to the asynchronous input R and the second output Q / delivers said composite pulse signal to the band-pass filter situated downstream.

Description

Programmable Multiplication Frequency Multiplier The

  The present invention relates to a frequency multiplier circuit for

rank of variable multiplication.

  The invention applies in particular, but without limitation, to the generation of signals by frequency synthesis, which is commonly used

  used in radars and telecommunication systems.

  Indeed, the frequency multiplication is one of the fundamental operations of the frequency synthesis, and it is advantageous to use for this purpose a frequency multiplier whose multiplication rank is variable either by a mechanical or analog control, or by a numerical control (then we speak of rank of

programmable multiplication).

  Many frequency multiplication circuits are known which are based on the production of energy distributed over harmonics

  a base frequency applied as input to the multiplier.

  When seeking a multiplication at high rank (that is to say greater than five) and / or variable or programmable, generally uses a circuit of the type illustrated in FIG. 1, essentially comprising a comb generator 1 associated with a pass filter. -gang

tunable 2.

  The signal at the base frequency fe applied at the input of the comb generator is deformed by the nonlinear transfer characteristic thereof into a time wave having the shape represented in A, and whose frequency image, represented in B , is a comb spectrum comprising a large number of harmonics of the frequency of

base fe.

  This signal A, B is applied to a tunable bandpass filter 2 which selects only the harmonic line of rank N (illustrated in B '), ie corresponding to the frequency N.fe, and it alone (if the surrounding parasitic lines are ignored because the filter response never shows perfectly abrupt sides); the time wave

  corresponding is represented in A '.

  For the comb generator 1, a "snap-off" diode has been used up to now, a component which is well known for its microwave applications, the very abrupt switching reaction of the direct direction in reverse direction allowing the generation of high order harmonics with a relatively high energy level

  constant over a wide range of harmonic frequencies.

2 2633467

  Nevertheless, this arrangement has certain drawbacks, inherent to the properties of the snap-off diodes, in particular the low efficiency, the noise of

  high intrinsic phase and sensitivity to charge and environment.

  To limit these disadvantages, it is necessary to provide a high attack power input comb generator, and an isolation stage between the comb generator 1 and the bandpass filter 2 to prevent the characteristics of the comb. impedance of it do not come

  disrupt the operation of the comb generator.

  One of the aims of the present invention is to propose a circuit which overcomes these drawbacks, and makes it possible to constitute a frequency multiplier that is simple to design and economical to produce, operating with excellent efficiency (thus saving the power of an input stage of the comb generator input), allowing a direct coupling between the comb generator and the selective filter, and capable of outputting a multiplied frequency signal closely correlated to the input signal at the base frequency , including a phase noise

intrinsically very weak.

  Another object of the invention is the production of such a circuit 23 operating in a very wide frequency range, typically between 100 kHz and 1 GHz, while maintaining a substantially constant amplitude of the harmonic lines over the entire frequency range.

used ("agile band").

  Another object of the present invention is to make this frequency multiplier programmable, that is to say to allow the multiplication rank to be chosen by a logic type command, for example

  a digital word applied to the circuit.

  For this purpose, the invention proposes a frequency multiplier circuit of the general type indicated above, that is to say having a comb generator receiving as input a signal at the base frequency to be multiplied and outputting a signal composite pulse having a plurality of harmonic lines of the base frequency, said comb generator being followed by a bandpass filter tunable selectively on

one of these harmonic lines.

  According to the invention: the comb generator is formed by logic means having two complemented outputs, a synchronous input whose activation controls the passage of these outputs from one logic state to the other, and an asynchronous input of which the control activation, regardless of the state of the synchronous input, the transition of these outputs to states complementary to those generated by activation of the synchronous input; the signal at the base frequency is previously biased so that its excursion takes place around the transition voltage controlling the transition from one logic state to another, this signal being applied to the synchronous input of the logic means; and a first output of these means is connected to the asynchronous input and the second output delivers to the bandpass filter located downstream said composite pulse signal. According to a number of advantageous features of the invention: the asynchronous input is connected to said first output of the logic means with the interposition of a time constant element, so as to lengthen the duration of the pulse signal to the optimum composite delivered on said second output of the logic means; said logic means are flip-flop means, the synchronous input being constituted by the clock input and the asynchronous input being constituted by the resetting input; these rocker means may in particular comprise a D-type flip-flop whose input D is brought to the high logic level; the band-pass filter is a digitally controlled filter, so as to make programmable the multiplication rank of the circuit; and an amplitude limiter is provided at the output of the bandpass filter making it possible essentially to keep the signal at the output of the bandpass filter only the phase modulation of this signal,

  reducing to a minimum its amplitude modulation.

  Other features and advantages of the invention will appear in the

  reading the detailed description below of various forms of

  embodiment, with reference to the accompanying drawings in which: - Figure 1, above, shows the general structure, in itself known, a frequency multiplier circuit operating from a comb generator, - Figure 2 is 1, for the circuit of the present invention; FIG. 3 shows the respective chronagrams of the input and output signals of the comb generator of the circuit of FIG. 2; FIG. 4 shows an example of a pass filter. FIG. 5 shows another example of a programmable bandpass filter that can be used in the circuit of FIG. 2; FIG. 6 is a variant of the circuit of FIG. 2, with a

  number of advantageous modifications.

  FIG. 2 shows the general circuit diagram of the circuit of the present invention, in which, as in FIG.

  comb I produces signals applied to an adjustable bandpass filter 2.

  In a characteristic manner of the present invention, the generator of

4 2633467

  comb 1, instead of consisting of an analog component having a non-linear transfer characteristic (typically a snap-off diode) as in the prior art, consists of a logic latch circuit whose sudden changeover , caused, allows to generate harmonics of high rank. For this purpose, it is possible to use for this purpose, as illustrated in FIG. 2, a D-type flip-flop whose clock input H (input controlling the tilting) receives the signal at the base frequency fe via a decoupling capacitor 3. This signal is biased, via a resistor divider bridge 4 and 5, to a voltage close to the transition voltage of the flip-flop, so that the excursion of this signal is around this transition voltage. . The waveform of the signal at the base frequency fe is not critical (except for the phase noise, which is better for a square signal), this signal being sinusoidal as well, as shown on the top timeline

  of Figure 3, that square, triangular, ...

  The D input of the flip-flop is raised to the high level, so that the flip-flop is controlled by only one logical command, namely the signal applied to the clock input H. The complemented output Q / constitutes the output of the comb generator, while the uncomplemented output Q is looped on the input R of

  resetting by a direct link 6.

  We will now describe the operation of this comb generator, namely how, receiving at its input the signal fe, the flip-flop will generate on the output Q / fine pulse, represented on the

chronogram at the bottom of Figure 3.

  The active transition of the signal on the clock input to the frequency fe switches - synchronously - the output Q to the same logic state as that present on the input D, that is to say in the logical state high since this input is permanently connected to the DC supply voltage, after a time ti corresponding to the intrinsic delay time of the flip-flop. The high level thus obtained on the output Q will activate - asynchronously - the reset input R, thus forcing the output Q to the state complementary to that of the input D, thus in the low state, after one

  time t2 related to the response time of the circuits used for the flip-flop.

  The signal Q /, complementary to the signal Q, will therefore have the appearance indicated on the bottom timing diagram of FIG.

  being generated during the aforementioned period t2.

  This pulse is generated at the same frequency fe as the base signal applied to the input H but has, because of its pulse aspect, a very rich harmonic spectrum, with an amplitude of the successive lines whose envelope is substantially sinus. x / x, that is to say comparable to what would be obtained with a comb type generator to

2633467

  diode snap-off, so that it is possible to obtain an energy level

  relatively constant over a wide range of harmonic lines.

  However, unlike the snap-off diode arrangement, it is found that the phase noise of the resulting spectrum is very low and furthermore the energy efficiency of the flip comb generator is very high, so that It is not necessary to provide, as in the prior art, driving circuit upstream of the comb generator, which circuit constituted

  itself an additional source of parasitic phase noise.

  Furthermore, since the comb generator is a logic circuit, the signal at the output Q / is totally independent of the load present at this terminal of the logic circuit, so that the output Q / of the output can be connected directly. the flip-flop at the inlet E of the filter, without the isolation stage which was necessary in the prior art, a stage which, besides its cost and the complexity of design that it implies, constituted an additional source of degradation of the quality of the signal delivered by the

comb generator.

  The duration t2 during which the pulse is produced is related to the speed of the logic circuit and therefore depends on the technology used. In practice, the comb of harmonic lines associated with these pulses is exploitable practically up to a maximum frequency f max = 0.5 / t 2

for a band at -3 dB.

  Thus, with the commonly used techniques, it is possible to obtain harmonic lines up to frequencies of 100 to 200 MHz with rapid fast ITL and CMOS logic (t2 of the order of 2.5 to 5 ns), 160 to 330 MHz in ECL logic (t2 of the order of 1.5 ns), and up to 1 GHz with

  AsGa logic circuits (t2 of the order of 500 ps).

  With regard to the lower limit, the rise time of the signal applied to the input H can not be less than a limit value imposed by the technology used; if it is desired to go below this threshold it is sufficient, instead of directly applying the signal to the frequency fe at the input of the flip-flop, to place upstream thereof a forming circuit of the type Schmitt trigger, so that the base frequency fe

  in input will have no lower limit.

  It is possible to use for the logic circuit other configurations than a D flip-flop, most of the sequential type logic circuits being usable for carrying out the function just described, in particular the flip-flops, the shift registers. , counters, etc. In general, the logic circuit must have: - two complementary outputs Q and Q /, - a synchronous input (the clock input H in the embodiment of Figure 2), whose activation controls the passage of these outputs from one logical state to another (by transmission of the fixed state

6 2633467

  on the input D at the output Q and this inverted state at the output Q /, in the embodiment of FIG. 2), and an asynchronous input (the reset input R in the embodiment of FIG. 2), whose activation controls, independently of the state of the asynchronous input, the passage of the outputs Q and Q / to the states complementary to those which are generated by activation of the synchronous input ( by forcing to zero, in

  the embodiment of Figure 2).

  More precisely, the asynchronous input can allow either the zero forcing or the one forcing of the logic state of the output Q, and the activation of this input can be carried out either by an "O" state (for example a logic TITL or CMOS) or by a state "1" (example of a logic ECL): one can deduce thus four possible basic schemas, all functionally

equivalents.

  With regard to the bandpass filter 2, many conventional arrangements can be used, the type of filter used not being critical for the operation of the comb generator since the latter, of logic type, will work invariable whatever the load coupled to its output.

  Advantageously, a programmable type filter is used, that is,

  say whose center frequency (and thus the multiplication rank chosen) is determined by applying a numerical control on a bus of

order 7.

  FIG. 4 describes such a type of filter: the latter, which is a symmetrical monopolar filter, essentially comprises two series-series LC circuits in opposition, each constituted by a varactor 9 in series with an inductor 10, the tuning frequency of the filter being modified by varying the bias applied to the cathode of the varactor. This variable bias can in particular be achieved by means of an analog multiplexer 8 selecting, as a function of the control signal 7 which is applied thereto, a voltage VPi from a plurality of voltage VP1, VP2 ... VPn, each of these corresponding voltages. to a value of the varactor 9 ensuring a tuning of the resonant circuit LC 9,10 on a frequency centered on one of the lines of the frequency comb applied to the input E. This filter also comprises connecting capacitors 11 at the input and in output, as well as impedances 12 formed of stop chokes and / or resistors of high value for isolating the high frequency signals of the DC voltages applied to the cathodes and anodes

Varactors.

  Such a varactor filter has both a high filtering selectivity (to isolate the useful harmonic line of the spectrum, and it

7 2633467

  only) and the coverage of a wide band of frequencies, ie the possibility of being tuned to a large number of multiplication ranks,

  typically up to the twentieth harmonic.

  FIG. 5 represents an improved variant of the filter of FIG. 4, where the filter of FIG. 4 has been modified by adding impedance adapter transformers 13, 14, 15 so as to obtain a two-pole filter structure. of pseudo-symmetrical type, that is to say that the impedances present on the terminals E and S can, if necessary, be

  chosen different (thanks to the addition of transformers 13,14,15).

  Filters such as those of FIGS. 4 and 5 make it possible, with all the desired selectivity, to obtain satisfactory operation on an agile band of about one octave; for wider agile bands, it is sufficient to provide a plurality of contiguous subband filters, implemented

  selectively by appropriate multiplexing.

  As regards the performances of this circuit, it has been possible to measure an improved intrinsic phase noise of at least 10 dB with respect to the multiplier of the prior art with a snap-off diode, thanks to the use of circuits in technology. CMOS, which are currently the best performers

in this domain.

  FIG. 6 illustrates a variant of the diagram of FIG. 2, in which two improvements (independent of each other) have been made. In the first place, with regard to the comb generator, the output Q is no longer connected directly to the reset input R, but via a time constant network 15, for example a low-pass network RC, the resistor being mounted between terminals Q and R of

  the flip-flop, and the capacitor being mounted between the terminal R and the ground.

  The incorporation of this network 15 makes it possible to increase the duration of the pulse (duration t2 of the timing diagram of FIG. 3), which makes it possible to optimize the energy efficiency as a function of the range of

output frequencies to be covered.

  In the second place, an amplitude limiter 16 can be provided at the output of the filter 2 which will make it possible to reduce the relative level of the parasitic lines with respect to the useful line, without however modifying the

filter structure.

  This limiter 16 may in particular be an amplitude limiter providing a symmetrical clipping of the amplitude and phase modulated signal outputted from the filter 2, which signal has no amplitude or phase modulation transfer. In this way, only the output of the limiter remains the phase modulation energy, which

8 2633467

  will reduce parasitic lines on the output signal

of the circuit.

  This limiter circuit may in particular be constituted by a transistor-type differential stage of conventional type, which is perfectly suitable for the implementation of the present invention. This floor is preceded if

  necessary of a linear amplifier.

  Typically, for a maximum level of spurious modulation of -6 dBc at the output of filter 2, a maximum level of

  parasitic modulation of -30 dBc at the output of the limiter 16.

9 263346?

Claims (6)

  A variable frequency multiplication frequency multiplying circuit comprising a comb generator (1) receiving as input a signal at the base frequency (fe) to be multiplied and outputting a composite pulse signal (A) comprising a plurality of harmonic lines of the base frequency, this comb generator being followed by a band-pass filter (2) tunable selectively on one (N.fe) of these harmonic lines, characterized in that the comb generator (1 ) is formed by logic means having two complemented outputs, a synchronous input whose activation controls the passage of these outputs from one logic state to another, and an asynchronous input whose activation commands, regardless of the state synchronous input, the passage of these outputs to states complementary to those generated by activation of the synchronous input, in that the signal at the base frequency is previously polarized so that its excursion takes place around the transition voltage controlling the transition from one logic state to the other, this signal being applied to the synchronous input of the logic means, and in that a first output of these means is connected to the asynchronous input and the second output delivers to the bandpass filter located downstream   said composite pulse signal.   2. The circuit of claim 1, wherein the asynchronous input is connected to said first output of the logic means with the interposition of a time constant element (15), so as to lengthen the duration of the signal to the optimum. composite pulse delivered on said second output logical means.   3. The circuit of claim 1, wherein said logic means are flip-flop means, the synchronous input being constituted by the clock input (H) and the asynchronous input being constituted by the input reset (R).   4. The circuit of one of claims 1 or 2, wherein the means to   flip-flop comprises a D-type flip-flop whose D input is carried logical level high.   5. The circuit of one of claims 1 to 4, wherein the filter passes   band (2) is a digitally controlled filter, so as to render   programmable the multiplication rank of the circuit.   6. The circuit of one of claims 1 to 5, wherein it is provided,   at the output of the bandpass filter (2), an amplitude limiter (16) 263,346? 7   allowing the signal at the output of the bandpass filter to be kept essentially only the phase modulation of this signal, reducing to a its amplitude modulation.