FR2631503A1 - Interfacing circuit for delivering analogue clock signals to a charge transfer device - Google Patents

Abstract

This circuit, which is intended to deliver analogue clock signals capable of taking at least two different voltage levels in response to the various logic states of a control signal applied as input, is essentially formed of means forming a static analogue switch IA, capable of switching selectively an output pole A, connected directly to the analogue clock signal input of the charge transfer device, to one of the poles of a plurality of input poles B, C, each of which is brought to one of the voltage levels VH, VL which the analogue clock signal has to take, this switching being operated under the command of control logic means L in response to the various logic states of the said control signal K and which are applied as input to these control logic means. If appropriate, the control logic means furthermore include, at the input, a matching stage enabling the voltage levels corresponding to the logic states of the control signal to be aligned with the respective voltage levels corresponding to the same logic states allowing control of the control logic means.

Description

Interface circuit for the delivery of analog signals
from clock to a charge transfer device
The present invention relates to an interfacing circuit for delivering analog clock signals to a charge transfer device.

 "Analog clock signals" will be understood to mean signals which, although capable of taking at least two different voltage levels (usually two, sometimes three) in response to the different logic states of a control signal, have electrical characteristics which are not those generally encountered in usual logic circuits; these analog clock signals can in particular have a high intensity, which can typically reach instantaneous values of several hundred milliamps, owing to the fact that they are applied to essentially capacitive loads, conditions which are not generally those encountered in the case of logical signals in the strict sense (in other words, these clock signals are analog with regard to their physical characteristics, but not with regard to their temporal sequencing).

 These analog clock signals are in particular the vertical transfer clock signals, the horizontal transfer clock signals and the reset register clock signals at the end of each line.

 These respective respective signals have been shown in more detail on the timing diagrams of FIGS. 1 and 2, which correspond to two examples of signals, respectively for an ICX 021l retina from Sony, and to a TH7864 retina from Thomson-CSF.

 Of course, these different signals and these two types of components are only given by way of illustration, without any limiting character, and we have chosen them only to show the diversity of the signals which we may need with the same circuit. or from one circuit to another, and to show the universality of the circuit. interface of the present invention, which can be very simply adapted, as will be seen below, to signals of very varied nature and characteristics.

 In the case of FIG. I (retina ICX 021L from Sony), the vertical transfer clock signal ~ V has a logic zero level at approximately +2 volts, a series of vertical transfer pulses at 4 volts with a frequency of recurrence corresponding to the duration of a line, that is to say 64 KLS and, for each frame (that is to say every 107 lls approximately), a pulse at +13 volts controlling the transfer of loads from the image area to the memory area for the entire frame. The equivalent capacitive load CCE seen at the input ~ V of the retina is relatively large, of the order of 1500pF.

 The horizontal transfer clock signal OH, for its part, is formed by square signals varying between -2.5 volts and +2.5 volts, of cyclic ratio 1: 1, with a recurrence frequency corresponding to the spacing between two successive pixels, which is of the order of 107 ns in the case of a retina at 500 points per line; the equivalent capacitive load CCE is of the order of 60 pF.

 Finally, the signal OPG for resetting the output register to zero has the same characteristics as the signal OH, but with a duty ratio 1: 3, and the two logic states corresponding to voltage levels of 0 and +10 volts.

 Figure 2 shows the homologous signals ~ V, OH and OPG for another type of retina (Thomson-CSF TH7864 in this example), so as to show that the shape of the signals (voltage levels, sequencing) is extremely dependent. the type of component used.

 However, it can be seen in all cases that, for the OH and OPG signals, the clock signals must have a very short rise time (taking into account the high recurrence frequency, the higher the retina has a large number of pixels), but that the equivalent capacitive load is relatively low (of the order of 60 pF).

 Conversely, in the case of the ~ V signal, the rise time is less critical (the recurrence frequency is determined by the number of lines per frame and no longer by the number of pixels per frame), but the equivalent capacitive load is much higher - of the order of 1500 pF.

 In all cases, it will therefore be necessary to apply a relatively large current to the charge transfer device, which can reach peak values of several hundred milliamps: in one case, the equivalent capacitive load is not very high, but the time for climb must be very short (case of OH and Ope inputs); in the other case the rise time is less critical, but the equivalent capacitive load is very high (case of ~ V signals).

 It is therefore impossible to directly use the signals delivered by the control logic to apply them to the corresponding inputs of the charge transfer device.

 An interface circuit must therefore always be provided which, while respecting the timing of the signals, makes it possible to deliver the necessary high current.

 Hitherto, logic gates of the "bus driver" type have been used for this purpose, that is to say control circuits making it possible to deliver current at high speed to a highly capacitive load.

The corresponding configuration is that shown in Figure 3, Figure 4 showing a typical internal diagram of such a control circuit (a
Sony CXB 0026 in this example, which is a circuit allowing to drive currents up to 1.5 A with propagation characteristics at high speed).

 As can be seen in FIG. 3, the circuit of the prior art receives as input a control signal K of TTL type (here and hereinafter, "signal of type 12" will be understood to mean a signal presenting the logic states that TTL type circuits typically deliver, i.e. 0 and 5 volt logic states, without referring to any particular circuit technology, these signals being able to be delivered by MOS type circuits as well , including HC, HEF, -etc.).

 To bias the clock input to the correct voltage level, it is necessary to add, at the output of the control stage DR, an alignment network D, C of the diode-capacity type, combined with an adjustable resistor RA for fine adjustment of the voltage level.

 The use of such circuits however has a number of drawbacks.

 First of all, due to the fact that the control stage DR must be produced in bipolar technology, with the signal input driving the base of a transistor (see the detailed diagram in FIG. 4), the consumption at input d 'such a circuit is relatively large, which can be annoying, especially with the signals delivered by the MOS control units.

 Furthermore, these DR control stages must have a very low output impedance in order to be able to achieve the speed characteristics that they allow. However, although it is necessary, as indicated above, that the rise time is short (in particular in the case of the clock signals OH and OPG), it can be harmful if this rise time is too short, because then rebound phenomena would appear on the signal, which would prevent a correct transfer of the charges and would pollute the resulting video signal. It is to compensate for this low impedance of the circuit DR that a resistor R is interposed between the output of this circuit and the clock input O of the charge transfer device, so that the rise time remains within the limits wanted.

 The present invention proposes to remedy these various drawbacks, by proposing an interfacing circuit which is easy to implement, makes it possible to respect the characteristics of the signals (in particular the rise time) so as not to induce parasitic charges. nor disturb the transfer of the charges to be analyzed, and which is of low consumption for the logic for controlling the timing of clock signals.

 In addition, it will be seen that the circuit of the invention has a universal character, because it is extremely easy to adapt it to charge transfer devices with very different characteristics and to very different types of control logic.

To this end, according to the present invention, the interfacing circuit is essentially formed by means forming a static analog switch, capable of selectively switching an output pole, directly connected to the analog clock signal input of the charge transfer device. , to one of the poles of a plurality of input poles, each of which is brought to one of the voltage levels which the analog clock signal must be able to take, this switching being effected under the control of logic means of control in response to the different logic states of said control signal, applied at the input of these logic control means,
Where appropriate, the logic control means also comprise, at the input, an adaptation stage making it possible to align the voltage levels corresponding to the logic states of the control signal with the respective voltage levels corresponding to the same logic states allowing control of the logic control means.

Other characteristics and advantages of the present invention will appear on reading the detailed description below, made with reference to the appended drawings in which
~ Figures 1 and 2, above, are timing diagrams illustrating
vertical transfer clock, transfer clock signals
horizontal and reset clock output register for
two respective examples of commonly used retinas,
- Figure 3, above, shows the circuit configuration used
in the prior art for the delivery of various explicit signals
Figure 1 and 2,
- Figure 4, above, shows the detail of the internal structure of a
control circuit usable in the diagram of FIG. 3,
- Figure 5 schematically illustrates the basic principle of the
present invention,
- Figure 6 is an example of the internal structure of a switch
static analog with integrated control logic used for
implementation of the circuit of FIG. 5,
~ Figures 7 and 8 show two possible circuit configurations
of the present invention for the delivery of clock signals of
horizontal transfer, respectively in the case of Figure 1 and
in that of Figure 2, and
~ Figures 9 and 10 show two possible configurations of the circuit
of the present invention for the delivery of clock signals of
vertical transfer, respectively in the case of FIG. 1 and in
that of Figure 2,
The essential principle of the present invention, illustrated very diagrammatically in FIG. 5, consists in using a static analog switch to switch the terminal ~, which will be connected to the corresponding clock input of the charge transfer device, to the one or the other of two voltage levels VH (corresponding to the high logic level) or VL (corresponding to the low logic level), voltage levels which can be obtained very simply, directly from the DC power supply (possibly with a voltage divider).

 In other words, the output ~ is multiplexed between two different voltage levels.

 We could also, in the same way, if necessary carry out a multiplexing between three different levels, as is for example the case for the signal ~ V of Figure 1.

 The control logic L of this analog switch is preferably integrated into the switch itself, in order to simplify mounting and to have very high common mode rejection between the power supply and the poles of the switch.

 An analog switch of the 4053 type can be used for this purpose, a component generally used in analog multiplexing / demultiplexing applications.

 FIG. 6 schematically represents the internal structure of such a component for switching from the common pole A to one of the poles (for example B) of the switch, the other pole (C in this example) being indeed heard switched by a signal complementary to that which controls the switching to the first pole.

 The voltage Vcc corresponds to the maximum level of polarization of the circuit, the voltage VEE corresponds to the minimum level of polarization of the circuit (zero volts or else a negative voltage), and Vss corresponds to the level of polarization of the logic ground of the control circuit (in the case of TTL type control signals, Vss will be worth 0 or +5 volts).

 The component used is very advantageously a component in MOS technology (which is the case of 4053), which allows, in addition of course the very low consumption at input for the control signal K, to have a homogeneous technology for the set of circuits, namely the control logic which is generally in CMOS (most often of the HC or HEF type), the interfacing circuit according to the invention and the charge transfer device whose clock inputs are all doors of HALOS.

 On the other hand, the static analog switches that are usually encountered typically have a resistance between switched poles (that is to say between A and B or between A and C, in Figure 5) of the order of 30 to 50 n, and such values are entirely compatible with the minimum time constant that the different circuits must have to avoid the rebound phenomenon mentioned above, so that the resistance R in the figure can be eliminated 3 (which typically had a value of a few tens of ohms) and therefore directly connect the common pole A of the switch to the clock input of the charge transfer device.

 There are shown in Figures 7 to 10 configurations for delivering the ~ H and ~ V signals shown in Figures 1 and 2, which respectively correspond to the signals required for retinas of the Sony ICX 021 and Thomson-CSF TH7864 type.

 As regards the horizontal transfer clock (the case of FIGS. 7 and 8), the voltage excursion VH-VL of the logic signal is less than 10 volts, and a fast switching (less than 20 ns) is sought for relatively low equivalent capacitive load (of the order of 60 with a frequency greater than 5 MHz.

 The typical diagrams are those indicated in FIGS. 7 and 8, and the control logic L can be attacked directly by the control signal K (case of FIG. 7), or by means of a capacitor (case of the figure 8).

 In the case of vertical transfer clocks (Figures 9 and 10), on the contrary, a given voltage level must be established on high equivalent capacitive loads (typically 1500 pF, possibly even up to 3000 pF), with an excursion of high voltage (VH-VL 210 volts), but with a much lower frequency, of the order of 16 kHz.

 Depending on the desired switching time, an AC adapter circuit may be used (case of FIG. 9) making it possible to transform the control signal K of TTL type (0/5 volts) into a control signal -2.5 volts / + 2.5 volts, for example an AC adapter circuit type 4104; the rise and fall times obtained are of the order of 200 ns (such an arrangement is suitable for switching times between 100 ns and 1000 ns).

 In the case of Figure 10, where we needed a much shorter switching time (less than 100 ns), we used a transistor T mounted in common base - therefore with a very low consumption for the signal control command K - in order to transform the control signal K of TTL type (0/5 volts) into a control signal +5 volts / + 11 volts; with this circuit, the measured switching time is of the order of 80 ns, with a conduction resistance of the switch of the order of 30 to 40 R.

Claims (3)

HEVENDICAflons  1. An interfacing circuit for delivering analog clock signals to a charge transfer device, these analog clock signals being able to take at least two different voltage levels (VH, VL) in response to the different logic states a control signal (K) applied as an input,  characterized in that it is essentially formed by means forming a static analog switch (IA), capable of selectively switching an output pole (A), directly connected to the analog clock signal input of the charge transfer device, with one of the poles of a plurality of input poles (B, C) each of which is brought to one of the voltage levels (VH, VL) which the analog clock signal must be able to take, this switching being operated under the control of logic control means (L) in response to the different logic states of said control signal (K)> applied at the input of these logic control means.  2. The circuit of claim 1, in which the logic control means further comprise, at the input, an adaptation stage (CA; T) making it possible to align the voltage levels corresponding to the logic states of the control signal on the respective voltage levels corresponding to the same logic states allowing the control of the logic control means.  3. The circuit of claim 2, wherein the adaptation stage is a transistor stage (T) mounted in common base.