FR2630246A1 - Semi-conductor memory - Google Patents

Abstract

The invention relates to semi-conductor memory technology. A memory according to the invention comprises a circuit 1 which produces internal selection signals in relation with a microchip selection signal applied to the memory; a pulse generation circuit 3 which detects changes in the address signal; and a circuit 9 for changing pulse width which emits a control signal in order to preload or equalize the data lines of an array of memory cells 6. The circuit for changing pulse width lengthens the duration of the pulses of the signal which is applied to it when the internal selection signals are in the selection condition. Application to fast memories.

Description

 The present invention relates to a semiconductor memory comprising a chip selection or inhibition signal terminal, and more particularly relates to a semiconductor memory which has a reduced access time, measured from the application of 'a chip selection signal.

 Figure 6 (a) is a block diagram of a conventional semiconductor memory, and an array of memory cells and a precharge / equalizer circuit of Figure 6 (a) are shown in more detail in the figure 6 (b). The symbol CS indicates the chip selection signal. The level H (high) of this signal indicates the non-selection condition, in which the memory circuit is in a standby condition, and the internal selection signal CSA is then at level H. When the signal CSA is at level H, it inhibits the operation of an address input amplifier circuit 2, and it stops the operation of a decoder 4, which keeps the word and column selection lines, which constitute the memory cell selection lines.

The CTL signal is a control signal for the operation of the circuit, which controls the operation of a precharge / equalization circuit 5, for the data lines which transmit the data of the memory cell network, as well as the operation of the data amplifier 7 and output circuit 8. In the standby condition, this signal is at level H, and the data lines are preloaded and equalized. Simultaneously, the operation of circuits 7 and 8 is interrupted. When the signal
CS is at level H, the signal CSB is at level H, which keeps the signal CTL at level H. There is also a pulse generator 3, to also allow operation when changes occur in the signals of address Ai.

FIG. 7 shows examples of concrete circuits for the selection signal generator 1, the address input amplifier circuit 2 and the pulse generator 3. The signal. CSA is applied at the door entrance
Input OR NOT 20 for address signals, which prevents changes to the Ai signal from being transmitted within the circuit when the CSA signal is at level H. Any change to the Ai signal is detected by the circuit 3 in relation to the rise and fall of the signal, and a signal in the form of ATD pulses is produced for each address, so as to perform an OR operation on the ATD signals for all the addresses. The CSB signal is a signal whose descent is delayed by means of the delay circuit TB of the selection signal generator 1; when it goes down to level B (low), a P-channel MOS transistor becomes conductive, which makes the OR circuits 3-2 work.

 We will now describe the operation of the circuit shown in Figure 6 (a), with reference to the sequential diagram in Figure 8. When the signal level of CS goes from level H to level B, the signal CSA goes to level B , and an address signal Ai is transmitted to the interior of the circuit by the NOR input gate 20. When the signal Ai is at level B, a change occurs in the internal address signal, which generates an ATD pulse. The CTL level goes down at the end of the ATD pulse; If all the signals Ai are at level H and if no ATD pulse is produced, the fall time of CTL does not change, since the signal CSB descends simultaneously with the fall of the ATD pulse. address is passed to the decoder and the signal level of the word lines and column selection lines, which lead to the memory cells to be selected, becomes high. As is well known, the word lines are connected to the memory cells and they are designed so as to select the memory cells which extend in the direction of the rows. The column selection lines select the data lines which are connected to the memory cells to be selected. The information that is stored in the memory cells then appears on the data lines, and it is sent to the output terminal through the amplifier and the output circuit.

 When the signal Ai changes while the signal CS remains at level B, a pulse ATD is produced, which raises the signal CTL at level H, and the preloading and equalization of the data lines are carried out. The data located at the following address is then read.

 In conventional semiconductor memories having a structure such as that described above, the access time conditions relating to the signal CS, when the address signal is at level B, are such that when the signal CS changes and the level CSA becomes low, the output signal of the NOR input gate of address 20 changes. In the case of access by the signal CS, the access operation begins at this time. In the case of access by the address signal, the output signal from the NOR gate 20 changes when the address signal changes, because the CSA signal is already at level B, which starts access.

Consequently, access by the CS signal is delayed more than access by the address signal, with a difference equal to the time necessary for the transmission of the signal from CS to CSA.

 In the case of access by the CS signal, the data line is already preloaded and equalized, and access begins in this condition. There is therefore no particular limit to the acceleration of the rise in the signal level of word lines and column selection lines; it is therefore desirable that the climb be as rapid as possible.

In a conventional semiconductor memory ,. it would be convenient to be able to accelerate the descent of the signal
CSB, decrease the width of the ATD pulse, and thus accelerate the operation of the address input amplifier and that of the decoder. However, in a conventional semiconductor memory, the reduction in the width of the ATD pulse also results in a reduction in the pulse width of the CTL signal. However, in the case of access by the address signal, it there is a risk that erroneous data will be written to the memory cell which is selected next, which would destroy the data recorded, unless the data lines are kept in the restored state for a sufficiently long period , by precharge and equalization by the CTL signal, since the data of the previous cycle remain on the data line.In addition, it is not sufficient to inhibit for a short period the operation of the data amplifier and that of the output circuit, by means of the CTL signal, since this will cause the amplifier to operate before the data has appeared sufficiently on the data line, which will cause malfunction because of the presence of noises, and this has the effect of delaying access.

 It has therefore been impossible in conventional semiconductor memories to accelerate the access by the signal CS by reducing the width of the pulse ATD, because this makes the aforementioned problem appear at the time of the access by the signal d 'address.

 The invention was made with the aim of eliminating the aforementioned problem encountered in conventional semiconductor memories. The object of the invention is therefore to provide a semiconductor memory in which one can achieve rapid access by the signal CS and one can maintain a stable access operation by means of an address.

 The invention provides a semiconductor memory (1) having a chip selection signal terminal, which comprises: a selection signal generation circuit for producing internal selection signals which are delayed with respect to the selection signal chip; a pulse generating circuit for detecting changes in the address signal and generating a signal in the form of pulses; and a pulse width changing circuit for changing the pulse width upon reception of the signal as pulses; this pulse width change circuit comprising a first logic gate which provides a delayed signal for the signal in the form of pulses when the internal selection signals are in the selection condition, and a second logic gate which combines by a function OR the output signal of the first logic gate and the signal in the form of pulses.

 The invention also provides a semiconductor memory (2) having the structure indicated in (1) above and further comprising a selection line control circuit for producing a selection line control signal, this selection circuit selection line control comprising a third logic gate which is adapted to output the signal as pulses as a selection line control signal, when the internal selection signal is in the selection condition, and this signal selection line command controlling activation of word lines and column selection lines.

The invention will be better understood on reading the following description of embodiments, and with reference to the accompanying drawings in which
Figure 1 is a block diagram which shows a semiconductor memory according to the invention;
Fig. 2 is a circuit diagram which shows embodiments of the pulse signal generation circuit, the pulse width changing circuit and the selection line control circuit;
Fig. 3 is a circuit diagram which shows other embodiments of the pulse width changing circuit and the selection line control circuit;
FIG. 4 is a circuit diagram which shows an embodiment of the decoder ;;
FIG. 5 is a sequential diagram which illustrates the operation of a semiconductor memory according to the invention;
Figures 6 (a) and 6 (b) are block diagrams which illustrate a conventional semiconductor memory
Fig. 7 is a circuit diagram which shows a selection signal generation circuit, an input amplifier circuit and a signal generation circuit in the form of # pulses in a conventional semiconductor memory; and
FIG. 8 is a sequence diagram which illustrates the operation of a conventional semiconductor memory.

FIG. 1 is a block diagram of a semiconductor memory according to the invention, while FIG. 5 is a sequential diagram which illustrates the operation of the circuit represented in FIG. 1. The symbol CS denotes a signal of input which passes through the chip selection signal terminal of the semiconductor memory, and this signal is in the chip selection condition when it is at level H (high), and in the non-selection condition when it is at level B (low) .When the signal
CS is applied to a selection signal generation circuit 1, internal selection signals CSA, CSB and CSC are produced, and among these signals, the signal CSC is transmitted to a pulse width change circuit 9 and a a selection line control circuit 10. A signal
CTL1, which is the output signal from a signal generation circuit in the form of pulses 3, is applied to circuits 9 and 10. A signal CTL2, which is the output signal from circuit 9, controls the operation of a precharge / equalization circuit 5, a data amplifier 7 and an output circuit 8. The operation of selecting selection lines word and column is performed by a decoder 4, to decode address signals Ai, and a selection line command signal WCTL, which is the output signal of circuit 10, performs an active state command / inactive.

 As in the conventional memory which is represented in FIG. 7, the selection signal generation circuit 1 produces the signal CSB. However, the delay of the delay circuit DB is fixed at a shorter value, so that the descent of the signal CSB can take place more quickly than in conventional cases. The embodiment which is represented in FIG. 1 further comprises an address input amplifier circuit 2, the fundamental structure of which is the same as in the classic example represented in FIG. 7, with the exception of the size of the transistor, which is chosen larger so as to operate at a high speed. Similarly, the basic structure of the signal generation circuit in the form of pulses 3 is the same as in the conventional memory which is represented in FIG. 7, with the exception of the fact that the number of inverter stages is reduced, in order to reduce the width of the ATD pulse, thereby reducing the delay.

The circuit diagram which is shown in Figure 2 shows embodiments of the circuit. generation of selection signal 1, of pulse width change circuit 9 and of selection line control circuit 10. The descent of signal CSC is delayed by a delay circuit DC. When the signal CSC is at level H in the circuit 9, the level of the signal CTL1 is transmitted in the form of the signal CTL2, via a NOR gate 91 and an inverter 92. When the signal CSC is level
B, the signal CTL1 is applied to the NOR gate 91 not only by the direct path, but also by three stages of inverters and a NOR gate 90, after which an operation
OR is carried out in NOR gate 91, The output signal from NOR gate 90 is therefore delayed due to the effect of the signal passing through four doors in total, and the CTL2 signal appears in the form of a signal having a correspondingly increased pulse width. When the CTL2 signal is at level H, it preloads and equalizes the data lines, which inhibits the amplification and the output of the data.

To avoid faulty operation, the pulse width of the CTL2 sign at the time of a change of address must be sufficiently large; it should be set to a value approximately equal to the pulse width of the signals
ATD and CTL in conventional memories. Because in the invention the pulse width of the ATD signal is relatively small, the pulse width changing circuit 9 has the function of increasing the pulse width.

In other words, circuit 9 increases the pulse width when an access signal access operation is performed with the CSC signal at level B. When the CS signal access is performed with the CSC signal at level H, this circuit does not delay the descent of the CTL2 signal, but causes it to rise rapidly.

In the selection line control circuit 10, when the signal CSC is at level H, the signal WCTL remains at level B. When it is at level B, the signal CTL1 is transmitted via a gate NO -ET 100 and an inverter 101. In other words, when the CSC signal is at level H, the preloading and the equalization are carried out only for a short duration, and the word and column selection lines are not inactivated. When the signal
CSC is at level B, the long pulse of signal CTL2 controls the achievement of preload and equalization for a long time, and the word and column selection lines are temporarily deactivated by the signal
WCTL, in order to avoid faulty operation when the address is changed.

 The circuit diagram of FIG. 3 shows other embodiments of the pulse width change circuit 9 and of the selection line control circuit 10.

In the example which is represented in FIG. 3, when the integrated circuit chip is not selected, that is to say when the signal CS is at level H, the signal CTL2 must enter at level H before preload and equalization can be performed. In addition, the WCTL signal must be at level H for the signal from the word and column selection lines to go low. In circuit 9, the signal
CSB is applied to a NOR gate 93, and in circuit 10, the CSA signal is applied to a NAND gate 103 via an inverter 102. Thanks to this configuration, it is not necessary applying the CSB signal to circuit 3 or the CSA signal to circuit 4, as in the embodiment which is represented in FIG. 1.

 In other words, in the embodiment which is represented in FIG. 1, the signal CSB is applied to the signal generation circuit in the form of pulses 3 to control the signal CTL1, while in the circuit which is represented in FIG. 3, the signal CSB is applied to the NOR gate 93 in the company of the signal CTL1, and the control by the signal CSB is carried out in the circuit 9. In addition, while in the embodiment shown in Figure 1, the decoder 4 is controlled by the CSA signal, this decoder is controlled by the WCTL signal in the embodiment which is shown in Figure 3. Therefore, in the case of the example shown in the Figure 3, the WCTL signal remains at level H until! the lowering of the CSA signal, which inhibits the functioning of the decoder.

 The circuit diagram of FIG. 4 shows an embodiment of the decoder 4 of the invention. To deactivate all word lines by means of the WCTL signal, this signal is applied to a NAND gate 40 of the decoder, by means of an inverter 41. When the WCTL signal is at level H, the outputs of the NAND gate 40 are all at level H, which means that the word lines Wi are all at level B. This also applies to the column selection lines.

 We will now describe the operation of the circuit which is represented in FIG. 1, with reference to the sequential diagram of FIG. 5. When the signal CS is at level H, this implies that the memory is in the condition in which the chip n 'is not selected. At this time, the CSA, CSB and CSC signals are all at level H.

When the signal CS is lowered to level B, which indicates the selection condition, the signal CSA first descends to level B and the address signal Ai is emitted via the input amplifier circuit. address 2, and the address signal Ai is transmitted inwards to produce an ATD pulse in the signal generation circuit in the form of pulses 3. However, since the signal CSB remains at level H, the signal CTL1 does not change and remains at level H, even when the ATD pulse is produced. When this signal CTL1 is at level H, the signal CTL2 is also at level H. This signal CTL2 commands the precharge / equalization circuit 5 to precharge and equalize the data lines, and the operation of the data amplifier 7 and that of the output circuit 8 are thus inhibited.

The CTL1 signal goes down when the CSB signal goes down. Because the CSC signal is still level
HH when the CTL1 signal goes down, the inputs of the doors NO
OR 91 and 93 are always at level B, and the signal CTL2 also descends following CTL1. This ends the preload and equalization, which causes the amplifier and the output circuit to operate. Because at this time the WCTL signal remains low, the NAND gates 40 in Figure 4 are not subject to any restriction by the WCTL signal. Consequently, the decoder 4 decodes the output signal of the input amplifier circuit 2, which accomplishes the word line selection. Column line selection is also performed in the same way, so the word line signal level rises in accordance with the operating speed of the address input amplifier 2 and decoder 4, to accomplish thus the selection of memory cell. Then the CSC signal drops to the level
B.

 When the signal Ai changes as a result of the reading of data at an address, and when the access by an address signal begins, an ATD pulse is produced in the signal generation circuit in the form of pulses 3, and the signal CTL also changes following the signal ATD, to take the form of a pulse at level H. Because at this time the signals CSC and CSB are already at level B, the circuit for changing the width of pulse 9 is working.

The rise in the CTL1 signal pulse causes the CTL2 signal to rise, via NOR gate 91 or 93. On the other hand, the falling edge of the CTL1 pulse is applied to NOR gate 91 and NOR 93 after being delayed by the three stages of inverters and NOR gate 90. I1 results therefrom that the descent of the signal CTL2 is delayed. In other words, as can be seen in FIG. 5, the CTL1 pulse is transformed into a longer pulse, which is the CTL2 pulse.

At this time, the selection line control circuit 10 also operates and a pulse appears in the WCTL signal. When the WCTL signal reaches the level
H, as shown in FIG. 5, all the NAND gates 40 transmit signals of level H, which brings all the word lines Wi down to the low level. Since the word lines make a memory cell selection at level H, all these lines are temporarily placed in the non-selection condition at the time of the change of address. As a result, no memory cell is selected when a change of address occurs and reveals an unstable condition in the chips, which improves the reliability of the memory.

As can be seen in Figure 5, the impulse
CTL2 is long at the time of the change of address, which means that the access by the signal CS takes less time than the access by the address signal, as regards the time which elapses between the rise of the ATD pulse and the completion of the access. In the case of access by the address signal, the pulse width of the CTL2 signal must be the same as in conventional cases, to avoid faulty operation. Therefore, at the time of the change of address which is represented in FIG. 5, the pulse width of the signal
CTL2 is fixed at approximately the same value as for the CTL signal of conventional memories. Simultaneously, the pulse width of the ATD signal is reduced, and the operating speed of the address input amplifier circuit and that of the decoder circuit are increased, so that the CSB signal can descend more quickly. Consequently, in accordance with the invention, the descent of the signal CSB is faster and the pulse ATD is shorter than in the access by the signal CS of conventional type, which means that the preload and the equalization are completed earlier. By speeding up the operation of the address input amplifier circuit and that of the decoder circuit, access by the signal CS becomes faster. On the other hand, because a short ATD pulse is transformed into a sufficiently long pulse at the time of the access by the address signal, the preloading and the equalization of the data lines are effected effectively, which avoids a faulty operation.

 As described above, the invention makes it possible to accelerate access at the time of access by the signal CS, while guaranteeing a sufficient duration for the preload and equalization at the time of access by the signal address. At the time of access by the signal CS, the rise of the signal in the word lines and the column selection lines can be made faster, by accelerating the operation of the address input amplifier circuit and that of the decoder. .

Furthermore, since the operation of the amplifier and that of the output circuit begins under conditions without which the preloading and equalization of the data lines are quickly effected, the complete circuit can operate at high speed, simultaneously with the rise of word lines or that of column selection lines.

 In addition, since a sufficient duration can be guaranteed for the preload and equalization at the time of access by the address signal, which means that the signal level on the word lines and the lines of column selection can only go up after the data rows have reached a stable condition, the amplification and output operations can be performed stably, without destroying the data in the memory cells. In addition, since all word lines are temporarily placed in the inactive state at the time of access by the address signal, defective operation can be avoided at the time of access.

 It goes without saying that numerous modifications can be made to the device described and shown, without going beyond the ambit of the invention.

Claims (9)

 1. Semiconductor memory designed to receive a chip selection signal, characterized in that it comprises: a signal generation circuit intended to produce internal selection signals, in relation to the chip selection signal, a circuit pulse generation for detecting any change in the address signal and for producing a signal in the form of pulses; and a pulse width changing circuit for receiving the signal in the form of pulses for transmitting a control signal for the purpose of controlling the data lines of a memory cell array: and in that the circuit pulse width change outputs the control signal as a signal having a pulse the width of which corresponds to what is obtained by converting the pulse width of the signal into pulses, to give a greater width, when the internal selection signals are in the chip selection condition.  2. Semiconductor memory according to claim 1, characterized in that the pulse width change circuit terminates the emission of the control signal practically in accordance with the termination of the signal pulse in the form of pulses. , when the internal selection signals are in the non-selection condition.  3. Semiconductor memory according to claim 1, characterized in that the control signal is provided for preloading and equalizing the data lines of the memory array, and for inhibiting the operation of the data amplifier and that of the output circuit .  4. Semiconductor memory according to claim 1, characterized in that the pulse width change circuit comprises a first logic gate which is designed to emit a signal delayed with respect to the signal in the form of pulses when the signals internal selection signals are in the selection condition, and a second logic gate which is designed to combine according to an OR function the output signal of the first logic gate and the signal in the form of pulses, to emit the control signal.  5. Semiconductor memory according to claim i, characterized in that it further comprises a selection line control circuit which is intended to produce a selection line control signal, this selection line control circuit comprising a third logic gate which receives the signal in the form of pulses and which transmits the selection line command signal when the internal selection signals are in the selection condition, and in that the activation of the word lines or that column selection lines of the memory cell array is controlled by the selection line command signal.  6. Semiconductor memory according to claim 5, characterized in that the word lines are connected to the gate of a transistor intended to connect the memory cells to the data lines, while the column selection lines are connected to the gate of a transistor which is intended to connect the data lines to the data amplifier.  7. A semiconductor memory of the type comprising a chip selection signal terminal, characterized in that it comprises a signal generation circuit which is intended to produce internal selection signals in relation to the chip selection signal, a pulse generation circuit for detecting any change in the address signal and for producing a signal in the form of pulses; and a pulse width changing circuit which receives the signal in the form of pulses and which outputs a control signal for controlling the operation of a memory cell array; and in that the pulse width changing circuit comprises a first logic gate which emits a signal delayed with respect to the signal in the form of pulses, and a second logic gate which combines the delayed signal and the signal by an OR function as pulses to form the control signal.  8. Semiconductor memory according to claim 7, characterized in that it further comprises a selection line control circuit intended to produce a selection line control signal, and this selection line control circuit emits a second control signal for placing the word lines or the column selection lines in the inactive state, when the internal selection signals are in the selection condition.  9. Semiconductor memory according to claim 7, characterized in that the emission by the first logic gate of the signal delayed with respect to the signal in the form of pulses, is inhibited when the internal selection signals indicate the non-selection condition of chip.