FR2608871A1 - Time-division method of multiplexing and demultiplexing synchronous digital streams - Google Patents

Abstract

This method consists in using the redundancy introduced by a line code of type by successive words of invariable length, which is often used to impart good transmission properties to digital streams, in order to suppress the frame-alignment word customarily used in the course of multiplexing several synchronous digital streams so as to be able to identify them on demultiplexing. The figure shows the diagram of the demultiplexing circuit which includes: a digital stream extraction circuit 41 operating by cyclic sampling of the multiplexed signal in tempo with a set of multiphased signals at the bit clock frequency of each of the digital streams and by synchronising the samples with one of the multiphased clock signals, an extracted digital stream identification circuit 42 which determines the succession of relative shifts of their code words and which delivers a digital signal representative of the rotation to be performed at the outputs of the extraction circuit in order to re-orient the digital streams correctly, and a switching matrix 43 performing this rotation.

Description

Method for multiplexing and temporal demultiplexing of synchronous digital trains.

 The present invention relates to digital transmissions and more precisely the technique of multiplexing and temporal demultiplexing of synchronous digital trains which is a technique making it possible to route several independent synchronous digital signals on a common transmission channel and to separate them on reception.

 In this technique, the transmission equipment or multiplexer performs the time division multiplexing of n independent and synchronous digital signals into a single digital signal of higher bit rate. To do this, each independent digital signal of duration T is assigned a time interval of duration t - T / n approximately and the pulses thus reduced in width are then interleaved.

The receiving equipment or demultiplexer performs the reverse operation.

So that it can identify in the signal delivered by the multiplexer each of the n independent digital signals, it is customary to insert into the signal resulting from the interleaving a periodic reference signal known as the frame alignment word which has the effect of increasing the bit rate of the multiplexed signal.

 The object of the present invention is to avoid the insertion of frame alignment words and therefore the resulting increase in bit rate in the multiplexed signal by taking advantage, for the identification of each of the component digital trains in the multiplexed signal, of the redundancy introduced in digital trains by the transmission codes known under the name of block codes often used to give signals frequency characteristics: absence of DC component, low energy at low frequency and reduction of the occupied frequency band, favorable to their routing by transmission equipment.

It relates to a method of multiplexing and temporal demultiplexing of digital trains synchronous to the number of n, coded individually by means of a unique code by successive words of invariable length of m elements, n and m being whole numbers greater than one , characterized in that it consists - in multiplexing to be searched from the properties of the code for the word cutting of each digital train, in assigning to each digital train an order of succession in an element-to-element multiplexing frame of n trains, to shift the digital trains over time so that the code words of the i th train are offset from those of the i-1 th train taken in the order of succession of a frame, i being an integer varying from 2 to n, of a predetermined number of offset elements Di between 0 and ml, such that the sequence of the nl offsets chosen does not form, with the resulting offset D1, code words of the first train with respect to those of the nth train delayed by the duration of a frame a periodic (D1, .., Di, .. Dn)) of period equal to a sub-multiple of n and
interleaving element by element the n trains thus offset taken in the order of succession of a frame - and at demultiplexing
to deinterlace the n digital trains by adopting an arbitrary frame division,
to search from the properties of the code for the breakdown into words of each train,
to detect the sequence of offsets between words of the different trains (D'2, .., D'i, .. D'n) resulting from the arbitrary frame cutting,
to compare said sequence of offsets (D'2, .., D'i, .. D'n) detected with that adopted for multiplexing in order to deduce the rotation making it possible to pass from one to the other and giving the correspondence between the arbitrary frame adopted at demultiplexing and the real frame used at multiplexing and
to redistribute the trains by identifying them by this correspondence.

 Advantageously, the relative offsets between the code words of the successive trains inside a multiplexing frame are chosen to be zero, the resulting offset between the code words of the first train of a frame relative to those of the last train of the frame delayed by the duration of a frame being equal to 1, to the length of a word.

 The invention also relates to a device for implementing the above method.

Other characteristics and advantages of the invention will emerge from the description below of an example of multiplexing and demultiplexing without frame locking word of three synchronous digital trains transmitted with binary coding by successive words of invariable length and parity. constant.This description will be made next to the drawing in which
FIG. 1 is a block diagram of a time multiplexing circuit according to the invention,
FIG. 2 is an electrical diagram of a circuit for recovering the cutting in code words of a digital train used in the time multiplexing circuit represented in FIG. 1,
FIG. 3 represents diagrams of curves illustrating the operation of the circuit for recovering the cutting in code words represented in FIG. 2,
FIG. 4 is the electrical diagram of a delay circuit used in the time multiplexing circuit of FIG. 1,
FIG. 5 represents diagrams of curves illustrating the operation of the delay circuit of FIG. 4,
FIG. 6 is an electrical diagram of a timing circuit used in the time multiplexing circuit of FIG. 1,
FIG. 7 represents diagrams of curves illustrating the operation of the timing circuit shown in the previous figure,
- Figure 8 is an electrical diagram of a time demultiplexing circuit adapted to the time multiplexing circuit of Figure 1, '
FIGS. 9, 10 and 11 are diagrams explaining the operation of the temporal demultiplexing circuit of FIG. 8,
FIG. 12 is an electrical diagram of a relative offset detection circuit used in the time multiplexing circuit of FIG. 8 and,
FIG. 13 represents diagrams of curves explaining the operation of the circuit for detecting the relative offset of FIG. 12.

 The embodiment which follows will relate to a multiplexing of three synchronous digital trains ta, tb, tc, (n = 3) transmitted with binary coding of the MBtC1P type, this multiplexing being carried out with zero relative shifts between words of code of the different trains, i.e. with D2, shift of code words of train tb compared to those of train ta and D3 shift of code words of train tc compared to those of train tb, both equal to zero. It will however be understood that the invention is not limited to this particular example and, in particular, to the multiplexing of digital trains transmitted with a coding by successive words of m binary elements but also applies to the case of digital trains transmitted with a coding by successive words of m elements or digits having more than two possible values.

 The MBlPlC type coding, advantageous at very high bit rates because it can be manipulated at high speed and only slightly increases the online bit rate, is described in French patent application FR-A-2,570,905. It consists in sharing the data to be transmitted in successive blocks of M bits each coded by a word of M + 2 bits consisting of the M bits of the block to be transmitted inverted or not so as to make the current digital sum tend towards zero and complete with a bit C signaling block inversions and by a parity bit allowing error detection and recovery of block cutting. The parity bit is assumed in the following description, to make the code words even.

 The time multiplexing circuit shown in FIG. 1 has a clock input 1 intended for the bit clock signal Hb of the three synchronous digital trains ta, tb, tc to be multiplexed, the periods of which define the frames of the multiplexing, a first, a second and third data inputs 2, 3 and 4 intended for the three digital trains to be multiplexed ta, tb, tc, considered in their order of appearance in a frame and a data output 5 on which it delivers the bit multiplexed digital trains bit.

 The clock input 1 leads to a sequencer 100 cyclically supplying a three-time sequence defining a series of three bit time intervals of the multiplexed signal each of duration equal to one third of that of the period of the bit clock signal Hb. This sequencer 100 consists for example, as illustrated, of a frequency multiplier by three 10 which defines the bit time intervals of the multiplexed signal and of a counter by three 77 clocked by the multiplier 10 and providing in the form of two addressing digits said sequence which defines the order of succession of the bits of the digital trains in a multiplexing frame.

 The data inputs 2, 3, 4 terminate directly or via timing circuits 12, 13 on the three data inputs 14, 15, 16 of a selector 77 which is addressed by the counter by three 11 of the sequencer 100 and whose output coincides with that 5 of the multiplexing circuit.

 This selector 17 provides bit-by-bit interleaving of the three digital trains ta, tb, tc. It has its three data inputs 14, 15 and 16 addressed successively during each period of the bit clock signal Hb defining the duration of a multiplexing frame, in an invariant order supposed to be that of their indexing, starting with the data input 14 directly connected to the first data input 2 of the multiplexing circuit receiving the digital train ta taken here as a reference train, continuing with the data input 15 connected via the timing circuit 12 to the second data input 3 of the multiplexing circuit receiving the digital train tb and ending with the data input 16 connected via the timing circuit 13 to the third data input 4 of the multiplexing circuit receiving the train digital tc.

 The timing circuit 12 ensures the synchronism of the code words of the digital train tb applied to the second data input 3 of the multiplexing circuit with respect to those of the digital train ta applied to the first data input 2 of the multiplexing circuit. For this, it has the bit clock signal Hb available on clock input 1 and a word clock signal Hma delivered by a word clock recovery circuit 18 operating on the digital train ta applied to the first data input 2 of the multiplexing circuit.

 Similarly, the timing circuit 13 ensures the synchronization of the code words of the digital train tc applied to the third data input 4 of the multiplexing circuit with respect to those of the digital train ta applied to the first data entry 2 of the multiplexing circuit. To do this, it has, as before, the bit clock signal Hb and the word clock signal Hma of the digital train ta.

 FIG. 2 details the electrical diagram of the word clock recovery circuit 18 in the context of a code MBlP1C with even parity and 14 bit words (M = 12 and m = 14).

 This comprises a word clock generator 20 which operates by frequency division of the bit clock signal Hb to deliver the word clock signal Hma and has a phase shift control, and a word parity check circuit 21 code of the digital train ta cut in accordance with the signal Hma delivered by the word clock generator 20, which actuates the phase shift control of the latter in the event of detection of parity errors.

 The word clock generator 20 includes a divider by fourteen counter 202 triggered on a rising edge, clocked by the bit clock signal Hb through a cycle flight circuit consisting of a gate 201 possibly blocked by a monostable 203. Gate 201 is a logic gate of type "or" with two inputs, one receiving the clock signal bit Hb and the other maintained at logic level 0 except during a cycle flight where it switches to logic level 1 under the control of the monostable 203 to mask a half-period at logic level 0 of the bit clock signal Hb.

The parity check circuit 21 comprises a logic gate of type "and" with two inputs 210 receiving the bit clock signal Hb and the digital train ta, and transforming the logic levels 1 of the digital train ta into positive pulses in the manner a transcoder
NRZ / L-RZ, a divider by two counter 211 with trigger on rising edge clocked by the signal Hma delivered by the logic gate of type "and" 210, a register of type D 212 with trigger on rising edge whose input d clock receives the signal Hma delivered by the divider counter by fourteen 202 and the data input D the signal delivered by divider counter by two 211, a monostable 213 with triggering on rising edge and on a falling edge actuated by the output signal D type register 212 and providing a pulse at each transition of this signal, and a parity error quantization circuit 214 which receives the monostable 213 output signal as well as the Hma clock signal and whose output triggers the monostable 203.

 The output signal of the D type register 212 has a logic level transition each time a word of the digital train ta cut in accordance with the word clock signal Hma is of odd parity each of these transitions, detected by the monostable 213, thus translates a parity error.

 The role of the parity error quantization circuit 214 is to limit the sensitivity of the word clock recovery circuit to possible transmission errors in the digital train ta causing parity errors. It is for example of the type of parity error counting and triggering when the number of these errors reaches a predetermined integer k for L consecutive words, the numbers k and L being chosen so as to optimize parameters such as invulnerability to transmission errors in the digital train, the probability of false recovery of word synchronization, the time of acquisition of word synchronization. This circuit can then be carried out simply using a counter by k counting the pulses supplied by the monostable 213 and self-blocking when its count reaches the number k, and of a counter dividing by L clocked by the clock signal word Hma and resetting the counter by k every L periods of this signal word clock, the output signal of the counter by k, at logic level 1 or O depending on whether the count of this counter is or not at k, constituting the output signal of circuit 214 which activates by its rising edges the monostable 2 03 of the word clock generator 20.

 In the event of incorrect centering of the word clock signal Hma delivered by the divider by fourteen 202, with respect to the code words 12B1P1C of the digital train ta, the output of the register of type D 212 passes, randomly, from logic level 1 at the logic level O and vice versa, which causes tripping of the parity error quantization circuit 214 and therefore of the monostable 203 and consequently of thefts of cycles at the input of the divider counter by fourteen 202. At each cycle theft, the word clock signal Hma is delayed by the duration of a binary element. There comes a time when the word clock signal Hma is correctly centered with respect to the word cutout of the digital train ta and when the state of the type D register 212 no longer varies causing the stopping of the cycle flights.

 The diagrams of the curves of FIG. 3 explain this operation in the case where the word clock signal Hma delivered by the divider counter by fourteen 202 happens to be at the start in advance of a binary element on the word cutout of the digital train ta and where the divider by two counter 211 detects a change of parity causing the triggering of the error quantization circuit 214 at the end of the first represented period of the word clock signal Hma. The detection of this change of parity results in the appearance of a rising edge in the output signal of the D type register 212 represented in d and of the monostable 213 as well as the triggering of the monostable 203, actuated by the error quantization circuit 214, which generates a pulse in its signal output represented in e, pulse causing the suppression of a period of the bit b clock signal in the signal which is applied to the input of the divider counter by fourteen 202 and which is represented in f. The deletion of this extension period, of the duration of a binary element, the following half period of the clock signal Hma as is recalled in FIG. 3 by the dotted curve, which has the effect of cropping the signal d word clock Hma on the words cutout of the digital train ta.

 The embodiment of the word clock recovery circuit 18 which has just been described relates, as mentioned previously, to the case of words with even parity. It will be noted that in the case of odd parity words, it suffices to replace, in the parity verification circuit 21, the monostable 213 which forms a circuit for detecting transitions of the output signal of the D type register 212, by a circuit for detecting the absence of transition of this signal between two consecutive periods of the word clock signal Hma, such an absence translating in this case a parity error. This circuit for detecting the absence of transition can be constituted for example by: '' a retriggerable monostable, with pulse at logic level 1 and of duration greater than one period of the word clock signal a and less than two periods of this signal, triggered by the rising edges and the falling edges of the output signal from register 212 and of a logic gate of type "or" receiving the output signal of the retriggerable monostable and the clock signal word Hma and delivering a pulse at logic level O following each absence of transition of the signal d e output of register 212 between two consecutive periods of the word clock signal Hma, pulse which thus translates the detection of a parity error.

 The two timing circuits 12, 13 are identical. According to a first embodiment, they can be constituted as shown in FIG. 1 from a local word clock recovery circuit 22, 23 similar to that 18 previously described for the digital train ta and from a circuit delay 24, 25 operating using the bit clock signals Hb and word clock signals Hma, Hmb, Hmc on the digital trains tb and tc.

 FIG. 4 details the electrical diagram of one of the delay circuits, the circuit 25 being of identical design, operating on the digital train tb applied to the second data input 3 of the multiplexing circuit. This delay circuit always provided for an online code MBIPiC with even parity and words of 14 bits (M = 12 and m = 14) comprises: a bank of thirteen delay circuits 240 which receive in parallel the digital train tb and the affect thirteen (ml = 13) different elementary delays T, 2T, 3T, ..., 13T, T being the bit clock period Hb, which we may need to readjust its code words compared to those of the train digital ta, a selector one among fourteen 241 which selects, from an undelayed version of the digital train tb and the thirteen differently delayed versions of the digital train tb provided by the delay circuit bank 240, the one whose code words are in synchronism with those of the digital train ta, and an offset measurement circuit 26 which determines the effective delay in number of binary elements or of periods T of the clock signal Hb which the code words of the digital train ta have with respect to those of the digital train tb and which addresses the selector one among fourteen 241 so as to delay the digital train tb by as much and to ensure the synchronism of its words with those of the digital train ta.

 The offset measurement circuit 26 comprises a counter by fourteen 260, triggered on a rising edge which counts the periods of the clock signal bit Hb successive between a rising edge of the clock signal word Hmb of the digital train tb and the edge next amount of the word clock signal Hma of the digital train ta. To do this, it is reset to zero on each rising edge of the word clock signal Hma of the digital train ta by pulses delivered by a rising edge detector constituted by a logic gate 261 of type "and" with two inputs receiving the word clock signal Hma of the digital train ta, one directly and the other by means of a delay reverser 262 and it receives the signal clock bit Hb on its counting input via a gate 263 unlocked by a rising edge of the word clock signal Hmb of the digital train tb and reblocked by a rising edge of the clock signal word Hma of the digital train ta This door 263 is a door l ogical type "or" with two inputs, one receiving the bit clock signal Hb, the other a blocking control signal delivered by a type D 264 register with trigger on rising edge which receives on its input of data D of a logic level 0, on its clock input the clock signal word Hmb of the digital train tb and on a reset input the pulses delivered by the logic gate of type "and" 261 corresponding to the rising edges of the clock signal word Hma of the digital train ta.

 The counter by fourteen 260 has its content memorized on each rising edge of the clock signal word Hma of the digital train ta before being reset to zero by means of the pulses generated by the logic gate of type "and" 261 transmitted to its input reset with a slight delay by an amplifier 265.

 This memorization is carried out by means of a battery of registers 266 placed in buffer in front of the addressing input of the selector 241 and directly controlled in writing by the pulses delivered by the logic gate of type "and" 261.

 The curve diagrams of FIG. 5 explain the operation of the preceding delay circuit in the case where the word clock signal Hmb of the digital train tb is found to be in advance of nine binary elements (9T) on the word clock signal Hma of the digital train ta. The curve g represents the signal delivered by the logic gate of type "and" 261 which generates a pulse at each rising edge of the word clock signal Hma of the digital train ta. The curve j represents the output signal of the D-type register 264 which goes to logic level 0 at each rising edge of the word clock signal Hmb of the digital train tb and to logic level 1 at each rising edge of the word clock signal Hma of the digital train ta. The curve k represents the signal delivered by the logic gate of type "or" 263 and applied to the counting input of the counter by fourteen 260, signal which is composed of the nine periods of the clock signal Hb appearing between the next rising edge of the word clock signal Hmb of the digital train tb and a rising edge of the word clock signal Hma of the digital train ta. The number nine contained in the counter by fourteen 260 at the appearance of each rising edge of the clock signal word Hma of the train ta is registered in the battery of registers 266 and addresses via the selector 241 the element of the delay circuit bank 240 having the delay 9T which synchronizes the code words of the version of the digital train tb available at the output of the selector 122 with the code words of the digital train ta applied to the first data input 2 of the circuit multiplexing.

 More generally, the figure contained in the register battery 266 corresponds to the number of bit clock periods Hb whose digital train tb has to be delayed so that its code words are synchronized with those of the digital train ta.

 If it is desired to have a non-zero offset rather than a synchronism, it suffices to take this offset into account at the inputs of the selector 241 by an adequate rotation of the elements of the delay circuit bank 240.

 The timing circuits 12, 13 can also be produced without explicitly calling on a word clock recovery circuit of the digital train processed. FIG. 6 details an electrical diagram of such an embodiment for the timing circuit 12 operating on the digital train tb. This variant always provided for a code MB1P1C with even parity and 14 bit words (M = 12 and m = 14) com carries, as before, a bank of thirteen delay circuits 300 which receive in parallel the digital train tb and affects it with thirteen different elementary delays T, 2T, 3T 13T which one may need to readjust its code words compared to those of the digital train ta, tt a selector one among fourteen 301 which selects from an undelayed version of the digital train tb and the thirteen differently delayed versions of the digital train tb provided by the delay circuit bank 300 the one whose words of code are in synchronism with those of the digital train ta.

 The selector one among fourteen 301 is addressed by a counter by fourteen 302 which makes it possible to cyclically scan all of its inputs and which is incremented by a parity checking circuit 27 operating on the version t'b of the digital train tb available at the output of the selector 301, under the control of the bit clock signal Hb and of the word clock signal Hma of the digital train ta.

 The parity checking circuit 27 comprises, like the previous one, a logic gate of type "and" 270 which has two, inputs receiving one the clock signal bit Hb and the other the version t'b of the digital train tb from the selector 301 and which transforms the logic levels 1 of the said version into positive pulses, a divider by two counter 271, triggered on a rising edge, incremented by the pulses delivered by the logic gate of type "and" 270, a type D register 272 triggering on a rising edge whose clock input receives the clock signal word Hma of the train ta and the data input D the signal delivered by the divider by two counter 271, a monostable 273 to tripping on rising edge and falling edge actuated by the output signal of the D type register 272 and supplying a pulse at each transition of this signal, and a parity error quantization circuit 274 which receives the output signal from the monostable 273 and the clock signal word Hma and the output of which controls the counting input of the counter by fourteen 302.

 In the event of incorrect centering of the code words of the more or less delayed version t'b of the digital train tb relative to the word clock Hma of the digital train ta, the parity checking circuit 27 detects parity errors which cause pass, at random, the output of its type D register 272 from logic level O to logic level 7 and vice versa, and which cause a triggering of the error quantization circuit 274 and consequently the advancement of the counter by fourteen 302 and the change of the version t'b of the digital train tb chosen by the selector 301. The version newly chosen by the selector 301 is in turn tested by the parity check circuit 27 and changed if the latter detects errors of parity causing the triggering of its quantization circuit 274. The non-delayed version of the digital train tb and the different delayed versions from the delay circuit bank 300 are thus reviewed until the one whose code words are in synchronism with the code words of the digital train ta is found.

 The curve diagrams of FIG. 7 explain this operation in the case where the code words of the version t'b coming from the selector 301 are, at the origin, in advance of a binary element on the word clock signal Hma of the digital train ta and where the parity check circuit 27 detects a change of parity causing the triggering of its error quantization circuit 274. This change of parity causes the output of the type D register output signal 272 shown at 1 from logic level 0 to logic level 1 and an incrementation of the counter by fourteen 302 then actuated by the error quantization circuit 274, which causes a change in the version t'b of the digital train tb chosen by the selector 301 for a version with an additional delay of a binary element as shown in the figure by the dotted cross.

 It will be noted that, in the case of odd parity words, the parity verification circuit 27 can be adapted in a similar manner to that indicated above for the parity verification circuit 21 illustrated in FIG. 2.

 This second embodiment of the timing circuits 12, 13 can, like the first, be used to obtain a non-zero offset between the code words of the digital train processed tb or tc and those of the digital train ta. 'add at the output of the selector one among fourteen 301, downstream of the socket of the parity check circuit 27, a delay circuit whose delay coincides with the desired offset.

 In the description given with reference to FIGS. 1 to 7 of the time-division multiplexing circuit represented in the form of a block diagram in FIG. 1, it has been considered that the digital train to be multiplexed serving as a reference for the timing of the other trains to be multiplexed, ctest- ie the digital train applied directly to the selector (17) ensuring the bit by bit interleaving of the trains to be multiplexed and whose word clock controls the timing circuits through which the other trains are applied to the selector, was the digital train first in the order of succession of trains in a multiplexing frame. Of course, any of the trains to be multiplexed can be chosen as the reference train for setting the others. Generally, for n digital trains to be multiplexed, one of which is taken as the reference train, nl is provided timing circuits operating on the nl other trains to be multiplexed so as to impose phase matching on the word clock signal of the reference train ensuring the code words of the n digital trains at the input of the selector the predetermined relative shifts chosen D2,. .. Dn, each timing circuit therefore delaying, for this purpose, the train it processes by a number of bits as a function of the offset it detects between the code words of this train it processes, before processing, and those of the selected reference train and relative offsets.

 FIG. 8 represents the block diagram of a demultiplexing circuit adapted to the multiplexing circuit which has just been described. This demultiplexing circuit has a multiplexed data input 35 on which it receives the three digital trains ta, tb, tc interleaved bit by bit and available at output 5 of the multiplexing circuit of FIG. 1, a first data output 36 on which is available the digital train ta originally applied to the first data input 2 of the multiplexing circuit, a second data output 37 on which is available the digital train tb originally applied to the second data input 3 of multiplexing circuit and a third data output 38 on which is available the digital train tc originally applied to the third data input 4 of the multiplexing circuit.

 The multiplexed data entry 35 leads to a time base 40 and to a circuit for extracting the digital trains 41 followed by a circuit for identifying the extracted digital trains 42 and a switching matrix 43 reorienting the digital trains extracts to the correct output of the demultiplexing circuit under the control of the identification circuit 42.

 The time base 40 formed by an oscillator controlled in phase on the transitions of the multiplexed data signal recovers the bit rate of this signal in order to clock the extraction circuit of the digital trains 41 and to find the bit clock signal of the digital trains.

 The digital train extraction circuit 41 has three data outputs 411, 412, 413 on which it delivers three separate digital trains tx, ty, tz not individually identified but corresponding, within one rotation to the three original digital trains ta, tb, tc taken in their multiplexing order. it comprises a first stage of three shift registers of type D 414, 415, 416, triggered on a rising edge, which sample the input of multiplexed data 35 at the rate of the time base 40, one after the other , in their numbering order, cyclically, by means of three three-phase clock signals generated from that of the time base 40 by means of a counter by three 44 controlling a three-way selector 45, and a second stage of three type D registers 417, 418, 419, triggering on a rising edge, resynchronizing the samples delivered by the first stage of registers on one of the three-phase clock signals, more precisely that H'b applied to the register of type D 414 providing the digital train tx available on the data output 411.

 The digital train identification circuit. 42 operates on the basis of the relative offsets between the code words of the digital trains tx, ty and tz and generates as output a binary signal with two parallel digits and three significant states representative of the possible delays of the code words of the digital train tx with respect to to those of digital trains ty and tz.

 Indeed, the digital trains of origin ta, tb and tc can present themselves at the outputs of the extraction circuit 41 only in three different ways which are deduced from each other by rotations and which can be identified by the delays of the code words of the digital train tx compared to those of the digital trains ty and tz.

 In the first situation illustrated by the diagrams of FIG. 9, a period of the bit clock signal H'b adopted to rhythm the digital trains tx, ty and tz coincides with the frame of the multiplexed signal represented by the repeating pattern a, b , c, recalling the interlacing of the binary elements a of the digital train of origin ta, b of the digital train of origin tb and c of the digital train of origin tc assigned an index recalling their order in a coding word. The digital train tx which results from the first sampling of the multiplexed signal during each period of the bit clock signal H'b has its binary elements x which correspond to those a of the original digital train ta. The digital train ty which results of the second sampling of the multiplexed signal during each period of the bit clock signal H'b has its binary elements y which correspond to those b of the original digital train tb. The digital train tz which results from the third sampling of the multiplexed signal during each period of the bit clock signal H'b has its binary elements z which correspond to those c of the original digital train tc. In this case there is synchronism between the code words of the different trains tx, ty, tz, that is to say that the offsets, are D'2 and D'3 of the code words of the trains tyet tz with respect to to those of the trains tx and ty respectively are zero, because the bits of the same rank of the code words of the digital trains of origin ta, tb> tc are sampled during the same period of the clock signal H'b.

In the second situation illustrated by the diagrams of FIG. 10, a period of the bit clock signal H'b adopted to rhythm the digital trains tx, ty and tz is delayed by a third of period relative to the frame of the multiplexed signal. The digital train tx then corresponds to the original digital train tb, the digital train ty to the original digital train tc and the digital train tz to the original digital train ta. The code words of the digital train tx are in synchronism with those of the digital train ty and one element late with those of the digital train tz, i.e. the offsets D'2 and
D'3 are equal to zero and one respectively, because two bits of the same rank of the code words of the original digital trains tb and tc are sampled with a bit of rank immediately above the code words of the third original digital train ta at each period of the bit clock signal H'b.

 In the third situation illustrated by the diagrams of FIG. 11, a period of the bit clock signal H'b adopted to rhythm the digital trains tx, ty, tz is delayed by two thirds of period with respect to the frame of the signal multiplex. The digital train tx then corresponds to the original digital train tc, the digital train ty to the original digital train ta and the digital train tz to the original digital train tb. The code words of the digital train tx are one bit behind those of the digital trains ty and tz, i.e. the offsets D'2 and D'3 are equal to one and zero respectively because a bit of the code words of the original digital train tc is sampled with a bit of immediately higher rank of the code words of each of the digital trains of origin ta and tb.

 Each of these three situations can be identified by the possible delay that the code words of the digital train tx have compared to those of the digital trains ty and tz. In the absence of delay, the digital train tx corresponds to the digital train of origin ta and the digital trains ty and tz to the digital trains of origin tb and tc. If there is a delay compared to the digital train tz only, the digital train tx corresponds to the original digital train tb and the digital trains ty and tz to the digital train of origin tc and ta. In the presence of a delay with respect to the two digital trains ty and tz, ie digital train tx corresponds to the digital train of origin tc and the digital trains ty and tz to the digital trains of origin ta and tb.

 The digital train identification circuit identifies these situations using three word clock recovery circuits 46, 47, 48 (Figure 8) similar to those described above for the multiplexing circuit, recovering the clock signals word Hmx, Hmy and Hmz of the digital trains tx, ty and tz from these and from the clock signal bit H'b, and to two identical circuits for detecting relative offset 49.50, one 49 detecting a delay of code words of digital train tx compared to those of digital train ty and the other 50 detecting a delay of code words of digital train tx compared to those of digital train tz.

 Figure 12 details the electrical diagram of one 49 of these relative offset detection circuits. This comprises a D 490 flip-flop, triggered on a rising edge, which receives on its clock input the clock signal word Hmx of the digital train tx and on its data input D the pulses delivered by a logic gate type "and" 491 with two inputs receiving the word clock signal Hmy from the digital train ty, one directly and the other via an inverter 492 and a delay circuit 493 providing a delay equal to the duration T of a binary element of trains.

 In the event of synchronism of the clock signals word Hmx and Hmy, the output Q of the flip-flop of type D 490 remains at logic level 0 because the rising edge of the clock signal word Hmx arrives on the clock input of this flip-flop before the pulse caused by the rising edge of the word clock signal Hmy arrives at the input D of this flip-flop.

 In the event of delay of the clock signal word Hmx on the clock signal word Hmy of a duration of a binary element of digital train, the output Q of the flip-flop of type D 490 goes to logical level 1 because the edge amount of the word clock signal Hmx arrives on the clock input of this flip-flop while the rising edge of the word clock signal Hmy generates via the logic gate of type "and" 491 a pulse now momentarily input D of this flip-flop at logic level 1.

 The diagrams in FIG. 13 explain these two operating cases, the curve p representing the signal at the output of the logic gate of type "and" 491 and the curve q the signal at output Q of the flip-flop of type D 490 which is the relative offset detection circuit output signal.

 The switching matrix 43 (FIG. 8) performs on the digital trains tx, ty, tz the rotation corresponding to the situation detected by the identification circuit 42 so as to always present the original digital train ta on the output 36 of the demultiplexing circuit, the original digital train tb on output 37 and the original digital train tc on output 38. It is a conventional switching circuit with three inputs and three data outputs addressed by the two output identification circuit digits 42.

As noted above, the code words of the original digital trains may not be synchronized with multiplexing but assigned specific relative shifts provided, however, that these shifts allow the identification of digital trains tx, ty, tz at the output of the extraction circuit 41. In this case, the identification circuit 42 is slightly modified, its relative offset detection circuits 49, 50 being produced like the offset measurement circuit 26 shown in FIG. 4, the word clock signal Hmx replacing the word clock signal Hmb, the word clock signals Hmy or Hmz replacing, as the case may be, the word clock signal Hma or
Hmb and the bit clock signal H'b replacing the bit clock signal Hb.

 The multi-digit output signals from these circuits are then applied to a transcoding memory, not shown, which contains a correspondence table between the relative offsets measured on the digital trains tx, ty, tz at the output of the extraction circuit 41 and the rotations to be performed to correctly replace the original digital trains ta, tb, tc on outputs 36, 37, 38 of the demultiplexing circuit.

 In order for the correspondence table to be established, the series of relative offsets measured between the code words of the digital trains tx, ty, tz at the output of the extraction circuit 41 must correspond to only one possible distribution. original digital trains ta, tb, tc.

In the general case of n digital trains of origin tl, ... tn multiplexed in their numbering order, we find at the outputs of the extraction circuit 41 a series of n digital trains t'1 ... t'n which results from a more or less complete rotation of the sequence tl, ... tn of the original digital trains. So that the sequence of relative shifts (D'2, .... D'n) of the code words of the digital trains t'2, ... t'n with respect to those of trains t'1, ... t'n-1 measured at the outputs of the extraction circuit 41 differs with each different distribution from the original digital trains (t1 .... tn), it is necessary that the sequence of relative shifts (D2 Dn) of the code words of the digital trains of origin t2 tn compared to those of the digital trains of origin t1, .... tn -1 which immediately precedes them in the same multiplexing frame, supplemented by the relative offset resulting D1 from the code words of the first original train t1 relative to those of the last original train tn delayed by the duration of a frame of multiplexing always forms different patterns with each incomplete rotation, or again, as the result of these relative shifts thus completed (D1. . ..D) is not periodic, of a period equal to one
n sub multiple of n.

Claims (11)

CLAIMS: 1 / Method for multiplexing and temporal demultiplexing of digital trains synchronous to the number of n individually coded by means of a unique code of type by successive words of invariable length of m elements, n and m being whole numbers greater than one, characterized in that it consists - in multiplexing, - in seeking, from the properties of the coding, the division into code words of each train,. to assign to each train an order of succession in an element-to-element multiplexing frame of the n trains,  shifting the digital trains over time so that the code words of the i th train are offset from those of the i-1 th train taken in the order of succession of a frame, i being an integer varying by 2 at n, by a predetermined number of offset elements Di between 0 and m-1, such that the sequence of n-1 chosen offsets does not form, with the resulting offset D1, code words of the first train with respect to those of the n th train delayed by the duration of a frame, a series (D, D2, ... Di, ... Dn) of period equal to a sub-multiple of n and  to interlace element by element the n trains thus shifted and taken in the order of succession of a frame, - and at demultiplexing,  to deinterlace element by element the n trains by adopting an arbitrary frame division,. to search from code properties for the breakdown into code words of each train,. to detect the sequence of offsets (D'2, ... D'i, ... D'n) resulting from the weft cutting adopted at de-interlacing,  compare the sequence of shifts (D'2, .... D'i, ... D'n) detected with that (D2, ... Di, ... Dn) adopted in multiplexing to deduce the rotation allowing to pass from one to the other and giving the correspondence between the positions of the trains in the frame adopted for de-interlacing and in the frame used for multiplexing  and to redistribute the digital trains by identifying them by this correspondence. 2 / A method according to claim 1, characterized in that the offsets of the synchronous digital trains within a multiplexing frame are zero. 3 / Device for implementing the method according to claim with n synchronous digital trains coded individually by means of a unique binary code of type by successive words of length m, n and m being whole numbers greater than one, and accompanied of their common bit clock signal Hb, characterized in that it comprises - a time multiplexing circuit comprising  a sequencer (100) cyclically supplying, from the bit clock signal (Hb) of the digital trains to be multiplexed, an n-time sequence defining for the multiplexed train a series of n bit time intervals each of duration equal to I / nth of that of the bit period of the trains to be multiplexed,  a word clock recovery circuit (18) operating using the bit clock signal (Hb) on one of the digital trains to be multiplexed (ta), called the reference, and delivering the word clock signal (Hma) of this reference train (ta),  a selector (17) with n inputs and an output, the n inputs receiving one the reference train (ta) directly, and the others the nl other digital trains to be multiplexed (tb, tc) via (nl ) timing circuits (12, 13), said selector (17) being addressed cyclically by means of said sequencer (100) and delivering the output signal of the multiplexing circuit and  said n-7 timing circuits (12, 13) controlled by the bit clock signal (Hb) and the word clock signal (Hma) of the reference train (t) imposing on the other nl multiplexed trains (tb, tc) a phase setting on the word clock signal (Hma) of the reference train ensuring that, at the inputs of the selector (17), the code words of each of the n-1 last digital trains to be multiplexed (tb, tc ) taken in the order of cyclic addressing of the selector (17) have compared to those of the digital train (ta, tb) which immediately precedes it during a same addressing cycle of this selector (17) an offset predetermined relative between 0 and m-1 bits and such that the sequence of n-1 predetermined relative shifts (D2,. ... Dn) supplemented by the resulting relative shift (D1) of the code words of the first digital train to be multiplexed (ta) compared to those of the last digital train to be multiplexed (tc) delayed by the duration of a frame is not periodic for a period equal to one sub -multiple of n - and a time demultiplexing circuit comprising  a time base (40) recovering the bit clock signal from the input multiplexed signal,  a digital train extraction circuit (41) with one input receiving the multiplexed signal and n sampling outputs (411, 412, 413) delivering n digital trains (tx, ty, tz) not individually identified, the said circuit d extraction (41) operating by cyclic sampling of the multiplex signal; input by n multi-phase bit clock signals generated from the time base signal (40) by means of a counter by n (44) controlling a selector with n channels (45) and by resynchronization of the samples taken from one- (H'b) of the bit clock signals delivered by the n-channel selector (45),  an identification circuit of the extracted digital trains (42) determining the sequence of the relative offsets CD'2, .. D'n) code words of the digital trains (tx, ty, tz) available on the outputs of the circuit extraction (41) and considered in the cyclic sampling order of this extraction circuit, and delivering a digital signal representative of the rotation making it possible to pass from the series of detected relative shifts (D'2, D'n) following the predetermined shifts (D2, .... D =) used for multiplexing and - a switching matrix (43) receiving the n digital trains (tx, ty, tz) delivered by the extraction circuit (41) and redistributing them on the n outputs of the time demultiplexing circuit under the identification circuit control (43). 4 / Device according to claim 3, characterized in that the timing circuits (12, 13) of the time multiplexing circuit assure the code words of digital trains (tb, tc) that they process a zero offset with respect to those of the reference train (ta). 5 / Device according to claim 3, characterized in that the timing circuits (12, 13) of the time multiplexing circuit each comprise a local word clock recovery circuit (22, 23) clocked by the bit clock signal (Hb), which operates on the digital train (tb or tc) processed by the timing circuit considered and which delivers the word clock signal (Hmb or Hmc) from this digital train, and a delay circuit (24, 25 ) which applies a variable delay to this last digital train to maintain at a determined value the offset of its code words with respect to the code words of the reference train (ta) and which operates under the control of the word clock signal ( Hma) of the reference train (ta) and of the word clock signal (Hmb or Hmc) delivered by the local word clock recovery circuit (22, 23). 6 / Device according to claim 5, characterized in that the delay circuit (24, 25) comprises - a bank of ml delay circuits (240) with ml different elementary delays T, ZT, (m-1) T, T being the period of the bit clock signal (Hb), which receive in parallel the digital train to be processed (tb or tc), - a selector one among m (241) placed following the delay circuit bank (240) which selects a version of the processed digital train (tb or tc) from an undelayed version and the various delayed versions and, - an offset measurement circuit (26) which controls the selector one from m (241) and which is formed by '' a counter per m (260) triggered at the start of the period of the signal delivered by the local word clock recovery circuit (22, 23) operating on the digital train processed and blocked at the start of the period of the signal delivered by the word clock recovery (18) operating on the reference train (ta) and of a battery of type D registers (266) m moralizing the content of the counter by m (260) at the start of the period of the signal delivered by the word clock recovery circuit (18) operating on the reference train (ta). 7 / Apparatus according to claim 3, characterized in that the digital train identification circuit (42) of the time demultiplexing circuit includes word clock recovery circuits (46, 47, 48) operating respectively on the digital trains available at the outputs of the digital train extraction circuit (41) and of nl relative offset detection circuits (49, 50) operating on the basis of the signals delivered by the word clock recovery circuits taken two by two. 8 / A device according to claim 3 for the multiplexing and the time demultiplexing of n synchronous digital trains coded individually by successive words of invariable length m, with the same parity, n and m being whole numbers greater than one, characterized in that the circuit word clock recovery (18) operating on the reference train (ta) comprises  - a word clock generator (20) formed by a meter divider by m (202) clocked by the bit clock signal (Hb) via a cycle flight circuit and,  - a parity check circuit (21) clocked by the bit clock signal (Hb), which operates on the reference train (ta) with the word clock signal (Hma) delivered by the word clock generator (20) and which activates the cycle flight circuit in the event of parity error detection. 9 / Apparatus according to claim 3, characterized in that each timing circuit (12, 13) of the time multiplexing circuit ensures the code words of the digital train it processes (tb or tc) a zero offset from those of the reference train (ta). 10 / Device according to claim 9, characterized in that each timing circuit (12, 13) of the time multiplexing circuit comprises  a bank of delay circuits (300) with ml different elementary delays T, 2T, ..., (m-1) T, T being the period of the bit clock signal (Hb), which receive the digital train in parallel to be treated (tb to tc),  a selector one among m (301) placed following the delay circuit bank (300) which selects a version of the digital train to be processed from an non-delayed version and the different delayed versions,  a counter by m (302) which addresses the selector one among m (301) and  a parity check circuit (27) clocked by the bit clock signal (Hb) which operates on the version of the digital train processed (tb or tc) from the selector one among m (301) with the word clock signal (Hma) of the reference train (ta) delivered by the word clock recovery circuit (18). 11 / Apparatus according to claim 7 wherein each timing circuit (12, 13) of the time multiplexing circuit ensures that the code words of the digital train that it processes (tb or tc) have a zero offset with respect to those of the train of reference (ta), characterized in that the relative offset detection circuits (49, 50) of the time demultiplexing circuit include means for detecting a possible delay of the code words of the digital train (tx) sampled first by the extraction circuit (41) at the start of the period of the bit clock signal (H'b) chosen for synchronization in the extraction circuit (41) with respect to the code words of each of the other digital trains (ty, tz ) available at the outputs of the extraction circuit (41).