FR2478410A1 - METHOD AND DEVICE FOR SYNCHRONIZING A BINARY DATA SIGNAL - Google Patents

Abstract

The invention relates to a method and an apparatus intended, in a data signal receiver, to suitably detect a transmitted message using a local clock signal which is not synchronized with the received data signal. FOR THIS EFFECT, THE ADDITION OR DISAPPEARANCE, BY INTERMITTENT, OF A BINARY CHARACTER OF THE MESSAGE SHOULD NOT HAVE AN EFFECT. THIS CONDITION IS FULFILLED IN A REDUNDANCY SYSTEM, FOR EXAMPLE A SYSTEM IN WHICH THE MESSAGE, CONSISTING OF A FIXED NUMBER OF BITS, IS TRANSMITTED REPEATED AND IN SEQUENCE AND ACCEPTED BY THE RECEIVER PROVIDED THAT THE LATTER DETECTS THE SAME MESSAGE ONE CERTAIN NUMBER OF TIMES IN A GIVEN TIME INTERVAL. FOR THIS EFFECT, TWO SAMPLING CIRCUITS 1, 2 AND ONE PHASE INVERSION CIRCUIT 3 ARE USED. FIELD OF APPLICATION: TRANSMISSION OF BINARY DATA SIGNALS.

Description

1. The invention relates to a method and a synchronization device

  a binary data signal arriving at a receiver with a clock signal available locally in the receiver. The binary data signal can be of the type to

  return to zero or non-return to zero type.

  The problem of synchronization is always present in all data transmissions and is solved in different ways depending on the application, the requested accuracy, etc. For example, if the clocks on the sides of the transmitter and the receiver are synchronized, if possible on a common reference, it is obvious that the detection of data on the side of the receiver poses no problem. Synchronization of a clock

  receiver may be carried out in a manner such that the information

  time is extracted from the transmitted data signal, for example by determining the instant of its passage-by zero, after which a signal corresponding to the time information is enabled to actuate a local and adjustable generator of clock signals. The requirements concerning the transition time and the error allowed in the transmission of the data obviously also influence the choice of the synchronization method. The technical problem to be solved in the present case consists in correctly detecting, by means of a signal which is asynchronous with respect to the data signal, a message transmitted to the receiver, provided that the addition of a binary character to the message or deleting a binary character from this message has no effect. This condition is fulfilled in a redundant system, for example a system in which the same message of a fixed number of bits is the subject of repeated and successive transmissions and is accepted by the receiver provided that the latter can detect the same message a number of times in a given time interval. If the addition of a binary character to the data signal or the removal of a binary character of this signal occurs relatively infrequently, such an occasional event does not affect the correct detection.

of the message by the receiver.

  2. The fact that the clock signal is asynchronous should obviously not mean that the frequency deviation is too large compared to the correct value. A frequency difference of the order or of an amplitude of one per thousand makes it appear, in accordance with the invention, the addition or the suppression of an information character at almost every one thousand bit positions. which can be accepted in

many applications.

  The solution to this problem of the present invention will be described in more detail hereinafter. The main advantage of the apparatus according to the invention lies in its

  extreme simplicity and in the low power required.

  The invention will be described in more detail with reference to the accompanying drawings by way of non-limiting examples and in which: FIG. 1 is a simplified diagram of the apparatus according to the invention; FIG. 2 is a diagram of a phase inversion circuit forming part of the apparatus shown in FIG. 1;

  FIG. 3 is a diagram of a first sample circuit

  lonnage forming part of the apparatus shown in Figure 1; FIG. 4 is a timing diagram relating to several signals of the apparatus shown in FIG. 1; and FIG. 5 is a timing diagram showing the same signals as those illustrated in FIG. 4, but present

  in another embodiment of the invention.

  Figure 1 is a schematic diagram of the apparatus according to the invention. This apparatus comprises a first sampling circuit 1 and a second sampling circuit 2 connected in series between a data input 4 and a data output 6. A phase inversion circuit 3 is connected between a clock input and the clock signal input of the first sampling circuit 1. The second sampling circuit 2 receives the clock signals directly from

the entrance 5.

  The data signal transmitted from the transmitter side is applied to the data input 4, and this signal is assumed to be a binary coded signal of the feedback type.

2 478410

  3rd zero or non-return to zero, as indicated previouslyo The data signal is sampled using the clock signal present at input 5, the clock signal being asynchronous with respect to the data signal, in accordance with assumptions, so that one obtains, at the output of doinées0 a signal synchronized with the clock signal and corresponding to the input data signal0 The circuit 3 phase inversion, which will be diverted; in greater detail below, reverses the phase of the clock signal applied to the first sampling i-cUit when, as a result of the frequency difference between the data signal and the clock signal, Positive or negative flanks of the respective signal tend to coincide. In the preferred embodiment described, sampling circuits 1 and 2 are made using normal D-type flip-flops, triggered by the flanks. The clock signal is assumed to have a rate of 50%, and the input data signal is assumed to be a non-return-to-zero type signal. In view of these assumptions, FIG. 4 shows the time diagram of several signals of the apparatus of FIG. 10. FIG. 2 shows an embodiment of the phase-inverter 3. This circuit comprises a data input 12, a clock signal input 1il and a clock signal output 13. An EXCLUSIVE-OR circuit 10 may be considered as a controlled inverter circuit. If the input 20 is nominally zero, the clock signal from the input 11 passes unabated, except for a negligible delay in this regard. Two pulse shaper circuits 7 are connected by their inputs to the output of the EXCLUSIVE-OR circuit and to the data input 12. These circuits 7 are made so that they deliver, at their respective outputs, a square pulse of given duration when the input signal takes a positive edge. The length of the pulse is small relative to the numerical time interval of the data signal in question. A coincidence detector, in the form of an AND circuit 8 whose inputs are connected to the outputs of the shaping circuits. pulses, emits a pulse at its output 4.

  when the output signals of the circuits 7 overlap.

  This coincidence pulse can trigger a D-type flip-flop 9 triggered by the positive flanks and mounted in a binary counter. The Q output of the flip-flop is connected to the input 20 of the EXCLUSIVE-OR circuit. This arrangement therefore means that a small gap between a positive edge of the data signal and a positive edge of the clock signal causes a reversal of 1800 of the phase of the signal appearing in the

exit 13.

  Signal A of FIG. 4 represents an input data stream of the non-return to zero type. This signal is thus detected in the receiver using the local asynchronous clock signal B. The frequency of the data bits is represented as being constant, as is the frequency of the clock signal. In general, these quantities may, however,

  derive from each other.

  It can be seen immediately that it is not possible to directly synchronize the input data with the signal

  In accordance with the invention as described above,

  2, positive pulses C are now obtained when positive flanks are detected in the input data A. Positive pulses D are formed in the same manner when positive flanks are detected in the signal d clock, the phase of which can be shifted, appearing at the output of the circuit OUEXCLUSIF according to Figure 2. At the appearance of the first flank

  positive in the input data, there is an overlap

  a coincidence, between the positive impulses thus formed. This is indicated by the pulse present in the signal E. In accordance with the foregoing, this pulse controls the inversion of the phase of the clock signal arriving at the input 11, as shown in FIG. 2. Two other coincidences are indicated in the signal E. The clock signal corrected by the phase inversion is illustrated by the signal F. In accordance with what has been previously described, this signal constitutes the clock signal transmitted to the first circuit 1. sampling. The output signal of this sampling circuit is indicated by the letter G. 5. According to the invention, this signal G is now introduced into the second sampling circuit 2 with the unmodified clock signal in the receiver. . The resulting signal at the output of the second sampling circuit and thus constituting the synchronized data signal is indicated in H. It can be seen that the second phase inversion of the clock signal causes a distortion of the data signal under the form of the addition of a bit, indicated by hatching on the drawing. In fact, this deformation is obtained for an out of phase phase shift of the clock signal. The asynchronous relationship is shown with exaggeration to illustrate the procedure of the invention which results in close phase inversions. In a real application of the invention, these phase inversions occur at time intervals greater than several times.

  powers of 10, as mentioned previously.

  In a second embodiment of the invention designed for input data in the form of a zero return type signal, the first sampling circuit 1, consisting of a simple D flip-flop, is replaced by the circuit shown in FIG. 3. This circuit comprises a data input 17, a clock signal input 18 and an output 19 connected to the next circuit 2

  sampling. The function of this circuit will be described below.

  next to Figure 5 which shows the values

  simultaneous signals in the device.

  The signal A of FIG. 5, which is the input signal of the first sampling circuit 1, therefore contains the input data of the type to return to zero. This signal is detected in the receiver using the local asynchronous clock signal B, and it is converted into a zero-return signal, synchronized with the signal B. The upper pulse-shaping circuit 7 of FIG. 2a, as indicated above, the task of producing a short positive pulse at the passage of the positive edge of the signal A. When the input signal is of the return-to-zero type, it is conceivable that this pulse-shaping circuit is useless. because the zero return signal consists of short pulses. In cases where the rate 6.

  pulses of the zero-return arrival signal is extremely

  However, this pulse-shaping circuit is necessary, however small or very large. In the case shown in FIG. 5, it is assumed, for the sake of clarity, that the output signal of the pulse shaping circuit is the

  same as the signal A, that is to say that in this particular case

to bind, the circuit is superfluous.

  A delay circuit 14 is connected to

  data input 17 of the circuit shown in FIG.

  The delay in this circuit is large compared to the delay occurring in the D-type flip-flop 15, but it is small compared to the duration of the pulses from the circuits 7 of Fig. 2. The delayed signal is indicated at A '. In the sequence illustrated in Figure 5, the delay is unimportant and, therefore, its function will be indicated below. The block diagram of Figure 2 has already been described. The signals D, E and F in FIG.

  Signals bearing the same letters in Figure 4.

  When zero return pulses A 'arrive at the clock input of the flip-flop 15 shown in FIG. 3, this flip-flop is positioned in a first state and the signal of its output Q corresponds to the signal I shown in FIG. 5. A fixed voltage corresponding to a logic state one is applied constantly to the data input of the

  rocker. After a while, the rocker is

  a signal applied to its input R and arriving from the output 13 shown in Figure 2. This signal is indicated at F in Figure 5. The detection and inversion of the phase when a coincidence between the signals A and D prevent the flip-flop 15 from being repositioned immediately after or at the same time as it receives a clock signal. The coincidence occurs substantially before the flanks before signals D and A coincide and the coincidence has the effect of generating the signal E which, itself, causes a phase shift of the signal D. The signal D also has the task of triggering the flip-flop 16 of FIG. 3. Since the delay between the signals R and Q, at the flip-flop 15, is much greater than the duration during which the data must remain stable at step D of the flip-flop 16, the introduction of FIGS. data, before they disappear, in the flip-flop 16 using clock signals is no problem. This

  is because the latches 15 and 16 are of the same type.

  If no pulse appears in signal A, c: that is, if a logical zero state has been transmitted, the input

  Q of the flip-flop IG remains at zero, which has the effect of

  The signal G appears at the output 19 of the flip-flop 16 and the signal 0 appears at the output of the flip-flop 2 shown in FIG. 1. The indiciaions P relating to FIG. HI signal of Figure 5 indicate data errors. The data should have had the value l for these two indications Since they were taken by signal A during the corresponding durations, a zero value was obtained at the same time. alternating impulses of the signal E. The indication R of the signal 1 denotes an additional bit, a-analog to the additional bit inCed -en

hatches in Figure 4.

  The need to use a timing circuit 14 does not obviously appear in FIG. 5o. The delay function is only necessary when the frequency of the clock signal M is smaller than the frequency of the bits of the signal of FIG. data, that is to say in a case opposite to that shown in FIG. 5o. It is assumed that the clock frequency B is lower than the frequency of the bits. It is further assumed that the timer circuit 14 is first short-circuited. The trailing edges of the pulses of the signal D then arrive successively close to the flanks before the pulses of the signal A. To phase out the signal D, the signals A and D must be slightly overlapped so that the pulses L are sufficiently long. This situation, immediately prior to the phase inversion, is problematic because the D-type flip-flop 15 is disengaged by clock signals at the same time.

  time that the signal present at its input R is high.

  By introducing the timer circuit 14, this problem does not arise because a phase inversion is obtained before the positive edge of the signal A 'and the negative edge of the signal 8. D coincide. A precondition for this is obviously that the delay is sufficient for the signal E to have the time to cause a phase shift before the coincidence

flanks.

  It goes without saying that many modifications can be made to the apparatus described and shown without

depart from the scope of the invention.

Claims (4)

REVENDIC & TION   Method for synchronizing, in a receiver of binary coded data signals, an input data signal (A) with an asynchronous local clock signal (B) available in the receiver, characterized in that it consists in making advancing the data signal (A) by means of a phase-corrected clock signal (F) formed so that the local clock signal (B) is out of phase with a flank of the clock signal ( F) corrected in phase and a flank of the same type of signal <A) of input data tend to coincide as a result of mutual drift, and to progress again the signal thus obtained with the clock signal (B) uncorrected.   A synchronization apparatus, in a binary coded data signal receiver, of an input data signal (A) with an asynchronous local clock signal (B) available in the receiver, characterized in that   it includes first and second sampling circuits   lonnage (1, 2) each having a data input, a data output and a clock input, a phase inversion circuit (3) having first and second inputs and an output, so that the input of the sampling circuit (1) is the input (4) of the apparatus and is adapted to receive the data signal arriving at the receiver, and its data output is connected to the data input of the circuit sampling device (2) whose data output constitutes the output (6) of the apparatus, the clock input of this first sampling circuit (1) being designed to receive the local clock signal (B ) and the first input of the phase inversion circuit (3) being arranged to receive the clock signal (B), the second input of this circuit being for receiving the data signal (A) and its output being   connected to the clock input of the sample circuit (1)   in order to apply to the latter a corrected clock signal (F) in response to the relative position of the signal flanks of the data signal (A) and the signal clock (B).   3. Apparatus according to claim 2,   characterized in that the first and second exchange circuits   leaching include triggered D-type flip-flops by positive flanks.   Apparatus according to claim 2, characterized in that the phase inversion circuit (3) comprises a controlled inverter circuit (10) having first and second inputs and an output and whose first input is connected to the input (11) of clock signals of the circuit (3) and whose output is connected to the output (13) of clock signals of the circuit (3), the first and second circuits (7) shapers of pulses each comprising an input and an output, the input of this first circuit being connected to the output of the circuit (10) and the input of the second forming circuit being connected to the data input of the circuit (3), a detector two-input coincidence and one output and whose inputs are each connected to an output of a pulse forming circuit (7), a D-type flip-flop triggered by a positive edge and comprising a clock input, an input data (D), a data output (Q) and an ent inverted data signal (Q), the clock input being connected to the output of the coincidence detector, the data input (D) being connected to the inverted data input (Q) and the data output ( Q) being connected to the   second input of the inverter circuit (10).