FR2605785A1 - Semiconductor integrated-circuit device including a microprocessor and a programable ROM memory - Google Patents

Abstract

The invention relates to semiconductor integrated circuits. A single-chip microcomputer includes a central processing unit CPU, a memory ROM serving to store a program, a direct-access memory RAM serving to store data, an programable ROM memory EPROM allowing an electrical write action and an input/output circuit for the data; the action of writing to the memory EPROM is carried out through access from the unit CPU and means are provided for allowing modification of the write time, these means being formed by a timer circuit including a counter effecting the couting of periodic pulse signals in accordance with a counting information item assigned from the unit CPU. Application in particular to single-chip microcomputers.

Description

 The present invention relates to semiconductor integrated circuits and more particularly to an efficient technology applied to a single-chip microcomputer containing a ROM memory (programmable read only memory, in which an electrical write action can be executed by means of an access executed at from a microprocessor for example.

A single-chip microcomputer containing an EPROM memory (electrically programmable ROM memory) is described for example in "Hitachi Microcomputer Data Book, 8-bit single chip" pages 823-865, published by the company known as
Hitachi Ltd. in August 1984. With this single-chip microcomputer, one can easily obtain a single-chip microcomputer with a program desired by a user, by means of the EPROM memory, and its adaptability to mass production can be improved. . That is, if a mask type ROM is used as the built-in ROM, much of the time will be spent on making different masks for writing the program and for making of integrated circuits using masks.

 In recent years, we have noticed the appearance of so-called integrated circuit cards instead of magnetic cards. A single-chip microcomputer containing an EEPROM memory (electrically erasable and programmable ROM memory) and to be used in such an integrated circuit card or in a database is described in RTHE HITACHI HYORON ", Vol. 68, N07, pages 29 -32, published by the company known as Hitachi Hyoronsha on July 25, 1986.

 In this example, the write ROM action is not performed using the above-mentioned writing device, but this write ROM action must be performed directly by means of '' access made from the microprocessor. In this case the action of writing at a ----------------- defined time is executed by an integrated logic circuit such as for example an oscillating circuit.

Since the operating drift of the built-in nonvolatile memory element is relatively large, the write time ---- must be adjusted taking into account the worst case, and that is why, in many cases , significant write time will be used, although this is not necessary.

 An object of the invention is to provide a semiconductor integrated circuit device, such as a single-chip microcomputer containing a programmable ROM memory making it possible to execute the writing action quickly and safely.

 This object is achieved in accordance with the invention using a semiconductor integrated circuit device characterized in that it comprises a microprocessor, the writing action being executed by means of an access made from said microprocessor , and a programmable ROM memory, for which the writing time is variable.

 In accordance with the means mentioned above, since the write action is executed in the minimum time corresponding to the operating drift of the integrated nonvolatile memory element, the write action can be implemented with a fast and safe way.

Other characteristics and advantages of the present invention will emerge from the description given below taken with reference to the appended drawings, in which
- Figure 1 is a block diagram of an embodiment of an EPROM memory, in which the writing time is variable
- Figure 2 is a block diagram of an embodiment of a single chip microcomputer, to which the present invention is applied;
- Figure 3 is a block diagram of another embodiment of an EPROM memory, in which the writing time is variable
- Figure 4 is a block diagram of an embodiment of a timing circuit of this memory
- Figure 5 is a flowchart illustrating a high speed writing algorithm;
- Figure 6 is a block diagram of another embodiment of an EPROM memory, in which the writing time is variable; and
- Figure 7 is a block diagram of an embodiment of a timing circuit of this memory.

 Below we will give a detailed description of the present invention.

 Figure 2 is a block diagram of a single chip microcomputer constituting an embodiment of the present invention.

 In FIG. 2, the part surrounded by a line formed by dashes constitutes an LSI (high integration density) semiconductor integrated circuit, and blocks of circuits surrounded by this line formed by dashes constitute the single-chip microcomputer in its together. The microcomputer is formed on a semiconductor such as monocrystalline silicon, without the invention being particularly limited to this case, by means of a known technology for manufacturing semiconductor integrated circuits.

 The reference CPU designates a microprocessor, and the main building blocks of the microprocessor are shown by way of example in a representative manner. That is, A designates an accumulator, X designates an index register, CC designates a status code register, ST designates a stack pointer, PCH, PCL designate program counters, CPU-COMP designates a controller of the CPU unit, and ALU designates an arithmetic logic operating unit.

 The reference I / O designates an input-output access which includes, on the interior side, a directional data transmission register. The reference I designates an entry only access.

 The reference OSC designates an oscillating circuit, which forms the high-precision reference frequency signal using the external crystal oscillator Xtal, although the invention is not particularly limited to this availability. The clock pulses required in the microprocessor CPU are formed by the reference frequency signal. The reference frequency signal is also used as a reference time pulse for a timing circuit. The timing circuit consists of a counter COUT, a predetermined counter PR and a controller CONT.

 The reference RAM designates a direct access memory, which is used mainly as a temporary data memory circuit.

The reference ROM designates a read only memory which is constituted by a mask type ROM memory, although the invention is not particularly limited thereto, and in which the programs serving to process different information are recorded. The programs include a program for writing data to an EPROM memory as will be described later.
The reference EPROM designates an erasable and programmable ROM memory, which is used mainly for storing important data which must be kept. For example, an integrated circuit bank card records the revenue / payment data, and an integrated circuit card for medical treatment records the consultation data, such as for example the clinical diagram.

The above-mentioned circuit blocks are connected to each other via the microprocessor CPU, in a centralized manner, via a BUS bus. The BUS bus contains a DAT bus for data transmission and an address bus
ADD, ---- as will be described later. The control signal sent to each memory and to each peripheral circuit is not indicated.

 In this embodiment, when the high write voltage Vpp equal to approximately 12 V or 21 V is applied from the external terminal, the EPROM memory receives an address and data produced by the microprocessor and the command signal controlling the writing action so that this writing action is performed, although the invention is not particularly limited thereto. In the writing circuit used to carry out the writing action, the writing time is variable.

If the data stored in the memory
EPROM must not be erased in the integrated circuit
LSI of this embodiment, the entire device is encapsulated ----------- in a plastic housing. On the contrary, if the data must be erasable, a window for ultraviolet radiation is provided in a part where the EPROM memory is formed.

 In the EPROM memory at the initial stage, data is fixed either at the value "1" or at the value "0" by the manufacturing process of the semiconductor element. The data in the initial state, that is to say the erased state, are chosen equal to "1", although the invention is not particularly limited thereto.

 FIG. 1 represents a block diagram of an embodiment of an EPROM memory, in which the writing time is variable.

An M-ARY memory array consists of a matrix arrangement of non-volatile memory elements having a stacked grid structure, including floating grids ----- and control grids (elements hereinafter referred to as stacked gate transistors ''
The control gates of these stacked gate transistors, which are located on the same line, are connected in common to the corresponding word line ------------------ and the electrodes of drain transistors located on the same column are connected to the corresponding data line ------- (line of numbers ----------------- or line of bits) .

 One of the M-ARY memory trunks is selected using an X X-DCR address decoder. That is, the address decoder in X X-DCR has a locking circuit FF which is similar to what the description given above indicates, so that an address signal sent by the through the ADD address bus, is retained ------------------ in the locking circuit FF. Then the address decoder in X X-DCR decodes the address signal and positions a line of words in the selective state.

The network data line ---------------- of memory M-ARY is selected by means of an address decoder in Y Y-DCR. That is, the address decoder
Y Y-DCR has an FF latch circuit which is similar to what has been described above, so that an address signal sent via the ADD address bus is retained in the FF latch circuit . Then the Y address decoder Y-DCR decodes the address signal, and a MOSFET transistor forming a column switch, which connects the data line to the line -------------- --------- common data transmission, is placed in the conductive state. If the recording mode is controlled when the high voltage-Vpp is applied, the X address decoders
DCR, Y-DCR form the selective signal having a high voltage level in accordance with the high voltage Vpp. On the contrary, if the read mode is commanded, IEs decoded addresses X-DCR, Y-DCR form the selective signal having a usual level in accordance with the relatively low voltage Vcc of about 5 V. Switching between the voltages Vpp / Vcc is achieved by means of a WC write control circuit as will be described later.

 The common data transmission line, mentioned above, is connected to the data transmission DAT bus via an f / O input / output circuit. For example, during a read action, the output circuit is set to the active state and sends data from the common data transmission line, to the DAT data transmission bus. During the recording action, the input circuit is positioned on the active state. If data from the data transmission DAT bus are logical "0" in the active state, the input circuit converts this data to the high voltage Vpp and sends the converted data to the common data transmission line. the data is a logic 1, the input circuit sends the ground potential level of the circuit to the common data transmission line. The input circuit has a latch circuit which is similar to that of the address decoder, and retains the recording data in the data transmission DAT bus.

The write signal delivered by the microprocessor CPU is positioned on a WFF write flag. WFF. When WFF is positioned and> output signal
PGM is brought to a high level, the write control circuit WC converts the voltage to a high voltage Vpp. Likewise, the write control circuit WC transmits the write signal to the input circuit of the I / O input / output circuit. In the case of this arrangement, if the corresponding write bit is a logic "0", the input circuit causes the output to deliver the high voltage Vpp. If the write bit is a logical "1", the input circuit places the output at the circuit ground level. Consequently, the write time is made variable in accordance with the positioning / reset of the flag WFF writing by the CPU microprocessor.

In other words, the microprocessor CPU sends atz decoders
X-DCR, Y-DCR from the EPROM memory the specific address signal in the address space allocated to the memory
EPROM via the ADD address bus, and also sends -------------- to the input circuit the data to be recorded, via the DAT data transmission bus. The WFF write flag is set in this state. Since the signal PGM is positioned high and the high voltage Vpp is sent to the decoders X-DCR, Y-DCR and to the input circuit, the EPROM memory begins the recording action. When the hEF flag is set, the X-DCA, Y-DCA decoders and the input circuit retain the address signal and the data respectively. Using the built-in timer circuit shown in Figure 2 or according to a program including the prescribed delay function, the writing flag ## FF is set after the expiration of the defined time interval. Therefore the action of recording the EPROM memory is finished. the recording time in the EPROM memory can be set to any value by means of the time setting in accordance with the built-in timing circuit or the timing program.

 FIG. 3 represents a block diagram of another embodiment of an EPROM memory including a time function - # 'variable writing.

In the case of the writing circuit represented in FIG. 1, since the microprocessor CPU directly controls the writing time in the memory
EPROM, another information processing cannot be executed during this time or at least the performance of information processing is greatly impaired. Although the use of the built-in timing circuit can reduce this deterioration of the information processing efficiency, the hardware resource cannot be efficiently used in particular in an application in which the frequency of writing in the EPROM memory If the write flag is set in error due to a program interruption or the like, erroneous recording may occur in the EPROM memory, or the write flag may remain in the set state. , which results in destruction of the memory element due to over-recording.

 This is why the writing circuit represented in FIG. 3 is provided with a timing circuit TM for exclusive use. Only the microprocessor CPU regulates the writing time information in the timer circuit TM, and this timer circuit TM then completely controls the writing time in the EPROM memory.

As a result, the microprocessor CPU can execute another action for processing information during the action of writing to the EPROM memory.

 FIG. 4 represents a block diagram of an embodiment of a timer circuit TM.

 The time information is recorded in the time register TR by the microprocessor CPU via the data transmission bus DAT. A DCT regressor is triggered by the microprocessor CPU in response to a control signal (not shown), and the time information is positioned as an initial value, and the DCT regressor executes its counting action of impulse signals which are formed by an oscillating circuit OSC. As a result, the output signal PGM of a logic circuit LG is placed at the high level and the write action is triggered in a manner similar to that which has been described above. The logic circuit LG detects the zero of the counting state of the regressive counter DCT and switches the write signal PGM from high to low level.

Thus the write action of the EPROM memory is executed in accordance with the time interval set by the timer circuit TM. For example, if the oscillation period of the oscillating circuit OSC is chosen equal to T and if the value 100 (decimal notation) is set in the time register
TR, the writing time becomes equal to 100 x T. With this arrangement, any recording time can be adjusted in accordance with the value of the counting signal sent to the time register TR and of the oscillation signal.

Triggering of the writing is executed by positioning the WFF flag, without there being any particular limitation. The WFF flag is cleared once the writing is completed.

 Similarly in a microcomputer as shown in the embodiment, in which the oscillating circuit is provided in addition to the timing circuit of the microcomputer so that the clock rate is made variable, the defined recording time can be set without being affected by the clock frequency.

 FIG. 5 represents a flowchart illustrating an example of what is called the high speed writing algorithm, using the writing circuit represented in FIG. 3.

In step (1), the microprocessor CPU executes the write instruction in the EPROM memory, and sends to the EPROM memory an address signal and a write data signal respectively via the bus. ADD addresses -------------- and via the bus
Data transmission DAT. The EPROM memory retains these signals in the locking circuit. During step (2), the CPU also deletes # bcontent of the specific register (N + O). In step 3, the addition of +1 in the register is performed (N + N + 1). In step 4, the unit write time is recorded in the time register TR. For example ple # the oscillation period of the OSC oscillating circuit is chosen equal to 1 ps and the counting state is set to 100 (decimal notation). Therefore the unit writing time becomes equal to 100 ps.

 In step 5, the write action with a duration of 100 us is executed. The CPU performs further processing during this period. If the write signal ---------- PGM is converted from high to low, the microprocessor CPU is interrupted, and the verification mode is commanded during step (6) . Thereby the action of reading from the EPROM memory is executed and a decision is taken with regard to the fact that the data in the non-volatile memory element, which corresponds to the logical writing data "0", becomes a logical "0" or not.

If the decision relating to a coincidence during step (7) is NO1, a decision is taken during step (10) as to whether the value N of the register is equal to 25 or not. If 12. value N is equal to 24 or less, the process returns to step (3). As a result, the write action --------------------- of 100 ps is executed again. If the unit write action is executed twenty-five times, it is established, in step (11), that the memory element has failed and the write action ---- has ended. That is, if the writing action of a logical "O" is impossible even during the lapse of the total writing time of 2.5 ms, it is decided that the writing is faulty and this action is stopped.

If the writing of a logical "0" is decided during step (7), the microprocessor CPU calculates 300x N during step (8), and the result is sent to the time register TR and the action of writing is executed. That is, the overlay writing is executed in
three times of 100 N ps, which are required for the write action of a logic 0. When the overlay write is complete the PGM write signal goes low during step (9) and the CPU microprocessor is subject to an interruption. Hence the writing action
data in the unit (for example a byte) is finished and the process passes to the next writing cycle --- or to the next processing of information. The high speed writing algorithm as described above is executed in accordance with the program stored in the ROM memory, without this being a particular limitation.

 FIG. 6 is a block diagram of an embodiment comprising a logic circuit implementing the high speed write algorithm represented in FIG. 5.

 The device of Figure 6 further includes a CMP comparator. The comparator CMP performs the action of reading the EPROM memory in synchronism with the variation of the write signal PGM, which makes the latter go from the high level to the low level, and also compares the content with the locked write data. in the input circuit. If the result indicates a coincidence, the superimposed write signal OPGM goes high, which has the effect that the superimposed write command is applied to a timing circuit TM.

 FIG. 7 represents a block diagram of an embodiment of the timing circuit TM.

If the timer circuit TM is triggered E the microprocessor CPU in accordance with a control signal (not shown), the content of a time register TR is set as an initial value in a regressive counter
DCT, which begins its counting action. Thereby the output signal PGM of a logic circuit LG is brought to the high level, and the write action is triggered. The logic circuit LG detects the zero of the counting state of the regressive counter DCT and brings by conversion the write signal TGM from the high level to the low level.

 Then the CMP comparator performs a control action. If the result indicates a non-coincidence, the OPGM superimposed write signal is at low level.

In this case the content of the time register TR is adjusted in the regressive counter DCT, and the process is repeated in a similar manner to ~ which has been described above.

 A progressive counter UCT detects the variation of the write signal TGM from high to low level and performs the counting action of this variation. Even if the content of the progressive counter UCT coincides with the prescribed value, for example 25, if the superimposed writing flag OPGM remains low, the decision indicates a writing failure and the writing failure flag is set . Then the regressive counter DCT, the progressive counter UCT and the locking circuit are brought back to their initial states, which ends the entire writing action.

If the writing flag superimposed OPGM goes high, a multiplier MUL multiplies the content of the time register TR by the content of the progressive counter UCT at this time. The MUL multiplier additionally multiplies the result by three for example, and the superimposed recording time information is produced and is set as an initial value in the DCT regress counter, which triggers the write action in a similar manner to the description given above. The OIGEI superimposed write flag is retained during this period. If the superimposed write is finished in this state and if the PGM write signal varies from high to low, the DCT regressive counter, the progressive counter
UCT and the latch circuit are returned to their initial states, which ends the overlapping write action.

 According to the method mentioned above, the high speed writing algorithm shown in Figure 5 can be executed without applying any load to the software. That is, during the recording in the EPROM memory, the microprocessor CPU produces only the starting signal for the circuit for assigning and writing the recording address data, and can execute the write action in a similar way to RAM memory, which makes it possible to prevent a reduction in the efficiency of the information processing executed by the microprocessor CPU.

Also in this case, it is preferable that the unit write time, the superimposed write time and the information of a failure decision can be assigned from the microprocessor CPU. For example, once it has been reset, the TR time register can only be assigned by the microprocessor
CPU. Or the value prescribed in the operation of the equipment can be recorded in the time register TR during the reset.

 In the high speed writing algorithm as described above, the writing action can be executed in a precise and rapid manner at the minimum time corresponding to the drift of the characteristics of the elements.

Setting the writing time in the writing circuit having the writing function
variable of figure 1 or figure 3 can be executed by means of an alteration based on the writing time ----- measured on the manufacturer side. Or otherwise, when adapting the writing method of FIG. 5, the average value of N can be determined on the user side and the writing time can be adjusted on the basis of the average value of N. Since the alteration of the writing characteristics of the element is produced by the repetition of the erasure writes, the writing time or. the superimposed writing time ------------------ can be extended in accordance with the number of repeated writes. When the reliability of the memory retention is not
not strictly required depending on usage, but that the write cycle must be completed in a short period of time based on the large number of write data, write time or write time superimposed can be set to minimum.

Write time information can be saved to a specific memory address
EPROM and the action to read the specific address can be executed before triggering the action d! write, and the write time can be set ----- automatically based on the action of reading the specific data.

For example, if the counting state of the time register TR in FIG. 3 or the value of N to be set in the register is recorded at the specific address of the memory
EPROM, the writing time, which depends on the value mentioned above, can be set automatically.

 In the memory elements formed on the same semiconductor substrate, the writing characteristics can differ from each other in a range corresponding to approximately a factor of 100. That is to say that the maximum time required for the action d writing can be equal to a hundredfold of the minimum time. For example, assume that the guaranteed write time is 10 ms.

During the test, in the circuit of the embodiment of Figure 3, a recording action ----------------- of 100 ps is first executed, and the registered element is determined to be usable and the other elements are subjected to the write action ------------ of 100 tis and a similar decision is made. Subsequently, the write action is executed successively at 200 ps, 400 read, 800 ps, 1600 s and 3200 ps, and a similar decision is made. When the write action --------- - of 3200 ps is finished, the total writing time ---- becomes equal to 6.4 ms and the elements, in which no recording has been executed, are determined to be defective, so as to fix the margin for guaranteed value. In the embodiment of Figure 3, since such a method can be carried out, the test time can be reduced effectively. In particular, when the self-diagnosis is executed by the software in the current state of use, the above-mentioned test procedure is more efficient. Similarly, in the current state of use, it is possible to adapt a writing processing procedure as described above. The write processing procedure as described above can also be implemented by means of the logic circuit as shown in FIG. 6.

The effects, which are obtained with the above-mentioned embodiments, are as follows
(1) Given that the write action is executed by means of an access made from the microprocessor and that the write time in the memory
Programmable ROM is variable, the write action can be executed with the minimum time and the optimal time corresponding to the operating drift of the integrated non-volatile memory element. Therefore the writing action can be implemented quickly and safely.

 (2) In order to make the writing time variable, the flag to be positioned / reset by the microprocessor is used. The high speed writing action can be performed by means of such a simple system.

 (3) In order to make the writing time variable, the setting of the time is executed by the timing circuit including the counting circuit used to perform the counting action of the prescribed periodic pulse signals in accordance with the assigned counting information. by the microprocessor. With this arrangement, only the microprocessor regulates the information of the writing time in the timing circuit, and then this timing circuit fully controls the writing time. As a result, the microprocessor can perform other information processing during the write action.

 (4) The timer circuit is provided with the oscillating circuit, separate from the microprocessor clock circuit. Therefore, even in a microprocessor in which the clock rate is variable, defined recording time can be set without being affected by the clock frequency.

 (5) After the write action executed at the unit time set by the timer circuit, the action for controlling the programmable ROM memory is implemented. The write action of multiple circuits during the unit time is executed until the prescribed write signal is recorded, and then the superimposed write is executed at the predetermined time.

Therefore the writing action can be executed quickly and safely, depending on the drift of the characteristics of the elements.

 (6 If the logic circuit to execute the write operation --- is integrated in the write circuit, the write action can be executed quickly and safely without reducing the efficiency of information processing executed by the microprocessor.

 The present invention has been described in a concrete manner on the basis of the embodiments indicated. However, the invention is not limited to these embodiments, and on the contrary various modifications can be made thereto without departing from the scope of the invention. For example, non-volatile memory elevants can not only consist of stacked-gate transistors, but can also be formed by an EPROM memory using transistorsMNOS (metal nitride-oxide-semiconductor) or FLOTOX transistors (floating gate oxide). electrically erasable. When using the EEPROM memory, the voltage increase circuit used to produce the high voltage Vpp was able to be integrated. Concrete circuits in each block of circuits can be produced by any circuit provided that the latter performs an action similar to that which has been described above.

 The invention includes the programmable ROM memory and the microprocessor so as to electrically validate the writing action, and this writing action is executed by the microprocessor in the programmable ROM memory. Consequently, the invention can be used to a large extent in semiconductor integrated circuits such as various integrated circuit cards, databases or the like, having the function of a microcomputer.

Claims (8)

 1 - Semiconductor integrated circuit device, characterized in that it comprises a microcompressor (CPU), the writing action being carried out by means of an access from said microprocessor, and a programmable ROM memory (EPROM; EEPROM ), in which the writing time is variable.  2 - Device with integrated semiconductor circuits according to claim 1, characterized in that the variation of the writing time in said programmable ROM memory (EPROM; EEPROM) is carried out by a circuit controlled by the microprocessor (CPU).  3 - Integrated circuit device according to one of claims 1 or 2, characterized in that the variation of the writing time in said programmable ROM memory (EPROM EEPROM) is performed by an output signal from a memory circuit which is controlled by positioning / resetting by the microprocessor.  4 - Semiconductor integrated circuit device according to one of claims 1 or 2, characterized in that the variation of the writing time in said programmable ROM memory (EPROM; EEPROM) is carried out by a timing circuit (TM) including a counting circuit (DCT) performing the counting action of prescribed periodic pulse signals in accordance with the counting information assigned from the microprocessor.  5 - Semiconductor integrated circuit device according to claim 4, characterized in that said microprocessor (CPU) performs the action of controlling the programmable ROM memory (EPROM; EEPROM) and after the writing action at the set unit time by the timer circuit (TM) according to the writing program, and performs the writing action at unit time for a number of repetitions, until the prescribed writing data is recorded, then the superimposed write action is performed at the preset time.  6 - Semiconductor integrated circuit device according to one of claims 1 or 2, characterized in that it further comprises, for varying the writing time in the programmable ROM memory (EPROM; EEPROM), a logic circuit ( LG) performing the write action.  7 - Device with integrated semiconductor circuits according to any one of claims 1 to 6, characterized in that the programmable ROM memory is an EPROM memory.  8 - A semiconductor integrated circuit device according to any one of claims 1 to 6, characterized in that the programmable ROM memory is an EEPROM memory.