FR2601461A1 - Scintillation camera - Google Patents

Abstract

Scintillation camera comprising a scintillator crystal 10, a collimator 20, a light guide 30 and a set 50 of p photodetectors, p acquisition channels 60, and a computer 100 intended to deliver the coordinates xj and yj of a scintillation j, and the energy Ej which is associated with this event j, characterised: a. in the said p acquisition channels deliver p digital signals to the input of the computer; b. in that the computer 100 itself comprises: - a transfer bus for the said p digital signals, - a digital summing stage 200, - an event processing stage, c. in that a detection, sequencing and storage stage 400 receiving a signal which corresponds to the sum of the p output signals of the photodetectors is provided, in order to deliver, on the one hand, the various clock signals and correction coefficients intended for the event processing stage. Application: scintillation cameras used in nuclear medicine.

Description

SCINTILLATION CAMERA
The present invention relates to a scintillation camera comprising a scintillator crystal possibly equipped with a collimator and intended to convert each photon received into a scintillation, a light guide for the coupling of said crystal to the input window of a set of p photodetectors intended to convert each scintillation into current, p acquisition channels receiving the output signals from said photodetectors and delivering p electrical signals with characteristics linked in particular to the intensity of the scintillation and to the distance of this scintillation to each of the photodetectors, and a computer intended to deliver the coordinates xj and yj of a scintillation j and the energy
Ej which is associated with this event j.

 To determine the image of radioactive fixations inside an organ, medicine uses, among other means, the principle of scintigraphy. This principle consists in introducing into the body of a patient a radioactive element which will fix itself more or less on certain organs depending on whether they are healthy or sick. The measurement of the intensity of gamma radiation emitted then provides an indication of the distribution of the radioactive element in the body and therefore constitutes an aid to diagnosis. Such a measurement is carried out using a scintillation camera.

 In traditional scintillation cameras, for example of the Anger type (the Anger physicist being the first to have proposed a scintillation camera, the fundamental principles of which are described in US Patent No. 3011057), gamma rays representative of the radioactive distribution in the medium examined, after crossing a collimator, in a scintillating crystal. The scintillations which occur in this crystal are then detected by the intermediary of a whole series of photomultiplier tubes (for example 37), after crossing of a light guide ensuring an optical coupling between the crystal and the tubes. distributed in front of the optical unit (crystal + light guide) to cover practically its entire surface and transform the light energy of each scintillation that has appeared into a measurable electrical signal.

 Each photomultiplier tube is then associated with an analog acquisition channel operating successively an amplification, integration and shaping of the signals supplied by the tube. The outputs Sij of all the acquisition channels are sent to a computer which provides, by estimation, the coordinates xj and yj of a scintillation j and its energy Ej (the index i denotes that of the acquisition channels which is concerned ). In the calculator, several types of calculating devices can be provided, but two of them essentially are actually used, namely a barycentric calculating device with arithmetic ratio, or a barycentric calculating device with logarithmic ratio.

In an arithmetic ratio barycentric calculating device, the quantities xj, yj, Ej are given by the expressions
Xs
xj = 3 (1)
Zj Yj
Zj

les coefficients Gi, Ki, Hi, Ji étant des facteurs de pondération liés à la position de l'axe de chacun des p tubes photomultiplicateurs.In these expressions, we have

the coefficients Gi, Ki, Hi, Ji being weighting factors linked to the position of the axis of each of the p photomultiplier tubes.

In a barycentric logarithmic calculating device, the quantities xj, yj, Ej are this time given by the expressions

The weighting factors are also linked to the position of the axis of each of the p photomultiplier tubes.

 In either case, whatever arithmetic is used, current scintillation cameras generally include weighted sum calculation devices which use resistance networks with which summing amplifiers are associated. In cameras of this type, it is not possible to carry out the calculations relating to an event (a scintillation) before the signals corresponding to the previous event have been brought to zero, which fixes the speed of maximum counting. To increase this counting speed, various solutions have been proposed, providing for example by reducing by means of analog circuits the duration of the electrical signals or the integration time. This reduction was however obtained only at the expense of certain intrinsic characteristics of the cameras, in particular the spatial and spectral resolutions.

 The applicant proposed in a previous French patent application FR-A-2 552 233 a digital device for measuring radiation avoiding the need for a complete return to zero of the electrical signals before any new measurement, that is to say accepting a partial stack of detected events (and therefore electrical signals, or pulses, which correspond to them).

 The object of the invention is to propose a new scintillation camera incorporating certain elements of this device but arranged partly in the p acquisition channels, partly within the computer, and according to a simplified electronic architecture making it possible to carry out the conversion. analog-digital signals followed by their digital integration from converters of less precision and therefore very inexpensive. This architecture also makes it possible to perform the stacking calculations by means of a limited number of processing circuits.

To this end, the invention relates to a scintillation camera characterized
(A) in that said p acquisition channels carry out the amplification, filtering and sampling of said photodetector output signals, then the analog-digital conversion of the samples obtained and their summation, and deliver p digital signals to the computer input
(B) in that the computer itself understands
(a) a bus for transferring said p digital signals
(b) a digital summing stage comprising four digital weighted summing devices which deliver from the output signals of the p acquisition channels four digital signals Xm, Yml Zm, Em
(c) an event processing stage including stacking calculation circuits and two dividers and delivering from the signals Xm, Yml Zm, En the three signals of coordinates and energy x, y, E
(C) in that a detection, sequencing and storage stage receiving a signal which corresponds to the sum of the p output signals from the photodetectors is provided to deliver on the one hand the different clock signals for the synchronization of the elements of the p acquisition channels and computer elements and secondly correction coefficients intended for the event processing stage.

 European patent application No. 0166169, for example, describes a scintillation camera which performs analog-to-digital conversion only in the computer, which in particular leads to the use of components of high precision and therefore considerably more expensive, currently in a report of 1 to 100 at least.

The features and advantages of the invention will now appear more precisely in the description which follows and in the appended drawings, given by way of nonlimiting examples and in which
- Figures 1 and 2 show the block diagrams of a scintillation camera according to the prior art and according to the invention respectively
- Figure 3 shows an embodiment of the device for converting and integrating each of the p acquisition channels
- Figure 4 shows a first embodiment of the computer of a scintillation camera according to the invention
FIGS. 5a to 5c respectively show the individual signals corresponding to close scintillations resulting in a partial stacking, the overall signal resulting from this stacking, and the shape of the signal representing the measured value which results from the summation of the samples during the interval of time 8d + l for channel i (this value being measured at time tolu + 1
- Figure 6 shows an example of. realization of one of the destacking stages of the event processing stage
- Figure 7 shows an embodiment of the detection, sequencing and storage stage
- Figure 8 shows an alternative embodiment of the stacking calculation circuits such as that of Figure 6
- Figure 9 shows a second embodiment of the computer of a scintillation camera according to the invention, including the alternative embodiment of the stacking calculation circuit shown in Figure 8
- Figure 10 shows a third embodiment of the computer of a scintillation camera according to the invention, including a third embodiment of the event processing stage
- Figures 11 to 13 and 14 to 16 show, in correspondence with Figures 4, 9, 10, the modifications of. calculator when only three calculation paths X are used,
Y, Z or X, Y, E respectively.

 The conventional type scintillation camera shown in FIG. 1 comprises a scintillator crystal 10 equipped with a collimator 20 and intended to convert each photon received into a scintillation. This crystal is coupled via a light guide 30 to the entry window of a set of p photodetectors constituted here by photomultiplier tubes 50. These tubes 50 convert each scintillation into a current which is then treated by p entirely analog acquisition channels 60. These acquisition channels 60 carry out in particular the amplification, the filtering, the integration and the shaping of the output signals from the photomultiplier tubes 50, and are followed by a computer 100 providing the coordinates xj, yj and the energy. Ej.

 According to the embodiment which will now be more particularly described, in correspondence with FIG. 2 showing with respect to FIG. 1 the modifications of the block diagram for a camera according to the invention, the p acquisition channels 60 are no longer completely analog as in conventional cameras, but they provide p digital signals Mi, j (i = index varying from 1 to p) at the input of the computer 100. These p channels now carry out successively the amplification, the filtering and the sampling of the output signals from the photomultiplier tubes 50 then the analog-digital conversion of the samples obtained and the summation of these digital samples. The value of these p digital signals is linked to that of the output current of the tubes 50 and therefore to a fraction of the intensity of the initial scintillation, but differently depending on the rate of stacking of scintillations (this fraction is itself linked to the production of the optical unit and in part iculier to the distance between the scintillation point and the axis of the tubes).

If there were no stacking, the value of each of these signals would be noted Si, j; the estimate of these values in the presence of stacking will be noted Sìlj.

Each of these p channels therefore comprises in series, in order to carry out the functions mentioned above, an amplification and filtering circuit 61 receiving the output of the corresponding tube 50, a time realignment circuit 62, then a device for converting and d integration 63 successively ensuring the sampling of the output signals of the corresponding circuit 62, the analog-digital conversion of the samples obtained and the summation thereof. An analog summing amplifier 64 is also provided, the p inputs of which receive the p outputs of the amplification and filtering circuits 61 and the output of which is supplied to a pulse start detector located in the detection stage, sequencing and storage 400 described below. The output of each of the p conversion and integration devices is sent to the computer 100, possibly via p so-called FIFO memories (from gFirst-In,
First-Out ") allowing later work at lower frequencies by regulating the flow of events.

This arrangement of FIFO memories in fact allows a reduction in the speed of subsequent calculations and the slower rate thus obtained can be practically equal to the average rate of arrival of events (for example 2 microseconds for an average rate of 500,000 events per second) and no longer at the random rate of arrival of events (around 0.2 microseconds in the previous example). Each of the conversion and integration devices 63 is here equivalent to that described in French patent application FR-A-2 552 233 and in this case comprises, according to the embodiment of FIG. 3, a circuit of sampling and analog-to-digital conversion 310 followed by an adder 311. Following this adder 311 are in turn provided a first register 312 for storing the output of the adder, the output of which is returned to a second input of this adder, and a second register 313 for storing the output of the adder, the output of which is that of the conversion and integration device which thus performs a cumulative addition and a corresponding memorization as and when the arrival of the samples. These operations are carried out under the control of the detection, sequencing and storage stage 400 which will be described later.

 The computer 100 receiving the p outputs from the acquisition channels itself comprises various calculation devices which will make it possible to distinctly determine the coordinates xj, yj and the energy Ej of any scintillation j, i.e. using relationships ( 1) to (6) in the case of a barycentric calculating device with arithmetic ratio either by means of relations (7) to (13) in the case of a barycentric calculating device with logarithmic ratio.

où Mi,j représente la valeur mesurée à l'instant to,j+ résultant de la sommation des échantillons pendant l'intervalle de temps 8j,j+1 pour la voie i. La forme du signal Moi 'j est représentée sur la figure 5c.More specifically, this computer 100, shown in FIG. 4 in the case of a barycentric calculation device with arithmetic ratio, is arranged as follows. It firstly comprises a transfer bus 150 of the digital signals Mi, j available at the output of the p acquisition channels. If, for one of these channels, for example channel i, we represent the individual analog signals associated with several scintillations close in time (FIG. 5a) and the signal resulting from the stacking of these individual signals (FIG. 5b) , we note that the event j is disturbed upstream by several events jl, j-2, etc ... If aj and rk, j are correction coefficients respectively by extrapolation and by interpolation which can be determined from the knowledge of the mean form, as a function of time, of the pulses corresponding to a detected event and from the measurement of the duration Ej, j + 1 between t, lj and to, j + 1, if k is successively equal to j-1, j-2, ..., jq, and if the signals 5ik represent for these respective values of k the corrected values of the stacking effects which would be provided by the digital acquisition channel i in response to the scintillations jl , j-2, ..., jq, then the digital signals obtained at the output of acquisition channels are of the form

where Mi, j represents the value measured at time to, j + resulting from the summation of the samples during the time interval 8j, j + 1 for the channel i. The shape of the signal Moi 'j is shown in Figure 5c.

les coefficients Ki, Hi, Ji. Gi étant l'expression numérique des facteurs de pondération définis en rapport avec les expressions (3) à (6) (pour un dispositif de calcul barycentrique à rapport arithmétique).Chacun de ces dispositifs de sommation pondérée numérique est par exemple du type du multiplieur-accumulateur TDC 1009 (commercialisé par la société TRW, La Jolla, CA 92038, USA), dont l'une des entrées reçoit la sortie correspondante du bus 150 et dont l'autre reçoit les coefficients de pondération sous forme numérique, stockés dans une mémoire auxiliaire. Dans le cas où l'on utilise effectivement ce type de multiplieur-accumulateur, ladite mémoire auxiliaire, qui doit être synchronisée avec le fonctionnement d'ensemble du calculateur, peut être par exemple incorporée à l'étage de détection, séquencement et stockage 400 décrit plus loin.The computer then comprises, at the output of the transfer bus 150, a digital summation stage 200 itself composed, as shown in FIG. 4, of four digital weighted summation devices 201 to 204. These four devices 201 to 204 respectively produce the following weighted summations

the coefficients Ki, Hi, Ji. Gi being the numerical expression of the weighting factors defined in relation to expressions (3) to (6) (for a barycentric calculating device with arithmetic ratio) .Each of these numerical weighted summing devices is for example of the multiplier type -accumulator TDC 1009 (sold by the company TRW, La Jolla, CA 92038, USA), one of the inputs of which receives the corresponding output of bus 150 and the other of which receives the weighting coefficients in digital form, stored in a auxiliary memory. In the case where this type of multiplier-accumulator is actually used, said auxiliary memory, which must be synchronized with the overall operation of the computer, can for example be incorporated into the detection, sequencing and storage stage 400 described. further.

 The output signals Xm, Ym, Zm, Em from the output of the digital summing stage 200 are then supplied to an event processing stage 500. This stage 500 comprises, as shown in FIG. 4, four circuits for calculating destacking 501 to 504, two dividers 505 and 506 and a time realignment circuit 507. The four circuits 501 to 504 being identical, only one of them is described here, for example circuit 501. This one, represented in FIG. 6, comprises a subtractor 510 receiving on its first positive input the output of the corresponding digital weighted summing device 201 (to the devices 201 to 204 correspond respectively the circuits 501 to 504). The subtractor 510 is followed by a first multiplier 511 and by a storage register 512 whose output is that of the circuit 501. The subtractor 510 is also followed, in parallel on the elements 511 and 512, by a second multiplier 513 and a second storage register 514. These multipliers can be replaced by a single multiplication circuit associated with a time-division multiplexer-demultiplexer.

The negative input of the subtractor 510 is connected to the output of the storage register 514. The second input of the multiplier 511 is connected to the output of a memory 470 storing the coefficient aj and that of the multiplier 513 is connected to the output of a memory 480 storing the coefficient xj, k. The outputs X, Y, Z, E of the four stacking calculation circuits 501 to 504 are given, for the event j, by the expressions

 The elements of each circuit 501 to 504, for example the elements 510 to 514 of circuit 501, constitute a stacking calculation circuit equivalent to that described in application FR-A-2 552 233 with the references 120 to 160. The other three circuits 502 to 504 include the same elements as circuit 501.

The output X of the stacking calculation circuit 501 is sent to the first input of the divider 505 and the output Y of the circuit 502 to the first input of the divider 506. The second input of each of these dividers is constituted by the output Z of the circuit for stacking calculation 503. The three outputs of the processing stage, which are also those of the computer, are constituted by the output ~ tie xj = Xj / Zj of the divider 505, the output xj =
Yj / Zj of the divider 506 and the output Ej of the time realignment circuit 507 provided at the output of the unstacking calculation circuit 504. To these elements is also associated, in the computer, the detection, sequencing and storage stage 400. stage 400, shown in FIG. 7, first comprises a pulse start detector 410, which receives the output of the summing analog amplifier 64 (see FIGS. 2 and 4). This detector 410 is followed by a clock circuit 420 which generates periodic signals ensuring the control of a sequencing circuit 450 and that of a counter 430 of these clock signals. The number thus counted is subjected to a test circuit 440 the output of which is sent to the sequencing circuit 450. The latter ensures the synchronization of the operations carried out in the acquisition channels, in stage 200 and in stage 500 , and validates the content of a register 460 for storing the output of the counter 430, a register which is in parallel on the test circuit 440. At the register output 460 there are two memories 470 and 480 mentioned above with reference to the FIG. 6 and respectively storing the coefficient ajet the coefficient Yj, k. The elements 410 to 480 which have just been mentioned constitute a detection, sequencing and storage stage similar to that which is described in the application.
FR-A-2 552 233.

avec toujours xj = X'jlZ'j et yj = Y'jlZ'j. Le coefficient de correction Ck,j est une fonction de 6j,j+ et des 8k,j Dans ce mode de réalisation, l'étage de traitement des événements est maintenant référencé 600, et les trois circuits de calcul de dés empilement qui reçoivent respectivement les signaux X1, Ym, Zm sont modifiés par suppression du multiplieur 511. Ces trois circuits ont en effet la structure représentée sur la figure 8 pour l'un quelconque, par exemple le premier de ces trois circuits 601 à 603. Ce circuit 601 comprend un soustracteur 610 qui reçoit sur sa première entrée la sortie du dispositif de sommation pondérée numérique correspondant 201. Le soustracteur 610 est suivi d'une part directement d'un registre de stockage 612, dont la sortie est comme précédemment celle du circuit de calcul de désempilement, et d'autre part, en parallèle, d'un multiplieur 613 puis d'un registre de stockage 614. La sortie de ce registre 614 est renvoyée vers la deuxième entrée du soustracteur 610, et l'autre entrée du multiplieur 613 est reliée à la sortie de la mémoire 480 prévue dans l'étage 400 pour le stockage du coefficient y. Les deux autres circuits 602 et 603 comprennent des éléments similaires. Le circuit de calcul de désempilement 504 restant inchangé, le calculateur 100 prend maintenant la configuration représentée sur la figure 9.L'énergie E est, comme précédemment, disponible en sortie du circuit de réalignement temporel 507.In a second embodiment, the calculation of the coordinates of the events can be carried out without introducing an extrapolation, according to the following expressions

with always xj = X'jlZ'j and yj = Y'jlZ'j. The correction coefficient Ck, j is a function of 6j, j + and of the 8k, j In this embodiment, the event processing stage is now referenced 600, and the three computation circuits for de-stacking which respectively receive the signals X1, Ym, Zm are modified by deleting the multiplier 511. These three circuits have in fact the structure shown in FIG. 8 for any one, for example the first of these three circuits 601 to 603. This circuit 601 comprises a subtractor 610 which receives on its first input the output of the corresponding digital weighted summing device 201. The subtractor 610 is followed on the one hand directly by a storage register 612, the output of which is as previously that of the stacking calculation circuit , and on the other hand, in parallel, of a multiplier 613 then of a storage register 614. The output of this register 614 is returned to the second input of the subtractor 610, and the other input of the multiplier 6 13 is connected to the output of the memory 480 provided in the stage 400 for the storage of the coefficient y. The other two circuits 602 and 603 include similar elements. The unstacking calculation circuit 504 remaining unchanged, the computer 100 now takes the configuration shown in FIG. 9. The energy E is, as before, available at the output of the time realignment circuit 507.

In a third embodiment, shown in FIG. 10, the computer 100 includes a third type of event processing stage, referenced 700. In this alternative embodiment, the stacking processing is no longer carried out on the signals Xm, Ym, Zm of output from the digital summation stage 200 but on xm and ym coordinates, say measured because deduced directly for each event j from uncorrected quantities
Xm, Ym, Zm according to the relations xm, j = Xm, jlZm, j and
Ym, j = Ym, j! Zm, j. These signals Xm and ym are obtained at the output of two dividers 705 and 706, the divider 705 receiving the outputs of digital summing devices 201 and 203 and the divider 706 receiving those of devices 202 and 203. The coordinates xj, yj corresponding to l event j are then obtained at the output of the stacking calculation circuits 701 and 702, on the one hand from these so-called measured coordinates and on the other hand from the coordinates already known xk, yk of the preceding events which disturb the event j , according to the following expressions

The coefficients Pk, j, which are a function of the measured time intervals 6j, jf k, j and of the ratios Ek / Ej are calculated in an additional calculation circuit 707 which receives on the one hand the output E of the stacking calculation circuit 504, still present in the processing stage, and on the other hand the coefficients a and X delivered by the detection, sequencing and storage stage 400. In this example, the circuit 707 calculates on the one hand, from the values of E successively received, the successive ratios Ek / Ej and on the other hand the products aj vklj from which the coefficients Pk, j are evaluated according to the relation rk, j = Qj wk, j Ek / Ej. The stacking calculation circuits 701 and 702 have a configuration similar to that of circuits 601 and 602. Energy E is, here again as previously, available at the output of the time realignment circuit 507.

 Of course, the present invention is not limited to the embodiments described and shown, from which other variants can still be proposed without thereby departing from the scope of the invention. For example, an amplitude rejection circuit for the number of events to be processed can be provided, in order to perform the calculations only on selected events (using a threshold, an energy window, etc. ..). On the other hand, a time multiplexer can be provided to use only one divider instead of two in each of the embodiments of FIGS. 4, 9 and 10. A time multiplexing circuit can also be provided to reduce the number stacking calculation circuits and use only one stacking calculation circuit instead of the four circuits 501 to 504 in the case of the embodiment of FIG. 4, of the four circuits 601 to 603 and 504 in the case of the embodiment of FIG. 9, or of the three circuits 701, 702 and 504 in the case of the embodiment of FIG. 10. All the variants proposed in this paragraph also apply to the other embodiments of the Figures 11 to 16.

 Taking into account the means of correcting the linearity and energy faults which are used in the gamma cameras currently available from the signals x, y, E obtained at the output of the computer, it is known that it is possible to use either Z or E for the calculation of the coordinates. In this case, it is possible to calculate only one of these two quantities and, according to the choice made, to deduce the other quantity of calculations involving specific corrections of this choice and executed by said means.

The digital summing stage 200 then only comprises three digital weighted summing devices supplying signals Xm, Ym, Zm or Xm, Ym, Em respectively. Likewise, the event processing stage 500 no longer comprises only three stacking calculation circuits. Figures 11 to 13 show, in correspondence to Figures 4, 9, 10, the modifications of the computer when only three channels X, Y, Z are used, while Figures 14 to 16 show, still in correspondence with Figures 4, 9, 10, the computer modifications when only three channels X, Y, E are used.

 On the other hand, it will also be noted that it is possible, to work at lower frequencies by regularizing the rate of events, to introduce, upstream of the digital summation stage, FIFO memories for writing and reading controlled by the 'detection, sequencing and storage stage 400.

 Finally, it is equivalent to consider that the bus 150 is incorporated into the computer, of which it is the input or access element, or that, on the contrary, it is associated with it without being included in it.

Claims (17)

1. Scintillation camera comprising a scintillator crystal possibly equipped with a collimator and intended to convert each photon received into a scintillation, a light guide for the coupling of said crystal to the input window of a set of p photodetectors intended to convert by running each scintillation, p acquisition channels receiving the output signals from said photodetectors and delivering p electrical signals with characteristics linked in particular to the intensity of the scintillation and to the distance of this scintillation to each of the photodetectors, and a computer intended for deliver the coordinates xj and yj of a scintillation j and the energy Ej which is associated with this event j, characterized  (A) in that said p acquisition channels carry out the amplification, filtering and sampling of said photodetector output signals, then the analog-digital conversion of the samples obtained and their summation, and deliver p digital signals to the computer input  (B) in that the computer itself understands  (a) a bus for transferring said p digital signals  (b) a digital summing stage comprising four digital weighted summing devices which deliver from the output signals of the p acquisition channels four digital signals Xm, Ym, Zm. Em ;;  (c) an event processing stage including stacking calculation circuits and two dividers and delivering from the signals Xm, Ym, Zm, Em the three signals of coordinates and of energy x, y, E  (C) in that a sequencing and storage detection stage receiving a signal which corresponds to the sum of the p output signals from the photodetectors is provided to deliver on the one hand the different clock signals for the synchronization of the elements of p acquisition channels and computer elements and, on the other hand, correction coefficients intended for the event processing stage. 2. Scintillation camera according to claim 1, characterized in that the event processing stage comprises four destacking calculation circuits, receiving respectively the digital signals X, Ym, Zmf Emr and delivering four signals X, Y, Z, E , and two dividers respectively delivering two signals x = X / Z and y = Y / Z, the three signals x, y, E being constituted by the output signals respectively of the first divider, the second divider and a realignment circuit time receiving the output of the fourth stacking calculation circuit, and in that the correction coefficients are correction coefficients by extrapolation and interpolation, a and y respectively, intended for the four stacking calculation circuits of the processing stage of the events. 3. Scintillation camera according to claim 2, characterized in that each of the four stacking calculation circuits comprises a subtractor receiving on its first input the output of the corresponding conversion and integration device, this subtractor being followed on the one hand a first multiplier and a first storage register, and on the other hand, in parallel on this first multiplier and this first register, of a second multiplier and of a second storage register, the output of this second register being connected to the second input of the subtractor and the second inputs of the first and second multipliers being connected the first to the output of the storage memory of the coefficient a and the second to the output of the storage memory of the coefficient y. 4. Scintillation camera according to claim 3, characterized in that the multipliers are replaced by a single multiplication circuit associated with a time-division multiplexer-demultiplexer. 5. Scintillation camera according to claim 1, characterized in that each of the first three stacking calculation circuits comprises a subtractor receiving on its first input the output of the corresponding digital summing device, followed on the one hand by a third register storage whose output is that of the stacking calculation circuit and on the other hand, in parallel, of a third multiplier then of a fourth storage register, the output of this fourth register being connected to the second input of the subtractor and the other input of the third multiplier being connected to the output of the storage memory of the coefficient y. 6. Scintillation camera according to claim 1, characterized in that the event processing stage comprises three destacking calculation circuits, two dividers, a time realignment circuit, and an additional calculation circuit, the two dividers receiving the signals Xm, Ymt Zm for delivering two signals xm = -Xm / Zm and Ym = Ym / Zm, the first two stacking calculation circuits receiving said signals xm, ym and delivering the signals x, y and the third receiving the signal En and delivering the signal E, and the additional calculation circuit receiving on the one hand said signal E and on the other hand said correction coefficients to provide the first and second destacking calculation circuits with an additional correction coefficient r. 7. Scintillation camera comprising a scintillator crystal possibly equipped with a collimator and intended to convert each photon received into a scintillation, a light guide for the coupling of said crystal to the input window of a set of p photodetectors intended for converting each scintillation into current, p analog acquisition channels receiving the output signals from said photodetectors and delivering p electrical signals with characteristics linked in particular to the intensity of the scintillation and to the distance from this scintillation to each of the photodetectors, and a computer intended to deliver the coordinates xj and of a scintillation j and the energy Ej which is associated with this event j, characterized  (A) in that said p acquisition channels carry out the amplification, filtering and sampling of said photodetector output signals, then the analog-digital conversion of the samples obtained and their summation, and deliver p digital signals to computer input  (B) in that the computer itself understands  (a) a bus for transferring said p digital signals  (b) a digital summing stage comprising three digital weighted summing devices which deliver from the output signals of the p acquisition channels three digital signals Xm, Ym, Zm or Xm, Ym, Em respectively  (c) an event processing stage including stacking calculation circuits and two dividers and delivering from said digital signals X Ym, Zm or Xm, Ym, Em respectively the three signals of coordinates and energy x, y, E  (C) in that a detection, sequencing and storage stage receiving a signal which corresponds to the sum of the p output signals from the photodetectors is provided to deliver on the one hand the different clock signals for the synchronization of the elements of the p acquisition channels and computer elements and secondly correction coefficients intended for the event processing stage. 8. Scintillation camera according to claim 7, characterized in that the event processing stage comprises three destacking calculation circuits, receiving respectively said digital signals, Xml Ym, Zm. X, Y, Z, or X, Y, E respectively, and two dividers respectively delivering two signals x = X / Z and y = Y / Z or x = X / E and y = Y / E respectively, the three signals x , y, E being constituted by the output signals respectively of the first divider, of the second divider and of a time realignment circuit receiving the output of the third stacking calculation circuit, and in that the correction coefficients are coefficients of correction by extrapolation and interpolation, a and y respectively, intended for the three destacking calculation circuits of the event processing stage. or Xm, Ym, En respectively, and delivering three signals 9. Scintillation camera according to claim 8, characterized in that each of the three stacking calculation circuits comprises a subtractor receiving on its first input the output of the corresponding conversion and integration device, this subtractor being followed on the one hand a first multiplier and a first storage register and on the other hand, in parallel on this first multiplier and this first register, of a second multiplier and of a second storage register, the output of this second register being connected to the second input of the subtractor and the second inputs of the first and second multipliers being connected the first to the output of the storage memory of the coefficient a and the second to the output of the storage memory of the coefficient w- 10. Scintillation camera according to claim 9, characterized in that the multipliers are replaced by a single multiplication circuit associated with a time-division multiplexer-demultiplexer. 11. Scintillation camera according to claim 7, characterized in that each of the three stacking calculation circuits comprises a subtractor receiving on its first input the output of the corresponding digital summing device, followed on the one hand by a third register of storage whose output is that of the stacking calculation circuit and on the other hand, in parallel, of a third multiplier then of a fourth storage register, the output of this fourth register being connected to the second input of the subtractor and the other input of the third multiplier being connected to the output of the storage memory of the coefficient y. 12. Scintillation camera according to claim 1, characterized in that the event processing stage comprises three destacking calculation circuits, two dividers, a time realignment circuit, and an additional calculation circuit, the two dividers receiving the signals Xm, Ym, Zm to deliver two signals xm = Xm / Zm and ym = Ym / Zm, or respectively the signals Xm, Ym, Em to deliver two signals Xm = Xm / Em and y, = Ym / Em, the first two stacking calculation circuits receiving said signals xm, Ym and delivering the signals x, y and the third receiving the signal Zm or By and delivering the signal E, and the additional calculation circuit receiving on the one hand said signal E and on the other hand said correction coefficients to provide the first and second destacking calculation circuits with an additional correction coefficient r. 13. Scintillation camera according to one of claims 1 to 12, characterized in that the dividers are replaced by a single division circuit associated with a time multiplexer-demultiplexer. 14. Scintillation camera according to one of claims 1 to 13, characterized in that the stacking calculation circuits are replaced by only one of these circuits with which is associated a time-division multiplexer-demultiplexer. 15. Scintillation camera according to one of claims 1 to 14, characterized in that an amplitude rejection circuit is provided for reducing the number of events to be processed. 16. Scintillation camera according to one of claims 1 to 15, characterized in that so-called FIFO memories are provided at the output of each of the p acquisition channels or upstream of each of the digital weighted summation devices. 17. Scintillation camera according to one of claims 1 to 16, characterized in that the bus is associated with the computer without being included.