FR2597281A1 - Analogue/digital coding device, of the type with modulation of duration - Google Patents

Abstract

This device includes: - first means 1, 2, 3, 4, 5, C0, D1, D2, C1, C2 for carrying out, in a first stage, a first analogue/digital conversion over <<n1>> bits with n1 </= n, or <<rough>> conversion; - second means 1, 3, 4, 6, 7, C'0, D3, D4, C2 for carrying out, in a second stage, from the result obtained at the end of the first conversion, a second analogue/digital conversion over <<n2>> bits with n2 = n - n1 or <<fine>> conversion; - third means 8 for subtracting from the result obtained at the end of the first conversion the result obtained at the end of the second conversion. Application: analogue/digital coding.

Description

ANALOGUE-DIGITAL CODING DEVICE,
OF THE DURATION MODULATION TYPE
The present invention relates to an analog-digital coding device of the "duration modulation" type.

Various techniques are known for carrying out an analog-to-digital conversion, in particular the so-called “parallel” (also called “flash”), “series-parallel”, or even “duration modulation” techniques. Each of these methods has its advantages and disadvantages relating to conversion speed and precision.

Thus the "parallel" technique is a rapid technique, but with a resolution quickly limited by the equipment to be implemented. The “series-parallel” technique makes it possible, thanks to a particular assembly of converters of the “parallel” type, to combine the speed of conversion of these converters with a high resolution, but is an expensive technique.

The present invention relates more particularly to the so-called “duration modulation” technique.

The known devices operating according to this technique have the drawbacks of their relative slowness and, for many applications, their insufficient precision.

These devices in fact consist in counting, by means of a pulse generator, the time which elapses until a signal, of regularly increased amplitude with each pulse, reaches the level of the signal to be digitized, and, once this level is reached, to stop the conversion. So, for a seven-bit conversion, the counter would have to register 127 pulses before reaching full scale. With a clock frequency of 100 KHz for example, it would take 1.27 ms to perform the conversion, or a conversion rate of about 800 words per second, which is very low.

Known devices of this type are described in particular in the book entitled “Analog-to-digital and digital-to-analog conversion techniques” (David F. Hoeschele Jr Masson).

The subject of the present invention is an analog-digital coding device operating according to the so-called “duration modulation” method and exhibiting an increased operating speed compared to the preceding devices, while remaining simple and easy to implement.

According to the invention, an analog-to-digital coding device of the duration modulation type is essentially characterized in that it comprises: first means for initially performing a first analog-to-digital conversion on "n" bits (with n1 <n), or "coarse" conversion, by counting the number of pulses of a clock signal until the level of the signal S to be digitized is crossed by a locally generated signal S 1, the amplitude of which is regularly increased , at each clock pulse ;; - second means for carrying out in a second time a second analog-digital conversion on "n2" bits (with n2 = n - zero), or "fine" conversion, by counting the number of clock pulses until crossing , in the downward direction, the level of the signal S to be digitized by the same signal SI, the amplitude of which then decreases regularly, at each clock pulse, and from the level acquired at the end of the first conversion; - third means for subtracting from the digital result on nl bits, supplied by the first means and representing high order bits, the digital result on n2 bits supplied by the second means and representing low order bits, these third means providing the digitized signal sought.

Other objects and characteristics of the invention will emerge more clearly on reading the following description of exemplary embodiments, given in relation to the appended drawings in which: FIG. 1 is a diagram of a first example production of an analog-digital coding device according to the invention; - Figures 2a, 2b and 2c are time diagrams relating to the diagram of Figure 1 - Figure 3 is a diagram of the same type as that of Figure 1, incorporating a variant; FIG. 4 is a diagram of a second exemplary embodiment of an analog-digital coding device according to the invention; - Figure 3 is a time diagram relating to the diagram of Figure 4.

The two embodiments described differ by obtaining the signal S1: - according to the first example, this is a "staircase" signal, obtained by means of diode pumps; - According to the second example, it is a ramp, obtained by means of integrators.

In both cases, the device for coding on n bits according to the invention comprises first means for carrying out initially a first coding on nl bits (with nl <n), or coarse coding, and second means for carrying out in a second step a second coding on n2 bits (with n2 = n-nl) or fine coding.

In FIG. 1, the first coding is carried out as follows: a pulse generator 1, through a coarse coding selection circuit 2 (itself activated by a decision logic 3) charges a capacitor C1 + C2 by a first diode pump D1 D2 and a capacitor C0.

The voltage S 1 thus obtained is compared with the signal S to be digitized in a comparator 4, the signal S being in the form of a constant signal obtained at the output of a sampler-blocker. If the level of the signal S1 is lower than the level of the signal S to be digitized, the coarse coding selection circuit 2 is again activated by the decision logic 3 and again transmits a clock pulse H which causes the charging of the capacitor Cl + C2 and the incrementation of a counter 5 called "big" counter. The level of the signal SI is thus regularly increased in stages and this until it becomes greater than the level of the signal.
S to be digitized in which case the decision logic 3 activates a fine coding selection circuit 6 which supplies clock signal pulses H of opposite sign to the preceding ones. These pulses, via a second diode pump D3 t) 4, and a capacitor C0, then cause the discharge of the capacitor C2 (the capacitor C1 remaining charged to its previously acquired value). As before, the voltage S1 obtained is compared in the comparator 4 with the signal S to be digitized. If the level of the signal S1 is greater than the level of the signal S to be digitized, the fine coding selection circuit 6 is again activated by the logic decision 3 and transmits again a clock pulse which causes the discharge of the capacitor C2 and the incrementation of a counter 7, called an "end" counter.

The level of the signal S1 thus decreases regularly in stages, and this until it becomes lower than the level of the signal S to be digitized, in which case the conversion is stopped, the decision logic being reset to zero and two switches I1 eut'2 reset preparing the next cycle by discharging capacitors C1 and C2. This process appears in FIG. 2a showing the shape of the signals S, H and S1.

The digitized signal SN, with n bits, is formed by subtraction in a subtracter 8 of the content of counters 5 and 7. The content of counter 5 is a digital word representing most significant bits and corresponding to the analog value 4, in the case of the example described in FIG. 2a (four clock pulses having been necessary in this example to obtain the crossing of the signal S by the signal S1 in the ascending direction) and the content of the counter 7 a digital word representing bits of low weight and corresponding in the example considered to the analog value 6 (six clock pulses having been necessary to obtain the crossing of the signal S by the signal S1 in the downward direction).

The number 2n1 + 2n2 of clock pulses necessary to perform coding according to the invention is less than the number of pulses 2n, i.e. 2 1 + n2, which would have been necessary with a device of the prior art, d 'where the greatest speed of the device according to the invention.

By way of example, an eight-bit coding can be done with a first coarse coding on four bits (nl = 4) hence a maximum number of clock pulses (or of rising steps) equal to sixteen, then with a second fine coding on four bits (n2 = 4), hence a maximum number of clock pulses (or of descending steps) equal to sixteen, ie a total of thirty-two clock pulses at most. By counting for example at 400 MHz, compatible with silicon, the time required to perform these operations is then 80 ns, which leaves 20 ns for resetting the converter.

In existing analog-to-digital converters, there is a risk of ambiguity whether or not the level of the signal to be digitized is crossed, this is the fundamental problem which limits the precision. In the proposed system, this ambiguity is removed. In fact, if, as in FIG. 2b, the level of the signal to be digitized has been crossed, the rollback counts a bit of fine significance. If, as in figure 2c, the level of the signal to be digitized has not been crossed, the system continues and counts one more significant bit, but the voltage will only cross the threshold again after a number of steps equivalent to a high order bit. The difference between these two cases is therefore only a low order bit.

During the first phase (coarse coding) the amplitude of the signal S1 is regularly increased, at each clock pulse, by a quantity A such that the product 2n1. A (where 2n1 represents the maximum number of clock pulses during this first phase) represents the maximum level to be digitized. During the second phase (fine coding) the amplitude of the signal S1 is regularly decreased, at each clock pulse, by a quantity B less than A, such as 2n2. B = A for 2n2 represents the maximum number of pulses that can include the second phase).

FIG. 3 differs from FIG. 1 in that it makes it possible to obtain a linear load for the most significant bits without having too large pulses on the diode pump. The output voltage is therefore reinjected at the foot of the diode D1, after passing through an impedance adapter 9 having an infinite input impedance and a zero output impedance.

In order not to apply too high a voltage to the differential input of the comparator, a diode 10 limits this voltage to an acceptable value.

According to the second embodiment which is the subject of FIG. 4, the signal S1 is in the form of ascending or descending ramps obtained by means of an integrator formed for example by means of an operational amplifier 10 looped back by means of 'a capacitor 11. As previously, the signal to be digitized S is compared with the signal S1 thus generated in a comparator 4 and, depending on the result of the comparison, a decision logic 3 selects the direction, ascending or descending, from the ramp to. generate, this by means of a part of a selection circuit 12 of the coding type (coarse or f, n) capable of supplying clock pulses of two types (positive or negative) to the integrator ( 10, 11), and on the other hand two switches 13 and 14 forming two possible inputs of this integrator.

The circuit 12 for selecting the type of coding (coarse or fine) moreover ensures, for each clock pulse H, either incrementation (in the case of coarse counting) or decrementation (in the case of end counting of a. counter 13 which supplies, at the end of the fine counting, the digitized signal SN.
RESET also prepares the following cycle by means of a switch I. This process appears in FIG. 5 showing the shape of the signals S and S1, as well as the incrementing pulses of the counter 13 on the one hand during the coarse counting phase, and on the other hand during the fine counting phase.

It is possible to generalize the principle described by considering a signal S1 exhibiting a variation over time as shown for example in FIG. 6, making it possible to successively implement coarse coding, medium coding and fine coding, the slope signal S1 being inverted at each type of coding.

The types of coding thus implemented successively are moreover not limited to 2 or 3, but can be of any number, as shown for example in FIG. 7, which makes it possible to approach the signal to be digitized in one step. shorter.

In such cases, the result obtained at the end of each type of coding is alternately subtracted or added to the previous result.

Furthermore, the coding device according to the invention is self-calibrating. In fact, it suffices to code the same voltage on the one hand according to the method described above, on the other hand by deferring the decision logic of the large weights by one clock step, and to use the increase as well measured by the fine weights to know the amplitude of this heavy weight walk.

It is thus possible to measure in calibration the amplitude of each most significant step; this maneuver can also be repeated for each of the ramps and thus ensure: - that all the steps of a ramp are identical; - that they are in the appropriate amplitude ratio with the immediately neighboring weight ramp; - that all the ramps are in a suitable ratio.

Claims (5)

1. An analog-digital coding device of the duration modulation type, capable of coding an analog input signal (S) on "n" bits, characterized in that it comprises: - first means (1, 2, 3, 4, 5, C0, D1, D2, C1, C2) to perform a first analog-digital conversion on "n1 ,, bits (with nl <n), or" coarse "conversion, by counting the number of pulses of a clock signal (H) until the level of the signal S to be digitized by a locally generated signal S1, the amplitude of which is regularly increased, at each clock pulse; second means (1, 3, 4, 6, 7, C'0, D3, D4, C2) for performing a second analog-to-digital conversion on "n2" bits (with n2 = n - n1), or "fine" conversion, by counting the number of clock pulses until the level of the signal S to be digitized is crossed, in the descending direction, by the same signal S1, the amplitude of which then decreases regularly, at each i m clock pulse, and from the level acquired at the end of the first conversion; - third means (8) for subtracting from the digital result on nl bits, supplied by the first means and representing high order bits, the digital result on n2 bits supplied by the second means and representing low order bits, these third means providing the digitized signal sought. 2. Device according to claim 1, characterized in that the growth or decrease of the signal S1 takes place discontinuously, in stages. 3. Device according to claim 1, characterized in that the growth or decrease of the signal S1 takes place continuously. 4. Device according to one of claims l, 2 or 3, characterized in that the number of successive increases and decreases of the signal S1 is greater than two, the result obtained at the end of each corresponding coding phase being then alternately subtracted or added to the result obtained at the end of the previous phase. 5. Device according to one of the preceding claims, characterized in that it is self-calibrating by measuring the elementary amplitude of variation of the signal S1 during one of its growth or decrease phases, by performing two codings. successive of the same signal S, the considered growth or decrease phase of one of these codings being delayed with respect to the other by a clock pulse, and by measuring the increase thus obtained during the next decay or growth phase.