FR2587817A1 - Addressable interface multiplier - Google Patents

Abstract

The present invention relates to an interface multiplier able to be connected between an output 2-3 of a microcomputer and a plurality of peripherals 10-17. The interface multiplier comprises at least one switch 25, 26, 29 capable of interconnecting, according to an address sent by the microcomputer to the interface multiplier, the output 2-3 of the microcomputer with any one or more of the peripherals 10A-B to 17A-B from among the plurality of peripherals. The interface multiplier being addressable allows interconnection between a microcomputer and a plurality of peripherals without address decoders.

Description

Addressable interface multiplier
The present invention relates to the connection between a microcomputer and a plurality of various peripherals which can be printers, screen-keyboards, measuring devices, displays. etc.

In computers, either an output per device is provided, or an interface multiplier is interposed between the computer and the peripherals which sends the output of the computer, associated with an address, to all the connected peripherals, each device comprising an address decoder which determines whether the output associated with this address concerns it or not. In the case of a microcomputer which, more often than not, only outputs one output, only the second solution of the interface multiplier is possible. In this case, however, each device must have an address decoder. As a result, the peripherals that can be associated with the microcomputer by means of an interface multiplier are necessarily of a complex and expensive type.

The object of the present invention is to provide a multi-interface multiplier capable of being connected between an output of a microcomputer and a plurality of peripherals, characterized in that it incorporates at least one switch capable of interconnecting as a function of an address sent by the microcomputer to the interface multiplier, the output of the microcomputer with any one or more of the peripherals among the plurality of peripherals.

Consequently, with the invention, the switching orders are included in the program, the peripherals are trivialized and the very cost of the whole apparatus is lower because it is possible to work slower, leaving the microcomputer being programmed
According to another characteristic, several micro-computers # are connected as inputs to the same interface multiplier, each of said microcomputers being, as a function: of the address sent by it to the interface multiplier, interconnected with the any one or more of the plurality of peripherals.

risk.

The interface multiplier comprises a read-only memory in which the identification data of the peripherals corresponding to the addresses are recorded, a microprocessor which receives the inputs, checks the identification signal of the interface multiplier, locks the flip-flops controlling the interrogation of the memory and control by the output of the read-only memory corresponding to the address closing of the contactor (s) sending the input to the output terminals corresponding to the peripheral address.

The invention will be described below in the form of an embodiment with reference to the appended drawing which represents the diagram of an interface multiplier associating a microcomputer with eight ripllZriques.

The multiplier # of interfaces according to the invention comprises a microprocessor 1 with two reception terminals.

tion 2 and transmission 3 connected to the microcomputer.

The read-only memory 4, which has as many addresses as there are served peripherals, eight in the example shown, is connected to the microprocessor by an eight flip-flop switch 5 controlled by a door 6 from the microprocessor to send the address by one of the conductors 7 to the read-only memory 4 which returns to the microprocessor by the conductors 8 the data corresponding to said address. As a function of said data, the microprocessor i emits an output on one of the eight terminals aa to 9h.

In the embodiment shown, the devices are connected to the groups hrarllen lo to 17 corresponding to eight channels and comprising a transmission terminal lOA to 17A, a reception terminal 10B to 17B and a ground terminal lOC e 17C yes is not shown for all groups.

The peripherals include two displays connected to keys 10 and 11, three peripherals of the printer or display console type which receive the same information and yes or may not be addressed simultaneously, these three peripherals being connected to channels 12, 13 and 14 and three other independent peripherals which can be any and even possibly other interface multipliers which are connected to the V # iS 15, 6 and
The terminals 9a and 9b control an electronic switch 18 which establishes contact between one or more of the transmission terminals loA-llA of the channels 10 and 11 and the output 19 of the microprocessor, the terminals loB, llB being supplied by the transistors 20 under the control of outputs 21 and 22 of microprocessor 1.

The receiving terminal 2 is connected by 23 to an input of the microprocessor and by 24 to the six
two of those electronic switches 25 and 26.

The transmission terminal 3 is connected by 27 on the microprocessor and by 28 to the inputs of an electronic switch 29.

The electronic switches 25 and 26 are controlled by the outputs on terminals 9c to 9h of the microprocessor and their outputs thus connected to the reception terminal 2 is sent to terminals 12A to 17A of channels 12 to 17 via d 'a dibde 30.

The electronic switch 29 is controlled by the outputs on the terminals 9f at 9h of the microprocessor and, via two NOR gates. 31 with three inputs, via outputs 9c to 9e of the microprocessor.

 The outputs are connected, for those controlled by 9f to 9h, to terminals 15B to 17B of channels 15 i 17 and for that controlled by 9c to 9e by two triple NAND 32 gates to terminals 12B to 14B of channels 12 to 14, the terminals 12B to 17B being protected by diodes 33.

The interface multiplier further includes polarization terminals at + 5V. 34 and a clock at 6MHz 35.

The message from the microcomputer comprises an identification of the interface multiplier which gives rise to a return signal and an address which is sent by the address decoder to the read-only memory.

Claims (3)

1. An interface multiplier capable of being connected between an output (2-3) of a microcomputer and a plurality of peripherals (10-17), characterized in that it comprises at least one switch  (25, 26, 29) capable of interconnecting according to an address sent by the microcomputer to the interface multiplier the output (2-J) to the microcomputer with any one or more of the peripherals (1OA -B to 17A-B) among the plurality of peripherals. 2. An interface multiplier according to claim 1 characterized in that several microcomputers are connected as input on the same interface multiplier, each of said microcomputers being, as a function of the address sent by it to the multiplier interfaces, interconnected with any one or more of the plurality of devices.  3. An interface multiplier according to any one of claims 1 and 2 characterized in that it comprises a read-only memory (4 in which are recorded the identification data of the peripherals corresponding to the addresses, a microprocessor (1) which receives the inputs, checks the identification signal of the interface multiplier, closes the flip-flops (5) controlling the interrogation of the memory and commands by the output of the read only memory (4) corresponding to the address the closing of the or contactors  (25 to 29) sending the input to the output terminals (1OA-B to 17A-B) corresponding to the address device.