FR2582892A1 - Detection device with delay and integration in phase - Google Patents

Abstract

The present invention relates to a detection device with delay and integration in phase. This device comprises detectors A1, B1, C1, D1; A2, B2, C2, D2... arranged in rows and columns. Means of storing charges C are associated with each detector and the detectors of a given row receive the same point of the image sequentially. A shift register 1 addresses each column of detectors sequentially. Means delay the information output by the detectors of a given row in order to sum them in synchronism. These means consist of a charge transfer device 2 associated with each row of detectors, which receives sequentially on a given connection 7 the information stored by the detectors of a given row, these charge transfer devices not being positioned between the rows of detectors and each charge transfer device having its output sent back to its input E2 so as to reinject into the device the item of information previously received from a detector in phase with the item received from the next detector in the same row.

Description

DETECTION DEVICE WITH DELAY
AND EPJTEGRATION IN PHASE
The present invention relates to a detection device with delay and phase integration.

 According to the prior art, such devices are known which generally comprise several linear arrays of detectors, parallel to each other. There is a relative movement between the detectors and the image to be analyzed, that is to say that the detectors of the same line receive sequentially the same point of the image to be analyzed. We sum in synchronism with the scrolling the information collected on the different detectors.

 This type of device is known in Anglo-Saxon literature under the name of "Time Delay Integration" or TDI. It allows the integration time to be multiplied by a factor N equal to the number of detectors on each line. As the reading noises are added in a quadratic way, a gain on the signal to noise ratio equal to sound is obtained.

 In the prior art, there is generally between each line of detectors a charge transfer shift register, the lateral inputs of which receive the signals delivered by the detectors of the same line. This register ensures the synchronous addition of the signals from the detectors of the same line.

 The problem that arises is that these registers with lateral inputs, placed between the detector lines, are very bulky.

 This problem is particularly critical when the detection device is used in the infrared. In this spectral range, the flux of photons received by the device is considerable and the same is true of the number of electrical charges to be conveyed in each register. We are therefore led to increase the width of the registers in order to be able to store all the charges.

 The present invention solves this problem.

 According to the invention, one no longer uses registers with lateral inputs placed between the detector lines. A charge transfer device is used for each line of detectors which is connected by a single connection, or possibly by two connections, to the detectors which makes it possible to place this device, outside the photosensitive zone, elsewhere than between the lines of detectors.

Thus, there is more space at the photosensitive zone which allows for example to increase the integration time of the charges and therefore to improve the performance of the device.

 On the other hand, in the prior art, the shift registers with lateral inputs placed between the detector lines adopted the same pitch for their stages as the pitch between detectors. According to the invention, the charge transfer devices are no longer placed between the lines of detectors which makes it possible to fix the pitch of their stages without taking account of the pitch between detectors. In some cases, it may be necessary to use a pitch of 25 micrometers between stages of the device while Se pitch between the detectors is 100 micrometers. This reduces the length of the charge transfer devices, and therefore their size. Transfer efficiency is improved.

The present invention relates to a detection device with delay and phase integration comprising detectors arranged in rows and columns, charge storage means being associated with each detector, and the detectors of the same line sequentially receiving a same point of the image, means delaying the information coming from the detectors of the same line to add them in synchronism, characterized in that:
- a shift register sequentially addresses each column of detectors;
- said information delaying means consist of a charge transfer device associated with each line of detectors, which receives information stored by detectors on the same line sequentially on a same connection, these charge transfer devices not being not positioned between the detector lines and each charge transfer device having its output returned to its input so as to re-inject into the device the information previously received from a detector in phase with that received from the following detector of the same line.

 The present invention relates to a detection device with delay and phase integration which can be used both in the visible spectrum and for detecting, for example, X-rays or infrared radiation.

 The following description will be made in the particular case of sensitive devices in the infrared in the spectral band 8 - 12 micrometers where the problem previously stated is particularly critical.

Other objects, characteristics and results of the invention will emerge from the following description, given by way of nonlimiting example and illustrated by the appended figures which represent;
- Figure 1 I diagram of an embodiment of a detection device with delay and phase integration according to the invention;
- Figure 2, a top view of an embodiment in integrated form of the different elements associated with each detector
- Figure 3, a top view of an embodiment in integrated form of the load transfer device associated with each line of detectors
- Figures 4a to d, and 6a a 'e sectional views through the devices of Figures 2 and 3 and diagrams illustrating the operation of these devices;
- Figures Sa to i, diagrams of different clock signals applied to the device according to the invention;
- Figure 7, the diagram of another embodiment of a detection device with delay and phase integration according to the invention;
- Figure 8 a top view of another embodiment in integrated form of the charge transfer device associated with each line of detectors
- Figures 9a to h, the diagrams of different clock signals applied to an embodiment of the device according to the invention.

 In the different figures, the same references designate the same elements, but, for reasons of clarity, the dimensions and proportions of various elements are not observed.

 FIG. 1 schematically represents an embodiment of a detection device with delay and phase integration according to the invention.

The device of Figure 1 has only two lines of four detectors designated by the references A1 B1, C1 D1 and A2
B2, C2, D2.

 It is understood that the device according to the invention comprises, concretely, a multitude of lines, for example 200 lines, each line comprising numerous detectors, for example 8 detectors.

 The detectors A1, B1 C1, D1, A2, B2 C2, D2 are arranged in rows and columns.

 In the case of infrared detection, the detectors are produced on a semiconductor substrate different from that on which the other elements are produced, such as C, T1, T2 and the device 2 in FIG. 1.

 At the upper part of FIG. 1, we have indicated by an arrow, going from left to right, I sense the relative scrolling of the image to be analyzed in front of the detectors.

 Each point of the image to be analyzed is therefore seen successively by the detectors A1, B1 C1 then D1 for the lower line and A2 B2 C2 then D2 for the upper line.

Each detector is associated with:
- means for storing the charges symbolized in FIG. 1 by a capacities C;
an element for injecting the charges of the detectors into the capacities C which is symbolized by MOS T2 transistors. These transistors T2 are connected between a detector and a terminal of each capacitor C, the other terminal of the capacitor C being at ground or at a constant potential. The gates of the T2 transistors associated with the detectors of the same line are connected to each other and receive a control voltage which leaves these transistors conductive for at least part of the reading time;
- a switch element - controlled by a shift register 1 which sequentially addresses each column of detectors.

This switch element is symbolized in FIG. I by a MOS transistor T1. These transistors T1, except the one associated with the last detector, are connected between the terminal of each capacitor
C which is not grounded and a common connection to the detectors of the same line and connected to an input E1 of the charge transfer device 2 associated with this line. The gates of the transistors T1 are controlled by the outputs R1, R2 R3 R4 of register 1.

 Outside the photosensitive zone, there are the charge transfer devices 2 associated with each line of detectors.

 To reduce the bulk, the load transfer devices 2 can be staggered.

 The operation of these devices will be explained in detail with the description of Figures 2 to 6.

 We see in Figure 1 that each charge transfer device 2 has its output connected to a second input E2. The information previously received from a detector is thus re-injected into the device in phase with that received from the following detector on the same line. It can also be seen in FIG. 1 that the information coming from the detectors D1 and D2 is directly linked to the output of the charge transfer devices 2 associated with each row of detectors.

 FIG. 2 is a top view of an embodiment in integrated form of the various elements connected to each detector and which are symbolically represented in FIG. 1 by the MOS transistors T1 and T2 and the capacitor C.

 In FIG. 1, only the elements connected to the detectors A1, B1, C1 and D1 of FIG. 1 have been represented.

 At the top of Figure 2, there are shown metal contacts 3 connected to the detectors A1 B1, C1 and D1 which are not shown. In the case of infrared radiation, these detectors are generally photo-diodes.

 Each contact 3 is connected to a diode dl integrated in a semiconductor substrate 4 through an opening 5 made in the insulator 6 protecting the surface of the semiconductor substrate.

 Figure 4a - left side - is a sectional view along the axis a a 'indicated in Figure 2 where the elements 3, 4, d are shown which have just been discussed.

 Following the diodes there are two gates G1 and G2 which receive constant bias voltages YGî and VG2, then gates G3 which as seen in Its figure 2 are specific to each detector. Isolation zones d ensure the transfer of charges from a given detector under the grids G1 and G2 then under the grid G3 specific to this detector.

VGI bias voltages and
VG2 pulsed.

 For example, the integration time of the charges can be adapted in the event of over-illumination by passing the voltage V, 1 to the low level.

 Likewise, the voltage VG2 can be lowered to improve the charge transfer.

 The gates G3 are controlled by the outputs R1, R2, R3 R4 of register 1.

 After the gates G3, there is a diode d2 associated with each detector. A connection 7 connects, through openings 8 through the oxide layer 6, the diodes d2 associated with the detectors of the same line, except the last diode D1, to an input E1 of the charge transfer device 2 associated with this line of detectors.

 FIG. 3 is a top view of an embodiment in integrated form of the charge transfer device 2 associated with each line of detectors.

 FIG. 3 represents an embodiment of the device 2 using a known method of injecting the charges into a charge transfer device. Various variants of the device 2 can be used by modifying the way in which the charges are injected, which results in slight structural modifications.

 As seen in Figure 1, this device has two inputs E1 and E2. FIGS. 4a - right part - and 6a are sectional views along the axes b b 'and c c' which show the structure of the inputs of the device 2.

 The inputs E1 and E2 each have a diode d3 and d4 followed by a series of MOS capacitance grids.

 Diode d3 is connected to connection 7. It is followed by a grid G4 brought to a constant potential VG4.

The diode d4 receives a bias voltage Vd4, pulsed and represented in FIG. Si. It is followed by a gate G5 which receives by the connection 9 the output voltage of the device 2, and by a gate G6 which receives a bias voltage constant VG6
We see in Figure 3 that after the gates G4 G5 and G6 the two inputs E1 and E2 still have a pair of gates specific to each input and then pairs of gates located on a single channel where the charges from the two inputs open E1 and
E2. These pairs of gates receive clock signals in phase opposition Q11 and t shown in Figures Se and -f.

 The charge transfer device shown in FIG. 3 also comprises an output diode d6 connected to a reading stage comprising a reading capacity C1 a MOS transistor for resetting to zero T3 of the capacity which receives a clock signal ~ R shown in FIG. 5g and a constant bias voltage V The output diode d, is also connected to a charge reading device consisting of two MOS transistors T4 and T5 mounted as a follower which deliver an output signal S.

This output signal S can be re-injected towards the input E2 by
I'm via connection 9 or sent to the device output.

 This alternative is symbolized in FIG. 3 by a switch which receives the clock signal #L represented in FIG. 5h.

 The charge transfer device 2 of FIG. 3 also includes a diode d5 followed by a grid G7 at a constant potential VG7 which allows the injection of charges coming from the last detector D1.

 The case of a P-type substrate is taken as an example in the description, to which control voltages are applied which when positive are high.

 Figures 4b to ci and 6b to e illustrate the operation of the device according to the invention and represent the potentials in the semiconductor substrate at different times.

 FIG. 4b shows the integration under the grid G2 of charges coming from the detector D1. The charges injected through the diode dl cross the channel located under the grid G1 and accumulate in a storage well located under the grid G2.

FIG. 4c shows the transfer of the charges stored under the grid G2 in the charge transfer device. This transfer is triggered by the modification of the potential applied to the gate G3 connected to the output R1 of register 1 and which receives the voltage VR1. In the figures Sa to ci, the voltages on the outputs R1 to
R4 of register 1. The passage from R1 to the high level allows the transfer of the charges towards the diode cri3 and the gate G4.

 The transition to the high level of ~ 1 allows the transfer of these charges to the rest of the device 2.

 In FIG. 4ci, ~ 2 is at the high level and ~ 1 is at the low level.

Charges are transferred under a couple of electrodes connected to
FIG. 6b represents the potentials in the substrate at a time when the signal Vd4 is at the low level. The gate G5 receives by the connection 9 the signal available at the output of the device 2. The signal is at low level.

 FIG. 6c represents the potentials at a time when the signal Vdrr is at the high level.

 The amount of charge stored under the gate G6 is a direct function of the signal transmitted by the connection 9.

 FIG. 6d represents the potentials in the substrate at a time when the clock signal ~ 1 is at the high level. The charges stored under the gate G6 are transferred under a pair of electrodes receiving the signal ~ 2 and then under a pair of electrodes receiving the signal ~ 1- - see Figure 6e.

 In Figures Sa to i, the voltages VR1 VR2 VR3, VR4 available on the outputs R1 to R4 of the register 1 are represented, then the clock signals ~ 1 and # 2 which transfer to the charge transfer devices 4 the signals ~ R and ~ L applied at the output of the registers 2 and the signal Vd4 applied to the diode dq.

 It should be noted that in Figures Sa to i as in Figures 9a to h, the voltages vary between a high level and a low level which may correspond to different values.

It can be seen that the signals VR1 and VR4 are merged. This is due to the fact that the signals from the last detectors D1, D2,
D3 ... do not pass through the charge transfer device. It is therefore possible, while the signals from these detectors are sent to the output of the register, to send to the input E1 of the register the signals from the first detectors A1, A2, A3 ...

 The signal ~ L which is represented in FIG. 5h when it is at the low level produces the transfer of the signal S on the connection 9 so that this signal is re-injected towards input E2.

 When the signals from the detectors A1, Bt, C1 have been delayed and summed in the charge transfer device 2, sign it! ~ L goes high. This passage from ~ L to the high level takes place while the signal VR4 has passed from the high level to the low level.

There is then available on the diode d5 the signal coming from the detector D1 and on the diode d cumulative signals of the detectors A1 B1, C1, D1 for the same point of the image. The resulting signal S is transmitted to the outside of the charge transfer device.

 The signal ~ R which is represented in FIG. 5g goes to the high level after the passage from XL to the low level.

 To obtain satisfactory operation, it is necessary to simultaneously adapt the values of different parameters such as the number of stages of the charge transfer devices 2, the operating frequencies of the register 1, of the devices 2, the speed of scrolling of the image. .

 In the case of FIGS. 1 to 6, the information coming from the detector A1 is transferred to the device 2 and re-introduced on the entry E2 in synchronism with the arrival on the entry E1 of the information coming from the detector B1 corresponding to the same point of the image.

There is summation in the device 2 of information coming from the detectors A1 and B1. This cumulative information is again transferred to device 2, and re-entered on the input
E2 at the same time as the input E1 receives the information coming from the detector C1 for the same point of the image.

 There is summation in the device 2 of information coming from the detectors A1, B1 and C1.

 The information coming from the detectors A1, B1 and C1 are added together with the information coming from the detector D1 for the same point of the image which is injected directly at the output of the device on the diode ci5.

 There is therefore a signal S, which is the sum of the information delivered by the detectors Al, B1, C1 and D1, of the same line for the same point of the image. This signal S is transmitted outside the charge transfer device 2.

 It is understood that the charge transfer devices 2 simultaneously process the information from the detectors of the same line concerning various points of the image.

 Figures 7 to 9 illustrate various variants of the device described above.

 FIG. 7 represents the diagram of an embodiment of the device according to the invention.

 This diagram differs from that of FIG. 1 in particular because only one line of detectors A1, B1 C1 and D1 has been shown, but also because it comprises two variants which will be explained in the following.

One of the variants consists in passing the information coming from the last detector through the charge transfer device 2
D1.

This modification leads to modification of the control signal
VR4 which is shown in Figure 9d. The signal VR4 is no longer confused with the signal VRî. It can be seen in FIGS. 9a to d that the signals VR1 VR2 VR3 and VR4 sequentially go high.

 This variant leads to increasing the number of stages of the charge transfer device 2 so that the information coming from the various points of the image is not confused in the register.

 Thus, for example, charge transfer devices 2 comprising 10 stages can be used when the information from detectors D1, D2, D3, etc. is sent directly to the output of these devices. Whereas when the information of these detectors passes through the devices 2, 13 stages must be used.

 Another variant of the device in FIG. 7 relates to the interposition of a charge reading stage between the input E1 of the charge transfer device 2 and the connection 7 which sequentially conveys the information coming from the detectors of the same line.

 This reading stage comprises a capacity C2 for storing the charges transmitted by the connection 7. The charges accumulated on the capacity C2 are converted into voltage by means of an amplifier made up of two transistors T6 and T7. These two transistors are for example MOS transistors connected in series.

The entry is made on the gate of T6 which receives on one of its electrodes a constant bias voltage V8. The transistor T7 is connected to ground. Its grid receives a constant bias voltage V7. It is the point common to the transistors T6 and T7 which constitutes the output of this amplifier connected to the input E1 of the device 2.

 A MOS transistor T8 allows periodic resetting of the capacitor C2. This transistor receives on its gate the clock signal JR represented in FIG. 9g. One of its electrodes receives a constant bias voltage V6 and which also controls the transistor T3 connected to the output of the device 2.

 In FIG. 8, there is shown a top view of an embodiment in integrated form of the charge transfer device associated with each line of detectors.

 This embodiment of the device 2 is used in the case of FIG. 7 where a reading stage precedes the device 2.

 In this case, the two inputs E1 and E2 of the device 2 are identical and similar to the input E2 of the device in FIG. 3.

 The inputs E1 and E2 therefore comprise two diodes d3 and d4 which receive a bias voltage Vd4. Each of these diodes is followed by a grid G4 and G5. The grid G4 follows the diode d3. This grid G4 is connected to the output of the reading device constituted by the transistors T6 and T7.

 Grid G5 follows diode d4.

 As in the case of FIG. 3, this grid G5 is connected by connection 9 to the output of the device 2.

Grids G4 and G5 are followed by a grid G6 brought to a constant voltage VG6
The inputs E1 and E2 have in this embodiment the same type of operation as that of the input E2 as shown in Figures 6a to 6e.

 The advantage of this embodiment is that the use of an amplification stage before the input of the device 2 makes it possible, if a gain less than 1 is used, to reduce the quantity of charges to be conveyed by the devices 2.

 We thus manage to further reduce the size of the charge transfer devices 2.

 In FIGS. 9a to h, the clock signals VRI to VR4 are shown, then ~ 1, @ 2, @R and VD4. As already explained, the embodiment of Figures 7 and 8, causes a modification of the signal VR4 which is no longer confused with VR1.

 It has been reported that the device according to the invention can be used both in the visible spectrum and for detecting infrared radiation.

 In the case of visible detection, the detectors are photodiodes or / and photo-MOS. These detectors are associated with storage means which can be constituted by the detectors themselves.

 For example, to be used in the visible the device of Figure 2 must be modified.

 The gates G1 and the diodes d1 are deleted. The rest of the device of Figure 2 does not have to be modified.

The detectors -may be constituted by photo-MOS constituted by the G2 grids or by photo-diodes preceding photo-MOS constituted by the G2 grids or only by photo
MOS formed by G2 grids.

Claims (8)

 1. Detection device with delay and phase integration comprising detectors (A1, B1 C1 D1 A2 B2, C2 D2 ...) arranged in rows and columns, charge storage means (C) being associated with each detector, and the detectors of the same line receiving sequentially a same point of the image, means delaying the information coming from the detectors of the same line to add them in synchronism, characterized in that:  - a shift register (1) sequentially addresses each column of detectors;  - said information delaying means consist of a charge transfer device (2) associated with each line of detectors, which sequentially receives on a same connection (7) the information stored by the detectors of the same line, these devices charge transfer not being positioned between the detector lines and each charge transfer device having its output returned to its input (E2) so as to re-inject into the device the information previously received from a phase detector with that received from the next detector on the same line.  2. Device according to claim 1, characterized in that the information stored by the storage means associated with the detector (D1, D2, D3 ...) D3 "~) of each line receiving last point of the image is sent directly to the output of the charge transfer device (2) associated with this line of detectors.  3. Device according to one of claims 1 or 2, characterized in that the detectors are photo-diodes (A1, B1 C1 ... A2, B2 ...), each photo-diode being connected to a first diode (dl) integrated in a semiconductor substrate (4), followed by two grids (G1, G2) of a grid (G3) controlled by said shift register (1) and a second diode (ci2) connected by a connection (7) to the charge transfer device (2) associated with each line of detectors.  4. Device according to one of claims 1 or 2, characterized in that it is used for the detection of visible radiation and in that the detectors are photo-ciiodes or / and photo-MOS each detector being connected to a grid (G2) which can be part of the detector which is followed by a grid (G3) controlled by said shift register (1) and by a diode (ci2) connected by a connection (7) to the transfer device load (2) associated with each line of detectors.  5. Device according to one of claims 1 to 4 characterized in that each charge transfer device (2) has a first and a second input (E1 and E2), the first input (E1) being connected to said connection ( 7) and the second input (E2) receiving the output voltage of the device.  6. Device according to claim 5, characterized in that a charge reading stage (T6, T7) is interposed between said connection (7) and the charge transfer device (2) associated with each line of detectors.  7. Device according to claim 5, characterized in that the first input (E1) comprises a diode (ci3) integrated in the semiconductor substrate (4) which is connected to said connection (7) and a second input (E2) comprising a diode (cri4) receiving a pulsed voltage (Vd4) followed by a grid (G5) receiving the output voltage of the device and then by another grid (G6) which receives a constant bias voltage.  8. Device according to claim 6, characterized in that each charge transfer device has first and second inputs (E1, E2) with a diode (d3, d4) which receives the same pulsed voltage (ci4), followed by a first grid (G4 G5) and by a second grid (G6) one of these first grids (G4 G5) being connected to the output of the reading stage associated with each line of detectors and the other first gate receiving the output voltage of the charge transfer device (2), while the second gate (G6) receives a constant bias voltage (VG6)