FR2588140A1 - Detection device with in-phase summation of signals - Google Patents

Abstract

Detection device with in-phase summation of the signals coming from several detectors. The signals coming from the same row of detectors A1, B1, C1, D1 are addressed to the input E1 of the same charge-transfer circuit 2 with lateral outputs, where the information signals, coming from the successive detection of a same point by the detectors of the row, are delayed so as to be added together in synchronism. Application to any detection effected by means of rows of detectors.

Description

 Detection device with phase accumulation of signals.

 The present invention relates to a detection device comprising a set of individual detection elements and means making it possible to delay and accumulate in phase the signals detected by the detection elements and relating to a view to be analyzed; the term seen here has a very broad meaning and includes any source or reflector of radiation as well, for example, in the field of visible light as in that of X-rays or infrared.

 Such devices are known; they generally comprise several linear arrays of detectors, parallel to each other, constituting a detection matrix of n rows and p columns. There is a relative movement between the detectors and the view to be analyzed, that is to say that the detectors of the same line receive sequentially the same point of the view to be analyzed. The information collected on the various detectors is summed in synchronism with the scrolling.

This type of device is known in the Anglo-Saxon literature under the name of "Time Delay Integration" or TDI. It allows the integration time to be multiplied by a factor N equal to the number of detectors on each line. As the reading noises are added in a quadratic way, these devices bring a gain, on the signal to noise ratio, equal to
V
In the prior art, between each line of detectors is generally arranged a load transfer shift register, the lateral inputs of which receive the signals delivered by the detectors of the same line. This register ensures the addition, in synchronism, of the signals from the detectors of the same line.

 The problem that arises is that these registers with lateral inputs, placed between the detector lines, are very bulky.

 This problem is particularly critical when the detection device is used in the infrared. In this spectral range, the flux of photons received by the device is considerable and the same is true of the number of electrical charges to be conveyed in each register. This therefore leads to significant widths of registers in order to be able to store all the charges.

 The object of the present invention is to reduce the size of the devices located at the detection zone level, thus allowing greater resolution of the image.

 This is obtained, in particular, by using, as delay and phase accumulation means, charge transfer circuits arranged outside the photosensitive zone of the detectors.

 According to the present invention, a detection device with phase accumulation, comprising: nxm detectors arranged in n rows and m columns (n and m: positive integers), the detectors of the same row detecting sequentially the same point of an image to analyze; n x m charge storage means, associated respectively with the n x m detectors; n delay means, coupled respectively to the n lines, for delaying the information coming from the detectors of the same line in order to allow them to be added in synchronism, is characterized in that it comprises a shift register for sequentially addressing each column of detectors, and in that the delay means respectively comprise n charge transfer circuits, each charge transfer circuit receiving sequentially on the same connection the information signals supplied by the detectors of the line to which it is coupled, the charge transfer circuits being positioned outside the n lines and having lateral outputs coupled together to allow the synchronization of the information signals received by the circuit.

 It should be noted that, in a patent application filed less than a year before this document (priority dates), it is also proposed to solve the congestion problems by using charge transfer circuits, but circuits load transfer whose structure, less well suited to the problem, makes their control more difficult.

 The present invention will be explained in more detail with the aid of the description below relating more particularly to devices sensitive to infrared radiation; with these radiations the number of photons to be detected is very large, which makes all the more critical, in known devices, the problem of the size of the charge transfer shift registers.

Other objects, characteristics and results of the invention will emerge from the following description, given by way of nonlimiting example and illustrated by the appended figures which represent;
- Figure 1, the diagram of an embodiment of a detection device with phase accumulation according to the invention
- Figure 2, a top view of an embodiment, in integrated form, of the various elements associated with each detector of Figure 1;
- Figure 3, a top view of an embodiment, in integrated form, of an element of the charge transfer circuits of Figure 1;
- Figures 4a to 4d sectional views through the elements of Figures 2 and 3 and diagrams illustrating the operation of these elements;
- Figures 5a to 5g, diagrams of different clock signals applied to the device according to the invention;
- Figure 6 the partial diagram of an alternative embodiment of a device according to the invention.

 In the different figures, the same references designate the same elements and, for reasons of clarity, the proportions of the various elements are not always respected.

 In the various diagrams, the precise synchronization devices, which are part of current technology, have not been shown in order to make the drawings clearer and to simplify the description.

 FIG. 1 schematically represents an embodiment of a detection device with delay and phase accumulation according to the invention.

 The detection device of FIG. 1 has two lines of four detectors designated by the references Ai, B1, Cl, D1 and A2, B2, C2, 22.

In reality the device which served as an example for this description
tion included 300 lines of 8 detectors each and these detectors, sensitive in the infrared domain, were produced on an HgCdTe semiconductor while the rest of the circuit was produced on p-type silicon; to simplify the drawing, the detection device according to FIG. 1 has only two lines of four detectors each.

 The detectors Al, Bl, Cl, Dl, A2, B2, C2, D2 are arranged in four columns, Al-A2, Bl-B2, Cl-C2, Dl-D2.

 In the upper part of FIG. 1, an arrow, f, going from left to right, indicates the direction of the relative scrolling of the image to be analyzed in front of the detectors.

Each point of the image to be analyzed is therefore seen successively by the detectors Ai, Bl, Cl, DI for the bottom line and A2, B2, C2,
D2 for the upper line.

Each detector such as AI is associated with:
- means for storing charges, symbolized by a capacity C, the first terminal of which is grounded;
- an element for injecting the detector charges into the capacity
C, which is symbolized by an MOS transistor, T2. This transistor T2 connects the detector to the second terminal of the capacitor C. The gates of the transistors, such as T2, associated with the detectors of the same line, are connected to each other and receive a control voltage which leaves these transistors conductive permanently;
- a switch element controlled by a shift register, 1, which sequentially addresses each column of detectors. This switch element is symbolized, in FIG. 1, by a MOS transistor,
T1. This transistor T1 connects the second terminal of the capacitor C to the first end of a connection, 7, common to the detectors of the same line.

 A shift register, 1, has four outputs Ri, R2, R3, R4 which control the gates of the transistors such as T1 associated with the same column, such as A1-A2.

 Outside the photosensitive zone, that is to say the zone of the detectors, are arranged charge transfer circuits, all identical, such as 2, associated one to one with each line of detectors; the association is made by connecting their input, such as El, to the second end of the connections, such as 7.

 The operation of the injection, storage and charge transfer circuits will be explained in detail using FIGS. 2 to 5.

 Each charge transfer circuit, such as 2, has as many lateral outputs as there are detectors per line, that is to say four lateral outputs in FIG. the summation, symbolized by conductors linked together, of the signals available on these outputs, produces the sought signal, which appears on a sum output such as SI.

 Figure 2 is a top view of an embodiment in integrated form which shows the different elements associated with each detector and symbolically represented in Figure 1, by the MOS transistors such as T1 and T2 and the capacitance such as C In this figure, only the part relating to the detectors A1, B1, Cl and DI of FIG. 1 has been represented.

 At the top of FIG. 2, four metal contacts, such as 3, are respectively connected to the detectors A1, B1, Cl and- Dl; these detectors are not shown in FIG. 2 but, by way of identification, their reference is written on the metallic contact which corresponds to them. In the case of the example which served for the description and where the radiation was infrared radiation, the detectors used were photo-diodes.

 Each contact, such as 3, is connected to a diode, such as dl, integrated in a semiconductor substrate 4 through an opening 5 made in the insulating oxide layer 6 protecting the surface of the semiconductor substrate on which is realized the circuit. The left part of Figure 4a is a sectional view along an axis a 'indicated in Figure 2; this view shows the elements 3, 4, 6, dl which have just been mentioned.

 Still on FIG. 2 and on the left-hand side of FIG. 4a, it appears that the diode dl is followed by two grids, G1 and G2, which respectively receive constant bias voltages VG1 and VG2, then another grid, G3 .; the two grids G1 and G2 are common to all the elements of the same row, and the grid G3 is common to the elements of the same column. Isolation zones, such as d, ensure the transfer of charges, coming from a given detector, under the grids such as GI, G2, then G3 specific to this detector.

The grids, such as G3, are controlled by that of the outputs
R1, R2, R3, R4 of register 1, which corresponds to the column of detectors with which the grid in question is associated.

 After each grid, such that G3 is a diode d2 associated with each detector. Thanks to openings such as 8, drilled through the oxide layer 6, the connection 7, already indicated in FIG. 1, connects the diodes, such as d2, associated with the detectors of the same line, at the input El of the charge transfer device 2 associated with the line of detectors considered.

 Figure 3 is a top view of an embodiment in integrated form, of a charge transfer circuit, such as 2 (Figure 1), associated with each line of detectors; the right part of FIG. 4a completes this view with a sectional view along an axis bb 'indicated in FIG. 3.

 The input El comprises a diode d3 connected to the connection 7 and followed by a series of grids of MOS capacities; the diode d3 is followed by a grid G4 brought to a constant potential VG4.

 After the gate G4, the structure comprises pairs of gates receiving clock signals in phase opposition, Xl and # 2 shown in FIGS. 5e and 5f and whose frequency is 1 MHz.

 Figure 3 also shows two of the side outputs of the charge transfer circuit. Each of these outputs consists of a grid, such as G5, and a diode, such as d4. The grids of the different outputs are connected together and brought to a potential VS. The diodes, such as d4, are connected together by a connection 9 which constitutes the signal output of the charge transfer circuit. The potential VS is shown in Figure 5g; these are niches of tension.

 Figures 4b to 4d illustrate the operation of the device according to the invention and represent the potentials, in the semiconductor substrate, at different times.

FIG. 4b shows the integration, under the gate G2, of charges coming from the detector D1. The charges injected through the diode corresponding to the diode dl (Figures 2 and 4a) but relating to the detector
D1, cross the channel located under the G1 grid and accumulate in a storage well located under the G2 grid.

 FIG. 4c shows the transfer of the charges stored under the gate G2, in the charge transfer circuit. This transfer is triggered by the modification of the potential applied to the gate G3 connected to the output R1 of the register 1 and which receives the voltage VRI.

Figures Sa to 5d represent the voltages on the outputs RI to
R4 of register 1. The passage of the output R1 to the high level allows the transfer of the charges towards the diode d3 and the grid G4.

 The passage to the high level of the clock signal ~ 1 allows the transfer of these charges to the rest of the charge transfer circuit.

 In the case of FIG. 4d, the clock signals #l and # 2 are respectively at the low level and at the high level; this results in a transfer of charges under the pair of electrodes receiving the signal ~ 2.

At each new period of the signals Qll and 4) 2 the charges coming from the detector A 1 are transferred step by step in the charge transfer circuit; during this transfer the charges coming from the detector 131 are injected into the input of the charge transfer circuit then transferred in their turn; charges from detectors
Cl then D1 are transferred in the same way behind the charges coming from the detector B1. The charge transfer circuit therefore contains in its wells the succession of signals from the detectors Al, B1
Cl and D1.

 Thus, when an image point arrives in front of the detector D1, it has been detected successively by the detectors Al, B1 and Cl and the corresponding signals are present in the charge transfer circuit. It then suffices to read these signals by means of the lateral outputs and to add them to obtain the output signal.

où N est le nombre de détecteurs par ligne, t1 le temps entre deux lectures de l'image par un détecteur, t2 le temps mis par un point d'image pour se déplacer d'un détecteur au suivant.The charge transfer circuit must have a sufficient number of stages to store all this information; the number of floors required is

where N is the number of detectors per line, t1 the time between two readings of the image by a detector, t2 the time taken by an image point to move from one detector to the next.

For example, for N = 4, t2 / tl = 4, the number of stages of the circuit is 52.

 The lateral outputs of the charge transfer circuit, N in number, are positioned at the first stage and the last stage, the others being regularly distributed along the circuit.

 A variant of the device according to the invention consists in interposing between the connection, such as 7, and the charge transfer circuit, such as 2, of each line, an amplifier whose role is to convert the electrical charges into a potential. FIG. 6 represents a possible diagram of such an amplifier as well as of the input stage of the charge transfer circuit.

FIG. 6 shows that, in this variant, the connection 7 is connected to a MOS transistor, T10, used for updating the connection 7 and to two MOS transistors, T11 and T12 mounted in follower amplifiers; the transistor T10 connects the connection 7 to a DC voltage source VIl of 10 volts and the control voltage, V10, of its gate is a reset pulse; transistors T11 and T12 are mounted between two DC voltage sources V13 and V14 respectively of 0 volts and +15 volts and their gates are respectively connected to a DC voltage source V12 of 0 volts and to connection 7, while their common terminal is connected to the input of a charge transfer circuit capable of receiving a signal in the form of a voltage. The charge transfer circuit, only part of which is shown in FIG. 6, comprises a diode d3 'followed by a series of MOS capacitance grids: G4 ', then G6 ... The gate G4' receives the signal from the transistor
T12 and the diode d3 'receives a signal Vi formed of a succession of pulses synchronized with the arrival of the signal on the gate G4'; the G6 grid is polarized at a constant VIS potential of 5 volts. The rest of the charge transfer circuit is not shown; it is identical to that which is shown in FIG. 3, from the elements which, in this FIG. 3, follow the grid G4.

 The variant according to FIG. 6, thanks to the gain amplifier less than 1, Tll-T12, which it implements, has the advantage of making it possible to reduce the dimensions of the charge transfer circuit in cases where a minimum size is sought.

Claims (4)

 1. Detection device with phase accumulation, comprising: nxm detectors (Al, 131, Cl, D1, A2, B2, C2, D2) arranged in n rows and m columns (n and m: positive integers), detectors d '' the same line detecting sequentially the same point of an image to be analyzed; n x m storage means (C) of charges, associated respectively with the n x m detectors; n delay means, respectively coupled to the n lines, for delaying the information coming from the detectors of the same line in order to allow them to be added in synchronism, characterized in that it comprises a shift register (1) for sequentially addressing each column of detectors, and in that the delay means respectively comprise n charge transfer circuits (2), each charge transfer circuit receiving sequentially on the same connection (7) the information signals supplied by the detectors of the line to which it is coupled, the charge transfer circuits being positioned outside the n lines and having lateral outputs coupled together to allow the synchronization of the information signals received by the circuit.  2. Device according to claim 1, characterized in that it comprises, in series from the electrical point of view, between each detector (A1) and the input (El) of the charge transfer circuit (2) associated with the line (A1, B1, Cl, D1) of which the detector in question is a part: a first diode (dl) specific to the detector considered, a first grid (G1) and a second grid (G2) specific to the line of the detector considered, a third grid (G3) specific to the column of the detector considered and controlled by the shift register (1), a second diode (d2), the connection (7) specific to the detector considered.  3. Device according to claim 2, characterized in that the elements, in series from the electrical point of view between each detector and the input of the charge transfer circuit associated with the line of which the detector in question is part, are integrated on a semiconductor substrate (4).  4. Device according to any one of the preceding claims, characterized in that the charge transfer circuits (2) are preceded by an amplifier (Tll-T12) with a gain less than 1.