FR2560409B1 - Unite arithmetique pour additionner des bits paralleles - Google Patents

Unite arithmetique pour additionner des bits paralleles

Info

Publication number
FR2560409B1
FR2560409B1 FR8403068A FR8403068A FR2560409B1 FR 2560409 B1 FR2560409 B1 FR 2560409B1 FR 8403068 A FR8403068 A FR 8403068A FR 8403068 A FR8403068 A FR 8403068A FR 2560409 B1 FR2560409 B1 FR 2560409B1
Authority
FR
France
Prior art keywords
arithmetic unit
parallel bits
adding parallel
bits
arithmetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8403068A
Other languages
English (en)
Other versions
FR2560409A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LARDY JEAN LOUIS
Original Assignee
LARDY JEAN LOUIS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LARDY JEAN LOUIS filed Critical LARDY JEAN LOUIS
Priority to FR8403068A priority Critical patent/FR2560409B1/fr
Publication of FR2560409A1 publication Critical patent/FR2560409A1/fr
Application granted granted Critical
Publication of FR2560409B1 publication Critical patent/FR2560409B1/fr
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
    • G06F7/607—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers number-of-ones counters, i.e. devices for counting the number of input lines set to ONE among a plurality of input lines, also called bit counters or parallel counters

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Physics (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
FR8403068A 1984-02-28 1984-02-28 Unite arithmetique pour additionner des bits paralleles Expired FR2560409B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8403068A FR2560409B1 (fr) 1984-02-28 1984-02-28 Unite arithmetique pour additionner des bits paralleles

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8403068A FR2560409B1 (fr) 1984-02-28 1984-02-28 Unite arithmetique pour additionner des bits paralleles

Publications (2)

Publication Number Publication Date
FR2560409A1 FR2560409A1 (fr) 1985-08-30
FR2560409B1 true FR2560409B1 (fr) 1989-05-19

Family

ID=9301492

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8403068A Expired FR2560409B1 (fr) 1984-02-28 1984-02-28 Unite arithmetique pour additionner des bits paralleles

Country Status (1)

Country Link
FR (1) FR2560409B1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2599528A1 (fr) * 1986-05-29 1987-12-04 Centre Nat Rech Scient Additionneur bipolaire et multiplieur binaire bipolaire comprenant au moins un tel additionneur
FR2599526A1 (fr) * 1986-05-29 1987-12-04 Centre Nat Rech Scient Additionneur mos et multiplicateur binaire mos comprenant au moins un tel additionneur
EP0721159A1 (fr) * 1995-01-03 1996-07-10 Texas Instruments Incorporated Additionneur binaire à entrées multiples

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2417139A1 (fr) * 1978-02-08 1979-09-07 Adersa Multiplieur-sommateur perfectionne
FR2469836A1 (fr) * 1979-11-16 1981-05-22 Hennion Bernard Systeme de codage et decodage a multiniveaux en courant

Also Published As

Publication number Publication date
FR2560409A1 (fr) 1985-08-30

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Legal Events

Date Code Title Description
ST Notification of lapse