FR2551247A1 - Rewritable non-volatile integrated memory, method of manufacturing this memory and device for writing thereto. - Google Patents

Abstract

Rewritable non-volatile integrated memory, method of manufacturing this memory and device for writing thereto. This memory comprises a plurality of MOS transistors T1, T2, T3, T4 whose dielectric layers 3, interposed between the gates G and the substrate 2, are contaminated by alkaline ions trapped at the gate-dielectric interfaces (high state) or at the dielectric-substrate interfaces (low state). These two states correspond to two different threshold voltages for the transistors. The ions pass from the high (low) state to the low (high) state or remain in the latter by heating of the transistors and simultaneous application of a positive (zero) voltage between their gates and the substrate. Application to the construction of information processing devices.

Description

 The present invention relates to a rewritable non-volatile integrated memory, a method of manufacturing this memory and a device for writing to it. It applies in particular to the production of information processing devices.

 We know rewritable non-volatile integrated memories, more commonly called REPRON memories. These memories comprise a plurality of MOS transistors which can be made conductive by penetration of electrons in the insulating dielectric layers separating their gates from their semiconductor substrate. Such memories are erasable by subjecting the transistors to intense and prolonged ultraviolet radiation, allowing the electrons to leave the thickness of the dielectric layers. It is then possible to rewrite in the memories considered, that is to say to program them again.

 Such memories have the following drawbacks: the erasing and rewriting operations of these memories are carried out one after the other. In addition, the erasure of such a memory requires a special machine comprising an intense source of ultraviolet radiation and requires the disassembly and extraction of this memory from the system of which it is a part, then are reassembled in the system, once reprogrammed. Erasing and rewriting these memories known in the state of the art are therefore long and costly operations.

 The object of the present invention is precisely a rewritable non-volatile integrated memory which does not have the above drawbacks, in particular that its erasure and its rewriting can be carried out simultaneously, in a simple and very rapid manner, in less than a minute. , or even in seconds, without having to dismantle the system memory of which it is a part.

 Specifically, the subject of the present invention is a rewritable non-volatile integrated memory, of the type which includes a plurality of MOS transistors produced on a semiconductor substrate, each MOS transistor comprising a conductive layer intended to constitute the gate of the transistor and formed on an insulating dielectric layer, itself formed on the substrate, memory characterized in that each dielectric layer is contaminated by alkaline ions trapped in one of two stable high and low positions, respectively constituted by the grid-layer interface dielectric and by the dielectric layer-substrate interface, the two positions corresponding to two different threshold voltages for each MOS transistor, making it possible to read the memory by means of an electric voltage applied to the gates of the MOS transistors and chosen in a field included between the two threshold voltages.

The semiconductor substrate can be of the type
N, the MOS transistors then being at P channel, or of P type, the MOS transistors then being at N channel. In addition, the integrated memory according to the invention can have all kinds of known configurations for MOS memories, for example a XEPROM type configuration.

 The memory object of the invention is called wreinscriptiblew or wreprogrammable because it is possible to erase its content and replace it with another by passing the alkaline ions corresponding to certain transistors from one position to another and leaving possibly the alkaline ions corresponding to other transistors at their position, by heating the memory while applying suitable electrical voltages between the gates of the transistors and the substrate.

 According to a particular characteristic of the integrated memory which is the subject of the invention, the alkaline ions are taken from the group comprising the Na + ions and the K + ions. Of course, other alkaline ions could be used.

 The present invention also relates to a method for manufacturing the rewritable non-volatile integrated memory also subject of the invention, method comprising the fabrication of the MOS transistors on the substrate, this fabrication of the MOS transistors itself comprising a step of forming the dielectric layers then a step of forming the grids on these dielectric layers, a method characterized in that it further comprises a step of contamination of the dielectric layers with alkaline ions after the step of forming the dielectric layers.

 According to a particular embodiment of the process which is the subject of the invention, the contamination is carried out by immersing the substrate provided with the dielectric layers in a heated liquid solution containing the alkaline ions.

 According to another embodiment of the process which is the subject of the invention, the contamination is carried out by forming the grids by evaporation of a metal placed in contact with an electrical conductor heated by an electric current, the metal and / or the conductor (that is to say either the metal or the conductor, or both), being contaminated by the chemical species corresponding to said alkali ions.

 The present invention finally relates to a device for writing into the rewritable non-volatile integrated memory also subject of the invention, characterized in that it comprises means for heating the memory, and means for applying positive electrical voltages or null between the gates of the MOS transistors and the substrate, so that for any given MOS transistor, the corresponding alkaline ions can pass from the high position to the low position or remain in the latter position, by heating of the MOS transistor and simultaneous application of '' a positive electric voltage between the grid of the latter and the substrate, or can pass from the low position to the high position or remain in the latter, by heating the MOS transistor and simultaneous application of a zero electric voltage between the grid of it and the substrate.

 According to a particular characteristic of the invention, the alkaline ions are Na + ions, the substrate is made of silicon and the heating temperature is of the order of 1500C to 2000C.

 According to another particular characteristic, the alkaline ions are R + ions, the substrate is made of silicon and the heating temperature is of the order of 2500C to 300 C.

 According to another particular characteristic, said positive electric voltage is of the order of 1V to 5V.

 Finally, according to another particular characteristic, the heating means comprise a thermoelectric element with Peltier effect.

The present invention will be better understood on reading the description which follows, of exemplary embodiments given by way of non-limiting example, with reference to the appended figures in which
FIG. 1 is a schematic view of an integrated memory according to the invention, formed on an N-type semiconductor substrate and comprising a plurality of MOS transistors located in different logic states,
FIG. 2 is a schematic view of the memory shown in FIG. 1, in which certain transistors have retained their logic state and others have changed logic state,
- Figure 3 is a graph showing the variation of the threshold voltage of a MOS transistor forming part of the memory shown in Figures 1 and 2, when the corresponding alkaline ions pass from the gate-dielectric layer interface to the dielectric layer-substrate interface of said transistor,
FIG. 4 is a schematic view of an integrated memory according to the invention, formed on a P-type semiconductor substrate and comprising a plurality of MOS transistors in different logic states,
FIG. 5 is a schematic view of the integrated memory shown in FIG. 4, in which certain transistors have remained in their logic state and others have changed in logic state,
- Figure 6 is a diagram showing the variation of the threshold voltage of a memory transistor shown in Figures 4 and 5 when the corresponding alkaline ions pass from the gate-dielectric layer interface to the dielectric layer interface- substrate of said transistor,
FIG. 7 is a schematic view of a particular mode of implementation of a fundamental step in the manufacture of an integrated memory according to the invention,
FIG. 8 is a diagrammatic view of another particular embodiment of this fundamental step, and
- Figure 9 is a schematic view of a particular embodiment of the writing device object of the invention.

 In FIG. 1, a rewritable non-volatile integrated memory according to the invention is shown diagrammatically. It comprises a plurality of MOS transistors formed on a semiconductor substrate 2, made of N-type silicon for example. Four of these transistors T11 T2, T3, T4 are shown in FIG. 1. Each transistor is P-channel and includes an insulating dielectric layer 3 formed on the substrate 2, a conductive layer G intended to constitute the gate of the transistor and formed on the dielectric layer 3, a source S (of type P), a source electrode 4, a drain D (of type P) and a drain electrode 5. The dielectric layer is for example made of SiO2, Si3N4 or Al203 . The gate G is for example made of a metal such as aluminum or of highly doped silicon.

 Of course, the integrated memory shown in FIG. 1 also includes interconnections between the transistors as well as various electronic circuits not shown.

The dielectric layers 3 are contaminated with alkaline ions. For some transistors
T3, T4, the alkaline ions are trapped at the interface between the grid G and the dielectric layer 3, an interface that can be called "high position" of the alkaline ions, while for other transistors T1, T2, the alkaline ions are trapped at the interface between the dielectric layer 3 and the substrate 2, an interface which can be called "low position" of the alkaline ions.

 As will be seen later, during the manufacture of the integrated memory shown in FIG. 1, the alkaline ions are trapped in the high position and can then migrate into the dielectric layer to become trapped in the low position and then return to the high position, subject to certain conditions.

 In Figure 3, there is shown, for a given transistor of the memory shown in Figure 1, the variations of the drain-source current IDS as a function of "VG, where VG denotes a negative voltage applied between the gate and the substrate of said transistor, in case H where the corresponding alkaline ions are in the high position and in case B where the alkaline ions are in the low position. It can be seen that the threshold voltage VSB corresponding to the alkaline ions in the low position is less than the threshold voltage VSH corresponding to the alkaline ions in the high position, these two voltages being of course both negative. This is explained by the fact that the sign of the alkaline ions is positive and that, to repel the electrons from the substrate, it is necessary apply a higher voltage to the grid in absolute value when the ions are in the lower position than when they are in the high position.

 It follows that one can read the integrated memory shown in Figure 1 by applying to the gates of the transistors which compose it a negative voltage VF belonging to a domain between the two threshold voltages VSB and VSH. One can for example take for VF the average of these two threshold voltages. For a transistor whose corresponding alkaline ions are in the high position, the quantity -VF is greater than the quantity -VsH and there is then a non-zero IDS drain-source current. We then say that the transistor considered is in the logic state 1. On the contrary, for a transistor whose corresponding alkaline ions are in the low position, the quantity VF is less than the quantity -VsB, the drainsource current IDS is zero and l 'we then say that the transistor considered is in logic state 0.

In FIG. 2, the same memory is shown schematically as that which is represented in FIG. 1, this memory being rewritten. The following four possible cases have been considered: transistor T1 remains in logic state 0; the transistor
T2 goes from logic 0 to logic 1; transistor T3 goes from logic 1 to logic 0 and transistor T4 remains in logic 1.

 The content of the memory corresponding to FIG. 1 is replaced by the content of this memory corresponding to FIG. 2 is carried out as follows: the memory is heated as a whole and during this heating, voltages VE are applied between the grids of the different transistors and the substrate. For transistors of type T or T3, the applied voltage VE is positive and for transistors of type T2 or T4, the applied voltage VE is zero. Indeed, for alkaline ions, the high position is more stable than the low position.

 The application of a zero VE voltage allows ions in the high position to remain there and ions in the low position to migrate through the dielectric layer in the direction of the high position. Applying a positive VE voltage repels alkaline ions which are positive ions and allows those in the high position to migrate through the dielectric layer towards the low position and those in the low position to stay there.

FIGS. 4, 5 and 6 relate to an integrated memory according to the invention, the only difference from which is shown in FIGS. 1 and 2 in the substrate which is of type P instead of being of type N, the transistors then being channel
N instead of being at P channel. In FIG. 6, the variations of the drain-source current IDS are represented as a function of the positive voltage VG established between the gate of such an N channel transistor and the substrate, in case H where the alkaline ions are in the high position and in case B where the alkaline ions are in the low position. The threshold voltage VSH corresponding to the ions in the high position is positive and greater than the threshold voltage VSB also positive, corresponding to the ions in the low position. Indeed, the voltage to be applied to the gate of an N-channel transistor to repel the holes in the substrate when the ions are in the low position and weaker than when they are in the high position.

 The memory can then be read according to the invention shown in FIGS. 4 and 5 by means of a positive voltage VF chosen in a domain comprised between the two positive threshold voltages VSB and VSH, the voltage VF being for example equal to the average of these two threshold voltages. For an N-channel MOS transistor whose corresponding alkaline ions are in the low position, the application to the gate of said transistor of such a positive voltage VF allows the circulation of a drain-source current IDS and it is then said that the transistor is in logic state 1.

On the contrary, when applying the positive voltage VF to the gate of an N-channel transistor whose corresponding alkaline ions are in the high position, there is no IDS drain-source current flowing and it is said that the transistor considered is in logical state 0.

The passage from FIG. 4 to FIG. 5 corresponds to the change in the content of the memory according to the invention shown in these figures. The four possible cases are shown: transistor T1 remains in logic state 0; transistor T2 goes from logic 0 to logic 1; the transistor T3 passes from the logic state 1 to the logic state 0 and the transistor T4 remains in the logic state 1. The passage from one content to another of the memory represented in FIGS. 4 and 5 is done as before (Figures 1 and 2), taking into account the current meaning of logic states 0 and 1: the memory is heated as a whole and during this heating, a voltage
Zero VE is applied to transistors of type T (for which the ions remain in the high position) and T3 (for which the ions pass from the low position to the high position) and a positive voltage VE is applied to transistors of type T2 (of which the alkaline ions pass from the high position to the low position) and T4 (whose alkaline ions remain in the low position).

 By way of indication and without limitation, the positive voltage VE considered in the description of FIGS. 1, 2, 4 and 5, voltage which is to be applied between the gates of certain transistors and the substrate, is for example less than or equal to about 5 volts . This value of 5 volts is suitable for the voltage VE, which means that the memory according to the invention is compatible with so-called TTL electronic circuits.

 Also as an indication but not limiting, in the case of Na + ions, the heating of the memory can be carried out between 1500C and 2000C, at l800C and for a few seconds for example; and in the case of K + ions, the heating can be carried out between 2500C and 4000C, for example at 2500C for a few minutes, or between 3000C and 3500C for ten seconds. It is of course possible to use higher temperatures, the heating times then being reduced. The advantage of K ions over Na + ions is that they are more stable near room temperature.

 Figure 7 is an explanatory diagram of a method of manufacturing the integrated memory object of the invention. This process is identical in all respects to the techniques of MOS-VLSI Microelectronics, except that, after the formation of the insulating dielectric layers 3 on the substrate 2, these dielectric layers being intended to receive the conductive grid layers, the wafer 6 formed by the substrate 2 provided with said dielectric layers 3 is immersed in a liquid solution 7, contained in a container 8 and heated to about 800C for example, of an alkaline salt corresponding to said alkaline ions.

Then, we proceed to the deposition of the grid material by any known method: evaporation by Joule effect, electron beams ... (then the sources, the drains and the ohmic contacts of these sources and these drains are formed). The sources and the drains could possibly be formed before immersing the plate 6 in the solution 7 and therefore before the grids are formed, as is the case in certain known techniques.

 In the case of K + dions, a KOH solution can be used, for example. In the case of Na ions, a solution of NaCl or NaOH can be used, for example: an NaCl solution containing, for example, from 0.01 to 1 mole of NaCl per liter, at 800C, is used, in which the wafer 6 is immersed for approximately 30 minutes.

 FIG. 8 illustrates another way of producing the memory according to the invention: after the substrate 2 has been provided with insulating dielectric layers 3, the material (a metal for example) intended to constitute the grids, is deposited after having been previously contaminated with the chemical species corresponding to said alkaline ions. To do this, one can for example mount the wafer 6 on a support 9 in an enclosure 10 in which a vacuum has been created.

A metallic filament 11 in the form of a solenoid is placed in the enclosure above the wafer 6, and supplied by an electric current source 12.

A mask 13, comprising openings intended to delimit the grids to be formed, is interposed between the filament ll and the plate 6. Wires 14 made of the metal to be deposited are placed in the solenoid whose filament follows the shape. This metal can thus be evaporated by the Joule effect by contaminating the filament 11 beforehand. When the latter is heated, the metal melts, wets the filament, becomes contaminated on contact and evaporates to then deposit on the dielectric layers 3, through the mask 13. Instead of contaminating the filament, the wires 14 of metal (or even the filament and the metal to be deposited) could be directly contaminated. Said contamination is for example carried out by contact of the filament and / or metal wires to be deposited with sodium or a solution of sodium chloride in the case of ions
Na +, or by contact with potassium or a solution of potassium chloride in the case of K + ions. Traces of contaminant are enough.

 In Figure 9, there is shown schematically a writing device in the integrated memory according to the invention. This device comprises memory heating means 15 and means 16 for applying positive or zero electrical voltages between the gates of the MOS transistors and their substrate. As is known in the prior art, the memory according to the invention is mounted in a housing 17 from which contact pins emerge 18. The heating means 15 consist for example of a thermoelectric element with Peltier effect powered by a current source 19 and placed on the housing 17.

The means 16 for applying electrical voltages are known in the state of the art and make it possible to selectively apply, between the gates of the memory transistors according to the invention and the substrate, either a positive VE voltage or a zero voltage. . To do this, the case 17 is mounted on a plate 20 provided with a plurality of electrical connectors 21 with which the pins 18 are brought into contact, said connectors 21 themselves being suitably connected to the means 16 for applying said voltages. After which, the expected voltages are applied to the gates of the transistors, while heating the memory.

 The thermoelectric element 15 could be permanently mounted on the case 17.

Furthermore, instead of a Peltier thermoelectric element, other heating means could be used such as an intense light source. Finally, considering a shoemaker 17 mounted on an electronic card, there is not even a need to extract the box 17 from its electronic card, provided that the latter includes the electrical connections required to properly connect the means 16 to the memory according to the invention. Indeed, heating means such as a thermoelectric element with an effect
Peltier are localized heating means making it possible to heat the shovel 17 in place on its electronic card, without heating any other element of this card.

Claims (10)

 1. Integrated non-volatile rewritable memory, of the type which includes a plurality of MOS transistors (T1, T2, T3, T4) produced on a semiconductor substrate (2), each MOS transistor comprising a conductive layer (G) intended to constitute the transistor gate and formed on an insulating dielectric layer (3), itself formed on the substrate, memory characterized in that each dielectric layer (3) is contaminated by alkaline ions trapped in one of two stable high positions and low, respectively constituted by the gate-dielectric layer interface and by the dielectric layer-substrate interface, the two positions corresponding to two different threshold voltages (VSH, VSB) for each MOS transistor, making it possible to read the memory by means an electric voltage (VF) applied to the gates (G) of the MOS transistors and chosen in a range between the two threshold voltages.  2. Integrated memory according to claim 1, characterized in that the alkaline ions are taken from the group comprising Na + ions and K ions  3. A method of manufacturing the rewritable non-volatile integrated memory according to claim 1, method comprising the fabrication of the MOS transistors on the substrate (2), this fabrication of the MOS transistors itself comprising a step of forming the dielectric layers (3) then a step of forming the gates (G) on these dielectric layers, process characterized in that it further comprises a step of contamination of the dielectric layers (3) with alkaline ions after the step of forming the dielectric layers.  4. Method according to claim 3, characterized in that the contamination is carried out by immersing the substrate (2) provided with the dielectric layers (3) in a heated liquid solution (7) containing the alkaline ions.  5. Method according to claim 3, characterized in that the contamination is carried out by forming the grids (G) by evaporation of a metal (14) placed in contact with an electrical conductor (11) heated by an electric current, the metal and / or the conductor being contaminated by the chemical species corresponding to said alkaline ions.  6. Device for writing into the rewritable non-volatile integrated memory according to claim 1, characterized in that it comprises means (15) for heating the memory, and means (19) for applying electrical voltages (VE ) positive or zero between the gates (G) of the MOS transistors and the substrate (2), such that for any given MOS transistor, the corresponding alkaline ions can pass from the high position to the low position or remain in the latter, by heating the MOS transistor and simultaneous application of a positive electric voltage between the gate of the latter and the substrate, or can move from the low position to the high position or remain in the latter, by heating the MOS transistor and simultaneous application a zero electrical voltage between the grid thereof and the substrate.  7. Device according to claim 6, characterized in that the alkaline ions are ions Na +, in that the substrate (2) is made of silicon and in that the heating temperature is of the order of 1500C to 2000C.  8. Device according to claim 6, characterized in that the alkaline ions are ions K, in that the substrate (2) is made of silicon and in that the heating temperature is of the order of 2500C to 3000C.  9. Device according to any one of claims 6 to 8, characterized in that said positive electric voltage is of the order of 1V to 5V.  10. Device according to any one of claims 6 to 9, characterized in that the heating means (15) comprise a thermoelectric element with Peltier effect.