FR2545957B1 - - Google Patents

Info

Publication number
FR2545957B1
FR2545957B1 FR8307793A FR8307793A FR2545957B1 FR 2545957 B1 FR2545957 B1 FR 2545957B1 FR 8307793 A FR8307793 A FR 8307793A FR 8307793 A FR8307793 A FR 8307793A FR 2545957 B1 FR2545957 B1 FR 2545957B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8307793A
Other languages
French (fr)
Other versions
FR2545957A1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EFCIS
Original Assignee
EFCIS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EFCIS filed Critical EFCIS
Priority to FR8307793A priority Critical patent/FR2545957A1/fr
Publication of FR2545957A1 publication Critical patent/FR2545957A1/fr
Application granted granted Critical
Publication of FR2545957B1 publication Critical patent/FR2545957B1/fr
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52Multiplying; Dividing
    • G06F7/523Multiplying only
    • G06F7/533Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804Details
    • G06F2207/386Special constructional features
    • G06F2207/3884Pipelining

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
FR8307793A 1983-05-10 1983-05-10 High-throughput binary multiplier Granted FR2545957A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR8307793A FR2545957A1 (en) 1983-05-10 1983-05-10 High-throughput binary multiplier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8307793A FR2545957A1 (en) 1983-05-10 1983-05-10 High-throughput binary multiplier

Publications (2)

Publication Number Publication Date
FR2545957A1 FR2545957A1 (en) 1984-11-16
FR2545957B1 true FR2545957B1 (de) 1989-01-13

Family

ID=9288750

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8307793A Granted FR2545957A1 (en) 1983-05-10 1983-05-10 High-throughput binary multiplier

Country Status (1)

Country Link
FR (1) FR2545957A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2611286B1 (fr) * 1987-02-23 1989-04-21 Dassault Electronique Circuit integre multiplieur, et son procede de composition

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4189767A (en) * 1978-06-05 1980-02-19 Bell Telephone Laboratories, Incorporated Accessing arrangement for interleaved modular memories

Also Published As

Publication number Publication date
FR2545957A1 (en) 1984-11-16

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Legal Events

Date Code Title Description
ST Notification of lapse