FR2545623A1 - Programmable timer - Google Patents

Abstract

High-accuracy programmable timer with very low consumption characterised in that it uses a first oscillator 1 which operates continuously and oscillates at a very low frequency F1, and a second oscillator 2 which is set into operation only during short time intervals and oscillates at a much higher frequency F2. The first oscillator 1 is used as a clock and sends pulses periodically to a counter 6 while the second oscillator 2 serves for synchronisation and resets the frequency of the first oscillator. The combination of the two oscillators and a logic control system 3, 4, 5, 7 is capable of delivering a signal after a time predetermined by the filling of the levels of the counter 6. Application to horology or diverse timing systems for example for the self-ignition of mines or rockets.

Description

 The present invention relates to an electronic timer device which, by its electronic design, can be miniaturized and whose operation requires only a reduced amount of energy.

 Up to now, there have been a large number of timers produced using mechanical or electronic means. Programmable electronic timers have appeared recently, using dividers produced by large-scale integration technology known as o controlled by a quartz clock. These timers, which already show significant progress in terms of the energy savings they provide, nevertheless require a relatively large amount of energy. This amount of energy is often an increasing function of precision.

 The main advantage of the present invention, also based on the use of oscillators, is to program time durations with very high precision while requiring only a very low operating energy. The device, capable of delivering a signal when a time which has been determined in advance has elapsed, can be used for various needs: for military purposes for self-priming mines or rockets ..., or for commercial purposes (watchmaking, various timings, etc.).

 In principle, the present invention uses two oscillators. The first, which can be of the "capacity resistance" oscillator type, is always in operation and oscillates at a very low frequency f @ (for example around 1 Hz). The second, which can be of the quartz oscillator type, is operated only during certain time intervals and for short periods of time. It oscillates at a higher frequency P2, for example of the order of 32 KHz.

 The first oscillator is used as a clock and sends pulses periodically to a counter. It is at this counter and by prior filling of the internal levels of the counter that programming is done.

 The second oscillator serves as synchronization, it controls and "readjusts the frequency of the first oscillator.

 The set of two oscillators added to a logic control system is capable of delivering a signal after the predetermined time by filling the levels of the counter.

 By design, such a programmer does not require a high-precision "capacity resistance" oscillator since its frequency is automatically corrected by the secondary quartz oscillator.

 The use of a low frequency treks for the oscillator of the "capacity resistance" type and the sequential operation of the quartz oscillator mean that the assembly, object of the present invention, requires for its operation only very little energy. in fact, in this kind of technology used, consumption is directly proportional to frequency.

Other characteristics and advantages of the invention will be better understood on reading the description which will follow made with reference to the accompanying drawings in which
FIG. 1 of plate I is a block diagram of the various elements constituting a possible embodiment of the invention,
Figure 2 of Plate II shows in detail an example of a circuit corresponding to the general diagram of Figure 1
FIG. 3 of plate III gives the shape of the signals at the different points of the circuit of FIG. 2.

 The description of a possible embodiment of the invention is detailed below p with reference to Figure i do plate I.

 Oscillator 1 of the "capacitance resistance" type oscillates on a frequency slightly less than 1 Hz and with an accuracy which may be poor. Oscillator 2 of the b quertz oscillator type oscillates on a high frequency of the order of 32 EEss by design; its oscillation frequency is known with great precision.

 A set 3 made up of a pulse divider element and a decoder sends pulses to oscillator 2 which will be used to start or stop oscillator 2.

 A logic comperator 4 which divides the pulses from oscillator 2 and compares them to the pulses from oscillator 1.

 It outputs a signal whose duration is a series of pulses, the number of which is proportional to the error over the period of oscillator 1.

This period must always have, whatever its drift, a value greater than its ideal value such that the error over time would be zero
This same signal is sent to a corrector 5. The corrector 5 divides the number of pulses it receives in order to modify the prior programming and to compensate for the "shifts" in frequency of the oscillator.
Element 6 is composed of a counter which, when its levels are filled will deliver a signal to output 8. This counter 6 receives pulses from element 7 which is composed of an OR gate with three inputs. counter 6 can receive pulses t either from oscillator 1, or from corrector 5, or from the programming unit external to the system.

 The operation of such an embodiment is detailed below.

 The oscillator 1 delivers a signal of low frequency f1, without great stability and always lower whatever its drift to the ideal value f 2, that should have f 1 so that the error on time is zero. Oscillator 2 of frequency F 2 multiple of f 2 and of great stability, is normally blocked. It provides a signal only every N pulses from oscillator 1 during a period t 1 of oscillator 1. Its operation is therefore controlled by the decoder counter 3.

 The comparator 4 then compares the frequencies f 1 and f 2 and supplies the corrector circuit 5 with a number of pulses proportional to the error on f 1. This corrector circuit then sends via the OR gate 7 a series of pulses correcting the display of the output counter 6 which is normally controlled by i through the door 7.

 Programming is done through 7, at a frequency much higher than f 1 and a function of the maximum programming time available. It consists, conventionally, of a prepositioning of the counter 6 by sending a number of pulses complementary to the time to be programmed.

 The maximum programmable time is therefore obtained by using the full capacity of the counter 6.

 A detailed description of a circuit based on this principle and of its operation is described below by way of example with reference to FIGS. 2 and 3.

 it constitutes a programmable time delay from 0 to 24 hours with an accuracy better than 1 min.

 The multivibrator 1 consists of a logic circuit with complementary NOS transistors, provides a signal of frequency f 1 - 0.8 Hz (period t 1 = 1.25 seconds).

 The maximum value of f 1 is f 2 = 1 Hzo This signal appears on output 16 of element i. A double period signal is provided by the annex 17 output.

 The signal from the output 16 is applied to the Og gate 7 from where it attacks the output divider 6 of capacity 217.

 - To the divider 3 of capacity 26 associated with the decoder 28 which makes it possible to obtain a time slot of duration t I at point 18, every 64 periods of the oscillator I.

 Elements 1 and 3 are put into operation by passing the blocking input "26 from logic level" 1 "to logic level" 0 ". The time delay is counted at this instant until the rising edge of the counter 6 output pulse.

 The same decoder 28 on the link with the signal from output 17 provides a signal identical to the signal from 18 but offset by t 1.

 The gate 9 combining these two signals makes it possible to obtain a slot of 1.5 t 1 at 20 (the first half-period serving for the start-up and stabilization of the quartz oscillator 2).

 This quartz oscillator provides in 21 pendant, 5 t 1 a signal at 32 768 Hz after being blocked for 62.5 t 1. This signal attacks a divider 10 of capacity 2 15 (32 768) via gate 11 This divider switches after a time @ 2 = one second (obtained with the precision of quartz), blocking the door there and opening the door 12.

 It therefore appears at 22 only pulses from 2 during the time t 1 - t 2.

 These pulses attack the counter 13 whose rab is to provide the number of pulses necessary to correct the accumulated delay during the 64 periods of oscillation of oscillator 1. The capacity of the counter 13 must therefore be ### ### = 512 or 2 6.

 This counter keeps the rest of the division which will be taken into account during the next correction. At point 23, the circuit 14 pulses the output signal from the counter 13 so that this signal comes to block the door 7 when the counter 13 remains in the high position.

 Gate 15 resets counter 6 to zero when power is applied; elements 1, 3 and 13 are released at the start of the time delay, then no longer undergo a reset, the divider 10 is reset to zero at each correction.

 The OR and AND logic circuits are produced by NOR and NAND circuits.

An example of operation is described below:
- time to program = 3 h 25 min, or 12,300 seconds;
- number of pulses to be introduced during programming - 2 17 - 12 300
= 118,772;
- interval between two slots of oscillator 2 operation =
1.25 x 64 = 80 seconds (if t 1 = 1.25 seconds) p
- oscillator operating time 2 = i, 25 x 1, 5 = 1.875 seconds
- slot width in 24 = 1 second é
- number of pulses in 22 = 32,768 x (1.25 - 1) = 8,192;
- number of corrective pulses = 8,192 = 16.

512
So, at the end of the 64 periods, 16 pulses are added which make it possible to obtain a total of 64 + 16 = 80 pulses corresponding well to the 80 seconds in real time.

 With such a system, the energy consumption can be evaluated as being approximately 34 times lower than the consumption that would require a timer operating continuously.

 Greater precision in programming can be obtained by multiplying the correction sequences (operation of the crystal oscillator). In this case, consumption is also increased.

Claims (4)

 R E V E N D I C A T I O N S  a set of comparator-corrector 4.5 which divides in frequency the signal coming from the second reference oscillator 2 so as to obtain a signal of frequency f 2, compares said signal of frequency f 2 with the signal of frequency f 1 su of the first oscillator 1 and supplies the counter 6 with a number of corrective pulses which compensates for the frequency deviations of the first oscillator 1 with respect to the reference frequency f 2.  a set 3 counter-decoder to which the signal from the first oscillator 1 is applied, said set 3 deliver pulses which periodically start and stop the operation of the second reference oscillator 2, during the time delay, F 2 is a multiple of a frequency f 2, f 2 being chosen so that the real frequency f 9 of the first oscillator 1 always remains, whatever its drift, less than f 2,  - a second reference oscillator 2, the oscillation frequency of which  a first low frequency oscillator 1 sending pulses into the counter at a frequency f 1 throughout the duration of the time delay,  1. High precision programmable timer with very low value including a counter 6 capable of delivering a signal when it has received a determined number of pulses, a direct input on the counter also allowing, thanks to a prior filling of the elements of the counter, to be able to program, characterized in that it includes  2. Timer according to claim 1 characterized in that the first oscillator 1 is of the "resistance-capacitance" type.  3. Timer according to any one of claims 1 or 2 characterized in that the second reference oscillator 2 is of the quartz type.  4. Timer according to all of claims 2 and 3 characterized in that the oscillation frequency of the first oscillator 1 is approximately 1 Hz and the oscillation frequency of the second reference oscillator 2 is of the order of 32 Khz.